Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3204789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

585747

1

T1

1269

T2

4967

T3

149

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3392071	1			T1	1527		T2	6302		T3	461
values[0x0]	197572	1			T1	407		T2	1703		T3	49
values[0x1]	200893	1			T1	383		T2	1833		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2191843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1598693

1

T1

1505

T2

6086

T3

248

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	78971	1			T2	41		T13	39		T15	1
valid_sources[0x01]	11305	1			T1	31		T2	37		T13	42
valid_sources[0x02]	12174	1			T2	51		T13	28		T15	1
valid_sources[0x03]	11165	1			T2	42		T13	53		T15	4
valid_sources[0x04]	11783	1			T2	43		T13	58		T15	3
valid_sources[0x05]	29023	1			T1	11		T2	27		T13	13
valid_sources[0x06]	11029	1			T2	35		T13	23		T15	4
valid_sources[0x07]	14209	1			T2	36		T13	21		T15	5
valid_sources[0x08]	10871	1			T2	41		T13	45		T15	4
valid_sources[0x09]	18267	1			T2	39		T13	69		T15	6
valid_sources[0x0a]	11286	1			T1	12		T2	30		T13	14
valid_sources[0x0b]	12656	1			T2	42		T13	68		T15	5
valid_sources[0x0c]	11692	1			T1	14		T2	37		T13	28
valid_sources[0x0d]	17949	1			T2	42		T13	7		T15	2
valid_sources[0x0e]	10544	1			T2	32		T13	23		T16	10
valid_sources[0x0f]	11861	1			T1	12		T2	31		T13	19
valid_sources[0x10]	16614	1			T1	16		T2	29		T13	54
valid_sources[0x11]	10865	1			T2	35		T13	2		T15	2
valid_sources[0x12]	13688	1			T1	13		T2	32		T13	6
valid_sources[0x13]	24194	1			T1	1		T2	39		T13	97
valid_sources[0x14]	12313	1			T2	28		T3	545		T13	68
valid_sources[0x15]	13123	1			T2	34		T13	9		T15	4
valid_sources[0x16]	11675	1			T1	1		T2	45		T13	31
valid_sources[0x17]	19908	1			T1	1		T2	40		T13	67
valid_sources[0x18]	12065	1			T2	30		T15	10		T16	7
valid_sources[0x19]	11039	1			T2	30		T13	9		T15	7
valid_sources[0x1a]	21625	1			T2	38		T13	42		T16	3
valid_sources[0x1b]	12883	1			T1	49		T2	40		T13	4
valid_sources[0x1c]	11716	1			T2	36		T13	1		T15	14
valid_sources[0x1d]	14562	1			T1	33		T2	29		T13	9
valid_sources[0x1e]	38762	1			T1	25		T2	38		T13	79
valid_sources[0x1f]	21323	1			T2	39		T13	23		T15	10
valid_sources[0x20]	11177	1			T2	46		T13	20		T15	3
valid_sources[0x21]	30998	1			T1	12		T2	38		T13	23
valid_sources[0x22]	42589	1			T2	38		T13	54		T15	6
valid_sources[0x23]	17780	1			T1	18		T2	33		T13	17
valid_sources[0x24]	21349	1			T2	29		T13	82		T15	5
valid_sources[0x25]	12889	1			T1	13		T2	33		T13	97
valid_sources[0x26]	12249	1			T2	48		T13	7		T15	6
valid_sources[0x27]	10991	1			T2	37		T15	4		T16	11
valid_sources[0x28]	12151	1			T2	34		T13	2		T15	2
valid_sources[0x29]	11040	1			T2	34		T13	14		T15	2
valid_sources[0x2a]	16100	1			T1	5		T2	38		T13	16
valid_sources[0x2b]	23868	1			T1	18		T2	39		T13	17
valid_sources[0x2c]	11491	1			T1	30		T2	36		T13	15
valid_sources[0x2d]	11043	1			T1	23		T2	42		T13	4
valid_sources[0x2e]	12196	1			T1	1		T2	26		T13	31
valid_sources[0x2f]	12106	1			T1	19		T2	26		T13	90
valid_sources[0x30]	15934	1			T2	34		T13	53		T15	2
valid_sources[0x31]	12272	1			T1	5		T2	32		T13	65
valid_sources[0x32]	12127	1			T1	9		T2	30		T13	21
valid_sources[0x33]	11075	1			T1	35		T2	37		T13	41
valid_sources[0x34]	49126	1			T2	32		T13	48		T15	4
valid_sources[0x35]	13458	1			T1	11		T2	30		T13	59
valid_sources[0x36]	11795	1			T1	3		T2	39		T15	8
valid_sources[0x37]	13420	1			T1	20		T2	42		T13	79
valid_sources[0x38]	10702	1			T1	32		T2	44		T13	22
valid_sources[0x39]	11165	1			T1	12		T2	42		T13	28
valid_sources[0x3a]	11267	1			T1	1		T2	35		T13	48
valid_sources[0x3b]	11277	1			T2	38		T13	8		T15	5
valid_sources[0x3c]	11860	1			T1	82		T2	36		T13	52
valid_sources[0x3d]	11925	1			T2	36		T13	57		T15	2
valid_sources[0x3e]	35190	1			T2	56		T13	1		T15	7
valid_sources[0x3f]	11527	1			T2	32		T13	13		T15	5
valid_sources[0x40]	11488	1			T2	39		T13	81		T15	6
valid_sources[0x41]	11704	1			T2	24		T13	72		T15	4
valid_sources[0x42]	11629	1			T2	62		T13	43		T15	5
valid_sources[0x43]	12679	1			T2	36		T13	72		T15	2
valid_sources[0x44]	11134	1			T2	36		T13	24		T15	5
valid_sources[0x45]	18584	1			T1	7		T2	51		T13	29
valid_sources[0x46]	13271	1			T1	61		T2	41		T13	41
valid_sources[0x47]	11030	1			T1	2		T2	36		T13	20
valid_sources[0x48]	11514	1			T2	40		T13	96		T16	9
valid_sources[0x49]	12997	1			T2	40		T13	40		T15	3
valid_sources[0x4a]	15159	1			T1	1		T2	42		T13	23
valid_sources[0x4b]	11639	1			T1	77		T2	46		T13	19
valid_sources[0x4c]	11231	1			T1	13		T2	41		T13	84
valid_sources[0x4d]	16137	1			T1	48		T2	32		T13	7
valid_sources[0x4e]	11234	1			T1	22		T2	40		T13	20
valid_sources[0x4f]	16172	1			T1	16		T2	53		T13	65
valid_sources[0x50]	12135	1			T2	43		T13	41		T15	6
valid_sources[0x51]	17679	1			T1	16		T2	32		T13	14
valid_sources[0x52]	16121	1			T1	8		T2	48		T13	23
valid_sources[0x53]	17684	1			T1	11		T2	31		T13	31
valid_sources[0x54]	10663	1			T2	40		T13	26		T15	6
valid_sources[0x55]	12156	1			T1	25		T2	46		T13	54
valid_sources[0x56]	12215	1			T2	38		T13	95		T15	4
valid_sources[0x57]	11241	1			T2	34		T13	7		T15	5
valid_sources[0x58]	14211	1			T2	38		T13	45		T15	6
valid_sources[0x59]	12106	1			T2	44		T13	21		T15	2
valid_sources[0x5a]	11575	1			T2	37		T13	47		T15	2
valid_sources[0x5b]	14060	1			T1	43		T2	46		T13	8
valid_sources[0x5c]	11035	1			T2	52		T13	28		T15	2
valid_sources[0x5d]	11824	1			T1	24		T2	35		T13	35
valid_sources[0x5e]	11292	1			T1	26		T2	34		T13	58
valid_sources[0x5f]	11795	1			T1	4		T2	46		T13	46
valid_sources[0x60]	13565	1			T2	30		T13	35		T15	1
valid_sources[0x61]	16263	1			T2	42		T13	29		T15	4
valid_sources[0x62]	13641	1			T2	35		T13	11		T15	4
valid_sources[0x63]	12017	1			T1	15		T2	38		T13	26
valid_sources[0x64]	13485	1			T2	48		T13	19		T15	6
valid_sources[0x65]	11488	1			T2	37		T13	60		T15	2
valid_sources[0x66]	12505	1			T2	39		T13	90		T15	6
valid_sources[0x67]	12329	1			T2	43		T13	21		T15	4
valid_sources[0x68]	43234	1			T2	54		T13	8		T15	9
valid_sources[0x69]	12703	1			T2	38		T13	16		T15	9
valid_sources[0x6a]	12164	1			T1	12		T2	38		T13	96
valid_sources[0x6b]	13386	1			T2	42		T13	46		T15	3
valid_sources[0x6c]	15538	1			T1	4		T2	47		T13	24
valid_sources[0x6d]	32639	1			T1	32		T2	41		T13	14
valid_sources[0x6e]	12319	1			T2	31		T13	6		T15	5
valid_sources[0x6f]	12225	1			T1	29		T2	44		T13	36
valid_sources[0x70]	18773	1			T2	33		T13	19		T15	6
valid_sources[0x71]	21098	1			T1	7		T2	35		T13	17
valid_sources[0x72]	21289	1			T1	3		T2	37		T13	35
valid_sources[0x73]	11198	1			T1	30		T2	21		T13	52
valid_sources[0x74]	11097	1			T1	22		T2	44		T13	7
valid_sources[0x75]	12137	1			T2	43		T13	30		T15	7
valid_sources[0x76]	11751	1			T2	44		T13	52		T15	4
valid_sources[0x77]	11115	1			T2	43		T13	22		T15	8
valid_sources[0x78]	10824	1			T1	24		T2	45		T13	32
valid_sources[0x79]	11544	1			T1	21		T2	33		T13	49
valid_sources[0x7a]	14163	1			T1	19		T2	36		T13	32
valid_sources[0x7b]	14617	1			T1	11		T2	33		T13	5
valid_sources[0x7c]	24677	1			T1	32		T2	34		T13	20
valid_sources[0x7d]	18940	1			T1	28		T2	45		T13	51
valid_sources[0x7e]	10960	1			T1	10		T2	28		T13	76
valid_sources[0x7f]	11365	1			T2	33		T13	53		T15	5
valid_sources[0x80]	12013	1			T2	40		T13	73		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

315807

1

T1

681

T2

2641

T3

130

values[0x0]

all_enables

biggest_size

141842

1

T1

311

T2

1197

T3

13

values[0x1]

all_enables

biggest_size

128098

1

T1

277

T2

1129

T3

6