Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4132709	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

630655

1

T1

209

T2

149

T3

2604

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4347239	1			T1	428		T2	474		T3	8532
values[0x0]	206263	1			T1	67		T2	41		T3	663
values[0x1]	209862	1			T1	70		T2	42		T3	715

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2816133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1947231

1

T1

270

T2

251

T3

4721

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17083	1			T1	1		T2	5		T3	43
valid_sources[0x01]	17066	1			T1	2		T2	1		T3	38
valid_sources[0x02]	16302	1			T1	1		T2	1		T3	34
valid_sources[0x03]	17466	1			T1	3		T2	2		T3	39
valid_sources[0x04]	17315	1			T1	2		T2	4		T3	48
valid_sources[0x05]	21723	1			T1	1		T2	3		T3	37
valid_sources[0x06]	15798	1			T1	3		T2	5		T3	45
valid_sources[0x07]	18309	1			T3	20		T4	2150		T16	3
valid_sources[0x08]	21395	1			T1	1		T2	4		T3	57
valid_sources[0x09]	15826	1			T1	3		T2	2		T3	41
valid_sources[0x0a]	52715	1			T1	3		T3	48		T15	5
valid_sources[0x0b]	20563	1			T1	2		T2	3		T3	40
valid_sources[0x0c]	15484	1			T1	2		T3	45		T16	5
valid_sources[0x0d]	17794	1			T1	1		T2	2		T3	40
valid_sources[0x0e]	20812	1			T1	1		T2	5		T3	36
valid_sources[0x0f]	18211	1			T1	2		T2	5		T3	49
valid_sources[0x10]	16601	1			T1	5		T2	3		T3	51
valid_sources[0x11]	16774	1			T1	4		T2	5		T3	37
valid_sources[0x12]	16810	1			T1	2		T2	4		T3	46
valid_sources[0x13]	16128	1			T1	2		T2	2		T3	37
valid_sources[0x14]	18168	1			T1	5		T2	3		T3	31
valid_sources[0x15]	15771	1			T3	37		T16	4		T18	3
valid_sources[0x16]	16347	1			T1	2		T2	1		T3	41
valid_sources[0x17]	16470	1			T1	2		T2	3		T3	37
valid_sources[0x18]	16832	1			T1	4		T2	2		T3	39
valid_sources[0x19]	20100	1			T1	2		T2	4		T3	37
valid_sources[0x1a]	15448	1			T1	3		T2	4		T3	40
valid_sources[0x1b]	18154	1			T1	2		T2	5		T3	50
valid_sources[0x1c]	15826	1			T2	3		T3	34		T15	1
valid_sources[0x1d]	15507	1			T1	3		T2	1		T3	23
valid_sources[0x1e]	15654	1			T1	1		T2	2		T3	42
valid_sources[0x1f]	20853	1			T1	2		T2	1		T3	30
valid_sources[0x20]	15625	1			T1	1		T2	2		T3	34
valid_sources[0x21]	15442	1			T1	3		T2	2		T3	31
valid_sources[0x22]	16911	1			T1	2		T2	4		T3	41
valid_sources[0x23]	16436	1			T1	1		T2	3		T3	43
valid_sources[0x24]	15826	1			T1	2		T2	3		T3	38
valid_sources[0x25]	15221	1			T1	2		T2	2		T3	55
valid_sources[0x26]	18066	1			T1	2		T2	3		T3	32
valid_sources[0x27]	15995	1			T1	3		T2	1		T3	28
valid_sources[0x28]	15725	1			T2	2		T3	21		T15	3
valid_sources[0x29]	30118	1			T1	2		T3	43		T15	1
valid_sources[0x2a]	16098	1			T2	2		T3	37		T15	1
valid_sources[0x2b]	18156	1			T1	3		T2	1		T3	33
valid_sources[0x2c]	18144	1			T1	3		T2	3		T3	55
valid_sources[0x2d]	17048	1			T1	1		T2	2		T3	32
valid_sources[0x2e]	16731	1			T1	2		T2	4		T3	34
valid_sources[0x2f]	22830	1			T1	2		T3	44		T15	3
valid_sources[0x30]	15880	1			T1	2		T2	2		T3	29
valid_sources[0x31]	16564	1			T1	4		T2	5		T3	24
valid_sources[0x32]	19849	1			T1	3		T2	6		T3	40
valid_sources[0x33]	15133	1			T1	4		T2	3		T3	31
valid_sources[0x34]	16931	1			T1	2		T2	3		T3	24
valid_sources[0x35]	16057	1			T1	4		T2	4		T3	46
valid_sources[0x36]	17602	1			T2	2		T3	22		T15	5
valid_sources[0x37]	16574	1			T1	1		T2	1		T3	32
valid_sources[0x38]	16638	1			T1	3		T2	2		T3	41
valid_sources[0x39]	17478	1			T1	2		T3	50		T16	2
valid_sources[0x3a]	24145	1			T1	2		T2	1		T3	41
valid_sources[0x3b]	21879	1			T1	1		T2	2		T3	51
valid_sources[0x3c]	17759	1			T1	3		T2	3		T3	48
valid_sources[0x3d]	15213	1			T1	1		T3	35		T15	1
valid_sources[0x3e]	16939	1			T1	1		T3	38		T15	1
valid_sources[0x3f]	16726	1			T1	1		T2	1		T3	25
valid_sources[0x40]	21004	1			T1	2		T2	3		T3	31
valid_sources[0x41]	18032	1			T2	5		T3	37		T15	1
valid_sources[0x42]	15346	1			T1	2		T2	1		T3	38
valid_sources[0x43]	19904	1			T1	3		T2	1		T3	44
valid_sources[0x44]	16437	1			T1	2		T2	1		T3	39
valid_sources[0x45]	19519	1			T1	2		T2	2		T3	37
valid_sources[0x46]	16205	1			T1	4		T2	4		T3	33
valid_sources[0x47]	15754	1			T1	6		T2	1		T3	36
valid_sources[0x48]	20804	1			T1	3		T2	3		T3	39
valid_sources[0x49]	16672	1			T1	3		T2	3		T3	36
valid_sources[0x4a]	17371	1			T2	2		T3	47		T15	1
valid_sources[0x4b]	15942	1			T1	2		T2	3		T3	57
valid_sources[0x4c]	18609	1			T1	3		T2	1		T3	27
valid_sources[0x4d]	18612	1			T1	3		T2	2		T3	43
valid_sources[0x4e]	17755	1			T1	1		T2	1		T3	41
valid_sources[0x4f]	16069	1			T2	2		T3	24		T16	3
valid_sources[0x50]	17027	1			T1	2		T2	4		T3	24
valid_sources[0x51]	15613	1			T2	1		T3	44		T16	5
valid_sources[0x52]	16319	1			T1	3		T2	5		T3	38
valid_sources[0x53]	15905	1			T1	3		T2	2		T3	29
valid_sources[0x54]	16647	1			T1	1		T2	1		T3	21
valid_sources[0x55]	43759	1			T1	2		T2	5		T3	37
valid_sources[0x56]	32020	1			T1	5		T2	3		T3	28
valid_sources[0x57]	16741	1			T1	4		T2	3		T3	45
valid_sources[0x58]	24450	1			T2	1		T3	38		T15	2
valid_sources[0x59]	16514	1			T1	1		T2	3		T3	44
valid_sources[0x5a]	16671	1			T1	3		T3	34		T15	2
valid_sources[0x5b]	17930	1			T1	1		T2	2		T3	31
valid_sources[0x5c]	23820	1			T1	3		T2	2		T3	49
valid_sources[0x5d]	16625	1			T2	2		T3	40		T15	1
valid_sources[0x5e]	15886	1			T1	6		T3	34		T16	13
valid_sources[0x5f]	17520	1			T1	2		T2	3		T3	46
valid_sources[0x60]	15411	1			T1	5		T2	1		T3	37
valid_sources[0x61]	16079	1			T2	2		T3	43		T15	2
valid_sources[0x62]	15740	1			T1	2		T2	5		T3	40
valid_sources[0x63]	18043	1			T2	1		T3	49		T16	4
valid_sources[0x64]	17064	1			T1	4		T2	4		T3	42
valid_sources[0x65]	44690	1			T1	3		T2	3		T3	27
valid_sources[0x66]	15383	1			T1	5		T2	2		T3	35
valid_sources[0x67]	20656	1			T1	4		T2	1		T3	31
valid_sources[0x68]	17670	1			T1	1		T2	1		T3	47
valid_sources[0x69]	15587	1			T1	1		T3	30		T15	1
valid_sources[0x6a]	17181	1			T1	1		T2	2		T3	37
valid_sources[0x6b]	18537	1			T1	1		T2	3		T3	45
valid_sources[0x6c]	44325	1			T1	1		T2	3		T3	43
valid_sources[0x6d]	15373	1			T1	4		T2	1		T3	55
valid_sources[0x6e]	16289	1			T1	3		T2	3		T3	45
valid_sources[0x6f]	17693	1			T1	4		T2	1		T3	46
valid_sources[0x70]	16220	1			T1	2		T3	41		T15	1
valid_sources[0x71]	15511	1			T1	3		T2	1		T3	37
valid_sources[0x72]	22080	1			T2	1		T3	18		T15	1
valid_sources[0x73]	15906	1			T1	2		T2	3		T3	51
valid_sources[0x74]	16351	1			T1	3		T3	38		T14	639
valid_sources[0x75]	18541	1			T1	4		T2	2		T3	49
valid_sources[0x76]	20413	1			T1	2		T2	2		T3	25
valid_sources[0x77]	16249	1			T1	1		T3	27		T15	1
valid_sources[0x78]	16149	1			T1	1		T2	1		T3	31
valid_sources[0x79]	17364	1			T1	2		T2	2		T3	35
valid_sources[0x7a]	15609	1			T1	1		T2	3		T3	49
valid_sources[0x7b]	16493	1			T1	3		T2	1		T3	34
valid_sources[0x7c]	30506	1			T1	2		T2	1		T3	61
valid_sources[0x7d]	26532	1			T1	5		T3	33		T15	3
valid_sources[0x7e]	16503	1			T1	2		T2	2		T3	37
valid_sources[0x7f]	15190	1			T1	3		T2	2		T3	39
valid_sources[0x80]	16472	1			T1	6		T2	2		T3	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

348410

1

T1

163

T2

125

T3

1630

values[0x0]

all_enables

biggest_size

148467

1

T1

31

T2

16

T3

479

values[0x1]

all_enables

biggest_size

133778

1

T1

15

T2

8

T3

495