Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30083257	16872	0	0
attest_sw_binding_0_rd_A	30083257	3018	0	0
attest_sw_binding_1_rd_A	30083257	2893	0	0
attest_sw_binding_2_rd_A	30083257	2871	0	0
attest_sw_binding_3_rd_A	30083257	2999	0	0
attest_sw_binding_4_rd_A	30083257	2972	0	0
attest_sw_binding_5_rd_A	30083257	2924	0	0
attest_sw_binding_6_rd_A	30083257	3073	0	0
attest_sw_binding_7_rd_A	30083257	2963	0	0
intr_enable_rd_A	30083257	3606	0	0
key_version_rd_A	30083257	2976	0	0
max_creator_key_ver_regwen_rd_A	30083257	2758	0	0
max_owner_int_key_ver_regwen_rd_A	30083257	2884	0	0
max_owner_key_ver_regwen_rd_A	30083257	2865	0	0
reseed_interval_regwen_rd_A	30083257	2892	0	0
salt_0_rd_A	30083257	2865	0	0
salt_1_rd_A	30083257	3015	0	0
salt_2_rd_A	30083257	2942	0	0
salt_3_rd_A	30083257	2979	0	0
salt_4_rd_A	30083257	2920	0	0
salt_5_rd_A	30083257	2993	0	0
salt_6_rd_A	30083257	2998	0	0
salt_7_rd_A	30083257	3063	0	0
sealing_sw_binding_0_rd_A	30083257	2949	0	0
sealing_sw_binding_1_rd_A	30083257	3093	0	0
sealing_sw_binding_2_rd_A	30083257	3148	0	0
sealing_sw_binding_3_rd_A	30083257	2994	0	0
sealing_sw_binding_4_rd_A	30083257	2787	0	0
sealing_sw_binding_5_rd_A	30083257	2860	0	0
sealing_sw_binding_6_rd_A	30083257	2766	0	0
sealing_sw_binding_7_rd_A	30083257	3014	0	0
sideload_clear_rd_A	30083257	2907	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	16872	0	0
T7	37937	1131	0	0
T37	15601	0	0	0
T52	0	261	0	0
T82	14299	0	0	0
T101	0	739	0	0
T102	0	1	0	0
T111	0	268	0	0
T112	0	251	0	0
T114	0	50	0	0
T115	0	57	0	0
T116	0	598	0	0
T117	0	22	0	0
T118	4736	0	0	0
T119	5993	0	0	0
T120	7195	0	0	0
T121	965	0	0	0
T122	9289	0	0	0
T123	854	0	0	0
T124	5355	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3018	0	0
T45	0	14	0	0
T67	0	23	0	0
T117	16090	13	0	0
T141	0	16	0	0
T152	0	87	0	0
T153	0	87	0	0
T173	0	19	0	0
T174	0	19	0	0
T175	0	20	0	0
T176	0	19	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2893	0	0
T45	0	21	0	0
T67	0	9	0	0
T117	16090	15	0	0
T141	0	35	0	0
T152	0	88	0	0
T160	0	7	0	0
T173	0	13	0	0
T174	0	21	0	0
T175	0	23	0	0
T176	0	23	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2871	0	0
T45	0	56	0	0
T67	0	38	0	0
T117	16090	27	0	0
T141	0	11	0	0
T152	0	67	0	0
T173	0	27	0	0
T174	0	22	0	0
T175	0	22	0	0
T176	0	21	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0
T186	0	4	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2999	0	0
T45	0	22	0	0
T67	0	27	0	0
T117	16090	12	0	0
T141	0	1	0	0
T152	0	78	0	0
T153	0	94	0	0
T173	0	17	0	0
T174	0	39	0	0
T175	0	22	0	0
T176	0	40	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2972	0	0
T45	0	45	0	0
T67	0	15	0	0
T117	16090	14	0	0
T141	0	18	0	0
T152	0	90	0	0
T160	0	3	0	0
T173	0	28	0	0
T174	0	37	0	0
T175	0	32	0	0
T176	0	28	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2924	0	0
T45	0	9	0	0
T67	0	34	0	0
T117	16090	12	0	0
T141	0	36	0	0
T152	0	80	0	0
T153	0	69	0	0
T173	0	20	0	0
T174	0	17	0	0
T175	0	46	0	0
T176	0	47	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3073	0	0
T45	0	35	0	0
T67	0	7	0	0
T117	16090	15	0	0
T141	0	32	0	0
T152	0	77	0	0
T153	0	67	0	0
T173	0	3	0	0
T174	0	24	0	0
T175	0	35	0	0
T176	0	45	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2963	0	0
T45	0	31	0	0
T67	0	10	0	0
T117	16090	20	0	0
T141	0	33	0	0
T152	0	94	0	0
T153	0	86	0	0
T173	0	27	0	0
T174	0	15	0	0
T175	0	33	0	0
T176	0	26	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3606	0	0
T25	5968	0	0	0
T34	41085	0	0	0
T42	0	61	0	0
T48	159753	21	0	0
T53	49260	0	0	0
T59	0	27	0	0
T128	4821	0	0	0
T129	132064	0	0	0
T130	11755	0	0	0
T131	95262	0	0	0
T132	30854	0	0	0
T133	3537	0	0	0
T187	0	17	0	0
T188	0	41	0	0
T189	0	22	0	0
T190	0	23	0	0
T191	0	7	0	0
T192	0	37	0	0
T193	0	12	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2976	0	0
T45	0	37	0	0
T67	0	20	0	0
T117	16090	12	0	0
T152	0	100	0	0
T153	0	69	0	0
T173	0	7	0	0
T174	0	17	0	0
T175	0	35	0	0
T176	0	28	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0
T194	0	17	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2758	0	0
T45	0	42	0	0
T67	0	8	0	0
T117	16090	24	0	0
T141	0	47	0	0
T152	0	80	0	0
T160	0	1	0	0
T173	0	13	0	0
T174	0	23	0	0
T175	0	22	0	0
T176	0	33	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2884	0	0
T45	0	30	0	0
T67	0	24	0	0
T117	16090	26	0	0
T141	0	11	0	0
T152	0	61	0	0
T160	0	2	0	0
T173	0	11	0	0
T174	0	17	0	0
T175	0	33	0	0
T176	0	18	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2865	0	0
T45	0	25	0	0
T67	0	25	0	0
T117	16090	21	0	0
T141	0	35	0	0
T152	0	64	0	0
T153	0	64	0	0
T173	0	21	0	0
T174	0	17	0	0
T175	0	29	0	0
T176	0	38	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2892	0	0
T45	0	32	0	0
T67	0	24	0	0
T117	16090	19	0	0
T141	0	14	0	0
T152	0	94	0	0
T153	0	71	0	0
T173	0	26	0	0
T174	0	36	0	0
T175	0	30	0	0
T176	0	28	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2865	0	0
T45	0	37	0	0
T67	0	17	0	0
T117	16090	20	0	0
T141	0	25	0	0
T152	0	86	0	0
T160	0	2	0	0
T173	0	10	0	0
T174	0	44	0	0
T175	0	27	0	0
T176	0	30	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3015	0	0
T45	0	43	0	0
T67	0	17	0	0
T117	16090	14	0	0
T141	0	18	0	0
T152	0	67	0	0
T153	0	67	0	0
T173	0	16	0	0
T174	0	16	0	0
T175	0	39	0	0
T176	0	14	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2942	0	0
T45	0	34	0	0
T67	0	9	0	0
T117	16090	12	0	0
T141	0	25	0	0
T152	0	89	0	0
T160	0	2	0	0
T173	0	25	0	0
T174	0	32	0	0
T175	0	44	0	0
T176	0	36	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2979	0	0
T45	0	24	0	0
T67	0	21	0	0
T117	16090	21	0	0
T141	0	23	0	0
T152	0	80	0	0
T160	0	6	0	0
T173	0	2	0	0
T174	0	20	0	0
T175	0	36	0	0
T176	0	41	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2920	0	0
T45	0	30	0	0
T67	0	31	0	0
T117	16090	15	0	0
T141	0	11	0	0
T152	0	97	0	0
T160	0	8	0	0
T173	0	14	0	0
T174	0	15	0	0
T175	0	47	0	0
T176	0	30	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2993	0	0
T45	0	24	0	0
T67	0	34	0	0
T117	16090	12	0	0
T141	0	9	0	0
T152	0	82	0	0
T160	0	3	0	0
T173	0	47	0	0
T174	0	22	0	0
T175	0	42	0	0
T176	0	31	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2998	0	0
T45	0	28	0	0
T67	0	32	0	0
T117	16090	24	0	0
T141	0	30	0	0
T152	0	60	0	0
T160	0	6	0	0
T173	0	16	0	0
T174	0	15	0	0
T175	0	36	0	0
T176	0	36	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3063	0	0
T45	0	33	0	0
T67	0	50	0	0
T117	16090	7	0	0
T141	0	30	0	0
T152	0	95	0	0
T153	0	105	0	0
T173	0	17	0	0
T174	0	24	0	0
T175	0	20	0	0
T176	0	26	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2949	0	0
T45	0	25	0	0
T67	0	29	0	0
T117	16090	33	0	0
T141	0	13	0	0
T152	0	76	0	0
T160	0	6	0	0
T173	0	25	0	0
T174	0	14	0	0
T175	0	21	0	0
T176	0	27	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3093	0	0
T45	0	57	0	0
T67	0	19	0	0
T117	16090	28	0	0
T141	0	27	0	0
T152	0	72	0	0
T153	0	85	0	0
T173	0	23	0	0
T174	0	29	0	0
T175	0	9	0	0
T176	0	30	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3148	0	0
T45	0	29	0	0
T67	0	28	0	0
T117	16090	22	0	0
T141	0	10	0	0
T152	0	101	0	0
T153	0	96	0	0
T173	0	33	0	0
T174	0	17	0	0
T175	0	33	0	0
T176	0	38	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2994	0	0
T45	0	52	0	0
T67	0	32	0	0
T117	16090	13	0	0
T141	0	23	0	0
T152	0	88	0	0
T153	0	63	0	0
T173	0	20	0	0
T174	0	28	0	0
T175	0	19	0	0
T176	0	42	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2787	0	0
T45	0	34	0	0
T67	0	36	0	0
T117	16090	18	0	0
T141	0	23	0	0
T152	0	64	0	0
T153	0	61	0	0
T173	0	23	0	0
T174	0	10	0	0
T175	0	22	0	0
T176	0	21	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2860	0	0
T45	0	43	0	0
T67	0	9	0	0
T117	16090	16	0	0
T141	0	20	0	0
T152	0	88	0	0
T153	0	90	0	0
T173	0	21	0	0
T174	0	11	0	0
T175	0	29	0	0
T176	0	27	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2766	0	0
T45	0	29	0	0
T67	0	15	0	0
T117	16090	5	0	0
T141	0	25	0	0
T152	0	98	0	0
T153	0	80	0	0
T173	0	28	0	0
T174	0	49	0	0
T175	0	29	0	0
T176	0	22	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	3014	0	0
T45	0	22	0	0
T67	0	22	0	0
T117	16090	13	0	0
T141	0	16	0	0
T160	0	3	0	0
T173	0	4	0	0
T174	0	25	0	0
T175	0	54	0	0
T176	0	16	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0
T195	0	9	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30083257	2907	0	0
T45	0	43	0	0
T67	0	11	0	0
T117	16090	21	0	0
T141	0	19	0	0
T152	0	65	0	0
T160	0	1	0	0
T173	0	5	0	0
T174	0	46	0	0
T175	0	29	0	0
T176	0	33	0	0
T177	19029	0	0	0
T178	11123	0	0	0
T179	14076	0	0	0
T180	5353	0	0	0
T181	1422	0	0	0
T182	7124	0	0	0
T183	60038	0	0	0
T184	197587	0	0	0
T185	6842	0	0	0