Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4015661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

616411

1

T1

433

T2

170

T3

519

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4227664	1			T1	1265		T2	1861		T3	1020
values[0x0]	200748	1			T1	186		T2	43		T3	190
values[0x1]	203660	1			T1	174		T2	44		T3	185

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2737130	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1894942

1

T1

760

T2

749

T3

750

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13138	1			T1	5		T2	15		T13	5
valid_sources[0x01]	14280	1			T1	17		T2	21		T13	8
valid_sources[0x02]	13389	1			T1	6		T2	11		T4	6
valid_sources[0x03]	16705	1			T1	1		T2	25		T13	6
valid_sources[0x04]	14029	1			T1	2		T2	9		T4	1
valid_sources[0x05]	13012	1			T1	6		T4	1		T13	9
valid_sources[0x06]	13959	1			T1	8		T2	12		T4	15
valid_sources[0x07]	14689	1			T1	5		T2	14		T4	6
valid_sources[0x08]	15095	1			T1	9		T2	7		T13	8
valid_sources[0x09]	48400	1			T1	14		T2	8		T4	2
valid_sources[0x0a]	15279	1			T1	3		T2	10		T4	2
valid_sources[0x0b]	51997	1			T1	3		T2	4		T13	4
valid_sources[0x0c]	13322	1			T1	10		T2	3		T13	1
valid_sources[0x0d]	15143	1			T1	7		T2	8		T13	3
valid_sources[0x0e]	17559	1			T1	5		T2	19		T13	8
valid_sources[0x0f]	12110	1			T1	9		T2	1		T15	2
valid_sources[0x10]	13975	1			T1	3		T2	3		T13	8
valid_sources[0x11]	13653	1			T1	4		T2	1		T4	2
valid_sources[0x12]	14358	1			T1	5		T2	26		T13	6
valid_sources[0x13]	13832	1			T1	7		T2	14		T4	1
valid_sources[0x14]	13678	1			T1	2		T13	11		T15	5
valid_sources[0x15]	12339	1			T1	7		T2	3		T4	7
valid_sources[0x16]	33916	1			T1	5		T2	6		T4	4
valid_sources[0x17]	13251	1			T1	7		T2	23		T13	7
valid_sources[0x18]	16416	1			T1	4		T2	16		T4	2
valid_sources[0x19]	13085	1			T1	11		T4	7		T13	9
valid_sources[0x1a]	17751	1			T1	12		T2	5		T13	3
valid_sources[0x1b]	17387	1			T1	4		T2	33		T13	4
valid_sources[0x1c]	12741	1			T1	2		T2	26		T4	2
valid_sources[0x1d]	20584	1			T1	6		T2	5		T13	1
valid_sources[0x1e]	17715	1			T1	3		T2	3		T13	1
valid_sources[0x1f]	16471	1			T1	4		T2	4		T4	1
valid_sources[0x20]	14204	1			T1	7		T2	3		T13	5
valid_sources[0x21]	222196	1			T1	5		T2	18		T13	4
valid_sources[0x22]	14270	1			T1	6		T2	5		T4	2
valid_sources[0x23]	25442	1			T1	6		T2	3		T13	5
valid_sources[0x24]	48201	1			T1	4		T2	12		T13	11
valid_sources[0x25]	12941	1			T1	9		T2	4		T13	3
valid_sources[0x26]	21988	1			T1	9		T2	10		T13	4
valid_sources[0x27]	14845	1			T1	6		T2	19		T13	2
valid_sources[0x28]	15128	1			T1	15		T2	9		T13	4
valid_sources[0x29]	12700	1			T1	4		T2	5		T13	5
valid_sources[0x2a]	12552	1			T1	9		T2	9		T13	6
valid_sources[0x2b]	14548	1			T1	5		T2	2		T17	32
valid_sources[0x2c]	14794	1			T1	7		T13	5		T17	45
valid_sources[0x2d]	12831	1			T1	4		T2	3		T13	6
valid_sources[0x2e]	18026	1			T1	7		T2	1		T13	14
valid_sources[0x2f]	14190	1			T1	6		T2	6		T13	9
valid_sources[0x30]	13438	1			T1	3		T2	19		T4	1
valid_sources[0x31]	16166	1			T1	4		T2	2		T4	3
valid_sources[0x32]	14722	1			T1	4		T2	25		T13	18
valid_sources[0x33]	14223	1			T1	11		T2	13		T13	16
valid_sources[0x34]	12814	1			T1	8		T2	10		T13	3
valid_sources[0x35]	78435	1			T1	5		T2	5		T13	2
valid_sources[0x36]	17943	1			T1	11		T13	16		T15	2
valid_sources[0x37]	15525	1			T1	1		T2	2		T4	2
valid_sources[0x38]	12968	1			T1	9		T2	3		T13	12
valid_sources[0x39]	18368	1			T1	8		T13	10		T15	1
valid_sources[0x3a]	12589	1			T1	6		T2	1		T4	2
valid_sources[0x3b]	17226	1			T1	3		T2	10		T13	10
valid_sources[0x3c]	13325	1			T1	2		T2	1		T4	5
valid_sources[0x3d]	23238	1			T1	5		T2	9		T13	4
valid_sources[0x3e]	14461	1			T1	7		T2	12		T13	2
valid_sources[0x3f]	13269	1			T1	7		T2	8		T4	3
valid_sources[0x40]	23698	1			T1	5		T2	7		T13	4
valid_sources[0x41]	12549	1			T1	12		T2	10		T13	11
valid_sources[0x42]	13915	1			T1	9		T2	16		T4	13
valid_sources[0x43]	12475	1			T1	7		T13	2		T15	1
valid_sources[0x44]	15825	1			T1	8		T2	8		T4	1
valid_sources[0x45]	16253	1			T1	2		T2	11		T4	5
valid_sources[0x46]	14974	1			T1	7		T13	9		T15	3
valid_sources[0x47]	12599	1			T1	9		T2	13		T13	4
valid_sources[0x48]	18757	1			T1	1		T2	12		T4	14
valid_sources[0x49]	15406	1			T1	6		T2	19		T13	3
valid_sources[0x4a]	12582	1			T1	2		T2	6		T13	11
valid_sources[0x4b]	21244	1			T1	3		T2	23		T4	5
valid_sources[0x4c]	14456	1			T1	10		T15	1		T17	25
valid_sources[0x4d]	14732	1			T1	4		T2	1		T4	3
valid_sources[0x4e]	13649	1			T1	6		T2	4		T4	2
valid_sources[0x4f]	16566	1			T1	9		T2	8		T13	3
valid_sources[0x50]	20470	1			T1	8		T2	3		T17	50
valid_sources[0x51]	17927	1			T1	9		T2	1		T13	1
valid_sources[0x52]	17429	1			T1	8		T2	5		T17	53
valid_sources[0x53]	13401	1			T1	7		T2	12		T4	3
valid_sources[0x54]	14180	1			T1	11		T2	1		T13	3
valid_sources[0x55]	14707	1			T1	9		T2	2		T13	17
valid_sources[0x56]	16392	1			T1	3		T4	17		T13	2
valid_sources[0x57]	26000	1			T2	9		T13	3		T15	2
valid_sources[0x58]	16813	1			T1	4		T2	1		T13	7
valid_sources[0x59]	16624	1			T1	6		T2	27		T4	3
valid_sources[0x5a]	12908	1			T1	11		T2	9		T13	6
valid_sources[0x5b]	14787	1			T2	3		T4	3		T13	1
valid_sources[0x5c]	13862	1			T1	12		T2	3		T13	11
valid_sources[0x5d]	12961	1			T1	3		T2	1		T4	3
valid_sources[0x5e]	52824	1			T1	11		T2	6		T13	9
valid_sources[0x5f]	12934	1			T1	4		T13	1		T15	1
valid_sources[0x60]	14421	1			T1	3		T2	7		T13	8
valid_sources[0x61]	19587	1			T1	2		T2	8		T13	16
valid_sources[0x62]	12883	1			T1	6		T13	4		T15	7
valid_sources[0x63]	14198	1			T1	6		T2	6		T13	7
valid_sources[0x64]	14871	1			T1	4		T2	6		T13	12
valid_sources[0x65]	12998	1			T1	10		T2	8		T13	11
valid_sources[0x66]	13079	1			T1	3		T2	1		T13	3
valid_sources[0x67]	12587	1			T2	11		T13	16		T15	2
valid_sources[0x68]	16988	1			T1	8		T2	11		T13	6
valid_sources[0x69]	12506	1			T1	9		T2	5		T4	2
valid_sources[0x6a]	12797	1			T1	7		T2	6		T4	1
valid_sources[0x6b]	15812	1			T1	5		T2	7		T13	1
valid_sources[0x6c]	25513	1			T1	8		T2	9		T13	4
valid_sources[0x6d]	16677	1			T1	6		T2	6		T4	6
valid_sources[0x6e]	15473	1			T1	15		T2	7		T13	11
valid_sources[0x6f]	24785	1			T1	6		T2	8		T4	11
valid_sources[0x70]	13120	1			T1	11		T2	3		T13	6
valid_sources[0x71]	14103	1			T1	4		T2	7		T13	4
valid_sources[0x72]	13783	1			T1	9		T2	10		T13	12
valid_sources[0x73]	14064	1			T1	8		T2	14		T13	3
valid_sources[0x74]	14659	1			T1	3		T2	6		T13	4
valid_sources[0x75]	13777	1			T1	5		T4	4		T13	2
valid_sources[0x76]	16475	1			T1	4		T2	8		T13	3
valid_sources[0x77]	16258	1			T1	8		T2	3		T4	3
valid_sources[0x78]	15438	1			T1	5		T2	5		T4	1
valid_sources[0x79]	13594	1			T1	6		T2	7		T13	15
valid_sources[0x7a]	14364	1			T1	5		T2	16		T13	2
valid_sources[0x7b]	14822	1			T1	16		T2	1		T15	4
valid_sources[0x7c]	13914	1			T1	12		T2	4		T4	16
valid_sources[0x7d]	14857	1			T1	3		T2	12		T4	15
valid_sources[0x7e]	12492	1			T1	2		T2	10		T4	4
valid_sources[0x7f]	13133	1			T1	5		T2	2		T13	17
valid_sources[0x80]	13727	1			T1	5		T2	3		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

340504

1

T1

202

T2

136

T3

283

values[0x0]

all_enables

biggest_size

144854

1

T1

127

T2

24

T3

127

values[0x1]

all_enables

biggest_size

131053

1

T1

104

T2

10

T3

109