Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5518278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

625524

1

T1

157

T2

243

T3

232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5734149	1			T1	624		T2	577		T3	782
values[0x0]	203976	1			T1	42		T2	65		T3	100
values[0x1]	205677	1			T1	38		T2	81		T3	80

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3739783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2404019

1

T1

320

T2

367

T3

440

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19528	1			T1	3		T4	8		T5	1
valid_sources[0x01]	20374	1			T1	1		T3	3		T15	20
valid_sources[0x02]	21165	1			T3	1		T4	15		T15	23
valid_sources[0x03]	21929	1			T1	3		T3	8		T4	9
valid_sources[0x04]	20309	1			T1	3		T3	3		T4	57
valid_sources[0x05]	52728	1			T1	4		T3	5		T15	17
valid_sources[0x06]	19549	1			T3	7		T5	7		T15	26
valid_sources[0x07]	49998	1			T1	1		T3	6		T14	1
valid_sources[0x08]	20483	1			T1	3		T3	2		T14	1
valid_sources[0x09]	18614	1			T1	11		T3	13		T15	28
valid_sources[0x0a]	19237	1			T3	7		T15	19		T16	1
valid_sources[0x0b]	20725	1			T15	19		T18	2		T26	11
valid_sources[0x0c]	19801	1			T3	5		T5	2		T15	23
valid_sources[0x0d]	23058	1			T1	3		T3	2		T4	16
valid_sources[0x0e]	18785	1			T1	1		T3	2		T15	21
valid_sources[0x0f]	21632	1			T1	1		T3	5		T5	7
valid_sources[0x10]	18929	1			T1	5		T3	4		T4	9
valid_sources[0x11]	18742	1			T1	2		T3	5		T5	2
valid_sources[0x12]	35719	1			T3	4		T4	1		T15	29
valid_sources[0x13]	21317	1			T1	1		T3	4		T15	23
valid_sources[0x14]	27640	1			T1	6		T3	3		T15	19
valid_sources[0x15]	53820	1			T3	4		T5	12		T15	23
valid_sources[0x16]	18641	1			T1	3		T3	3		T5	3
valid_sources[0x17]	18442	1			T1	2		T3	5		T15	23
valid_sources[0x18]	22517	1			T1	1		T3	3		T4	3
valid_sources[0x19]	19306	1			T1	3		T3	5		T15	22
valid_sources[0x1a]	18359	1			T3	5		T4	1		T15	18
valid_sources[0x1b]	20308	1			T1	2		T3	3		T14	2
valid_sources[0x1c]	18820	1			T3	9		T4	77		T5	2
valid_sources[0x1d]	21929	1			T1	5		T3	5		T15	37
valid_sources[0x1e]	19580	1			T1	13		T3	3		T5	1
valid_sources[0x1f]	18917	1			T3	2		T4	22		T15	24
valid_sources[0x20]	24448	1			T1	5		T3	8		T4	10
valid_sources[0x21]	20872	1			T1	3		T3	2		T5	1
valid_sources[0x22]	19946	1			T1	1		T3	4		T5	1
valid_sources[0x23]	20250	1			T3	5		T5	1		T15	26
valid_sources[0x24]	22437	1			T1	2		T5	4		T15	30
valid_sources[0x25]	18819	1			T1	5		T3	5		T15	32
valid_sources[0x26]	19507	1			T1	1		T3	3		T5	5
valid_sources[0x27]	18438	1			T1	1		T3	3		T4	1
valid_sources[0x28]	33010	1			T3	2		T4	9		T5	17
valid_sources[0x29]	19883	1			T3	3		T4	17		T5	1
valid_sources[0x2a]	24230	1			T1	2		T3	3		T4	5
valid_sources[0x2b]	57391	1			T1	7		T3	4		T4	18
valid_sources[0x2c]	20302	1			T1	1		T5	1		T15	21
valid_sources[0x2d]	22069	1			T1	1		T3	2		T5	3
valid_sources[0x2e]	21530	1			T3	4		T15	27		T16	1
valid_sources[0x2f]	19093	1			T1	1		T3	2		T5	8
valid_sources[0x30]	18568	1			T1	3		T3	4		T4	19
valid_sources[0x31]	19061	1			T3	2		T14	2		T15	23
valid_sources[0x32]	28719	1			T1	4		T3	5		T5	5
valid_sources[0x33]	18760	1			T1	7		T3	4		T15	22
valid_sources[0x34]	19504	1			T1	16		T3	3		T4	17
valid_sources[0x35]	25103	1			T3	3		T5	1		T15	26
valid_sources[0x36]	27103	1			T1	10		T5	2		T15	22
valid_sources[0x37]	23343	1			T1	3		T3	5		T4	81
valid_sources[0x38]	21189	1			T3	7		T4	12		T5	7
valid_sources[0x39]	40083	1			T1	6		T3	6		T5	4
valid_sources[0x3a]	35755	1			T3	7		T4	6		T5	2
valid_sources[0x3b]	23504	1			T1	1		T3	2		T4	16
valid_sources[0x3c]	19184	1			T1	1		T3	5		T5	3
valid_sources[0x3d]	21275	1			T3	1		T5	1		T15	34
valid_sources[0x3e]	18786	1			T1	1		T3	6		T4	62
valid_sources[0x3f]	38710	1			T3	6		T4	3		T5	8
valid_sources[0x40]	19714	1			T1	3		T3	4		T5	2
valid_sources[0x41]	19461	1			T3	2		T5	1		T15	13
valid_sources[0x42]	19204	1			T1	2		T3	2		T4	20
valid_sources[0x43]	19046	1			T3	4		T4	2		T15	18
valid_sources[0x44]	19905	1			T1	8		T5	1		T14	1
valid_sources[0x45]	21189	1			T1	1		T3	4		T15	21
valid_sources[0x46]	68722	1			T3	6		T5	2		T15	27
valid_sources[0x47]	18437	1			T1	5		T3	1		T4	6
valid_sources[0x48]	19847	1			T1	2		T3	5		T15	26
valid_sources[0x49]	20519	1			T1	3		T3	5		T15	27
valid_sources[0x4a]	19672	1			T1	8		T3	3		T5	1
valid_sources[0x4b]	20164	1			T1	1		T3	3		T5	1
valid_sources[0x4c]	24530	1			T1	2		T3	3		T14	1
valid_sources[0x4d]	24829	1			T5	7		T14	1		T15	21
valid_sources[0x4e]	20313	1			T1	4		T3	1		T15	24
valid_sources[0x4f]	20773	1			T1	2		T3	4		T4	15
valid_sources[0x50]	22688	1			T1	5		T3	6		T15	21
valid_sources[0x51]	24268	1			T1	4		T3	5		T4	17
valid_sources[0x52]	18370	1			T1	2		T4	29		T15	20
valid_sources[0x53]	19557	1			T1	1		T3	3		T14	2
valid_sources[0x54]	19683	1			T3	3		T5	1		T15	22
valid_sources[0x55]	19274	1			T1	2		T3	3		T15	19
valid_sources[0x56]	22435	1			T1	4		T3	1		T14	1
valid_sources[0x57]	19339	1			T1	2		T3	7		T5	1
valid_sources[0x58]	20790	1			T1	5		T3	2		T5	2
valid_sources[0x59]	19506	1			T3	1		T4	14		T5	7
valid_sources[0x5a]	21609	1			T3	3		T15	26		T16	2
valid_sources[0x5b]	19324	1			T3	5		T5	5		T15	20
valid_sources[0x5c]	23202	1			T3	2		T4	21		T15	25
valid_sources[0x5d]	21009	1			T1	2		T3	2		T4	12
valid_sources[0x5e]	20014	1			T5	1		T15	24		T18	5
valid_sources[0x5f]	21579	1			T1	2		T3	3		T4	16
valid_sources[0x60]	23230	1			T1	7		T2	723		T3	3
valid_sources[0x61]	92249	1			T3	5		T5	2		T15	26
valid_sources[0x62]	24523	1			T1	4		T3	1		T5	1
valid_sources[0x63]	18895	1			T1	1		T3	2		T5	1
valid_sources[0x64]	20974	1			T1	5		T3	5		T5	5
valid_sources[0x65]	24306	1			T1	5		T3	7		T15	35
valid_sources[0x66]	19849	1			T3	5		T15	14		T18	1
valid_sources[0x67]	29835	1			T1	3		T3	4		T5	2
valid_sources[0x68]	19252	1			T3	3		T4	5		T5	3
valid_sources[0x69]	18542	1			T3	4		T15	24		T16	5
valid_sources[0x6a]	21065	1			T1	5		T3	5		T5	7
valid_sources[0x6b]	25462	1			T1	1		T3	7		T5	3
valid_sources[0x6c]	19383	1			T1	7		T3	1		T4	24
valid_sources[0x6d]	46210	1			T1	1		T3	7		T4	9
valid_sources[0x6e]	19425	1			T1	4		T3	2		T5	4
valid_sources[0x6f]	18737	1			T1	2		T3	3		T15	17
valid_sources[0x70]	19763	1			T3	6		T5	3		T15	33
valid_sources[0x71]	19389	1			T1	3		T3	2		T15	21
valid_sources[0x72]	23057	1			T1	1		T3	9		T15	21
valid_sources[0x73]	32490	1			T3	6		T5	1		T15	25
valid_sources[0x74]	18320	1			T3	7		T15	20		T18	3
valid_sources[0x75]	19032	1			T1	5		T3	6		T5	4
valid_sources[0x76]	20105	1			T1	2		T3	2		T5	4
valid_sources[0x77]	20599	1			T1	2		T3	3		T4	15
valid_sources[0x78]	21707	1			T1	1		T3	2		T15	25
valid_sources[0x79]	20956	1			T1	3		T3	3		T5	2
valid_sources[0x7a]	22206	1			T1	9		T3	3		T4	8
valid_sources[0x7b]	21853	1			T1	5		T3	2		T15	15
valid_sources[0x7c]	19758	1			T1	2		T3	6		T5	1
valid_sources[0x7d]	21429	1			T1	8		T3	4		T15	16
valid_sources[0x7e]	24031	1			T1	7		T3	6		T5	2
valid_sources[0x7f]	28584	1			T1	2		T3	2		T5	1
valid_sources[0x80]	50957	1			T1	6		T3	6		T4	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

350813

1

T1

129

T2

197

T3

106

values[0x0]

all_enables

biggest_size

145078

1

T1

18

T2

29

T3

78

values[0x1]

all_enables

biggest_size

129633

1

T1

10

T2

17

T3

48