Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.04 95.95 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 37210377 14465 0 0
attest_sw_binding_0_rd_A 37210377 2659 0 0
attest_sw_binding_1_rd_A 37210377 2634 0 0
attest_sw_binding_2_rd_A 37210377 2598 0 0
attest_sw_binding_3_rd_A 37210377 2528 0 0
attest_sw_binding_4_rd_A 37210377 2424 0 0
attest_sw_binding_5_rd_A 37210377 2498 0 0
attest_sw_binding_6_rd_A 37210377 2588 0 0
attest_sw_binding_7_rd_A 37210377 2671 0 0
intr_enable_rd_A 37210377 2978 0 0
key_version_rd_A 37210377 2555 0 0
max_creator_key_ver_regwen_rd_A 37210377 2697 0 0
max_owner_int_key_ver_regwen_rd_A 37210377 2493 0 0
max_owner_key_ver_regwen_rd_A 37210377 2556 0 0
reseed_interval_regwen_rd_A 37210377 2528 0 0
salt_0_rd_A 37210377 2539 0 0
salt_1_rd_A 37210377 2584 0 0
salt_2_rd_A 37210377 2618 0 0
salt_3_rd_A 37210377 2641 0 0
salt_4_rd_A 37210377 2610 0 0
salt_5_rd_A 37210377 2557 0 0
salt_6_rd_A 37210377 2662 0 0
salt_7_rd_A 37210377 2627 0 0
sealing_sw_binding_0_rd_A 37210377 2482 0 0
sealing_sw_binding_1_rd_A 37210377 2597 0 0
sealing_sw_binding_2_rd_A 37210377 2514 0 0
sealing_sw_binding_3_rd_A 37210377 2566 0 0
sealing_sw_binding_4_rd_A 37210377 2520 0 0
sealing_sw_binding_5_rd_A 37210377 2547 0 0
sealing_sw_binding_6_rd_A 37210377 2503 0 0
sealing_sw_binding_7_rd_A 37210377 2674 0 0
sideload_clear_rd_A 37210377 2458 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 14465 0 0
T25 148895 0 0 0
T28 8886 0 0 0
T65 10763 0 0 0
T66 0 174 0 0
T67 6234 0 0 0
T101 22572 28 0 0
T102 819 0 0 0
T103 4032 0 0 0
T104 5391 0 0 0
T105 4244 0 0 0
T107 0 442 0 0
T108 0 979 0 0
T124 0 420 0 0
T125 0 621 0 0
T126 0 694 0 0
T127 0 338 0 0
T128 0 326 0 0
T138 0 441 0 0
T139 20486 0 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2659 0 0
T66 30265 23 0 0
T110 0 211 0 0
T127 0 29 0 0
T138 0 33 0 0
T187 0 25 0 0
T188 0 23 0 0
T189 0 6 0 0
T190 0 4 0 0
T191 0 58 0 0
T192 0 15 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2634 0 0
T66 30265 11 0 0
T110 0 227 0 0
T127 0 36 0 0
T138 0 41 0 0
T187 0 14 0 0
T188 0 41 0 0
T190 0 23 0 0
T191 0 28 0 0
T192 0 24 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 22 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2598 0 0
T66 30265 29 0 0
T110 0 225 0 0
T127 0 65 0 0
T138 0 34 0 0
T187 0 16 0 0
T188 0 15 0 0
T190 0 7 0 0
T191 0 30 0 0
T192 0 7 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 6 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2528 0 0
T66 0 37 0 0
T110 0 205 0 0
T127 0 22 0 0
T138 0 17 0 0
T158 3393 0 0 0
T187 0 12 0 0
T188 0 17 0 0
T190 0 15 0 0
T191 0 31 0 0
T192 0 5 0 0
T203 6818 4 0 0
T204 3086 0 0 0
T205 31490 0 0 0
T206 222100 0 0 0
T207 29513 0 0 0
T208 255969 0 0 0
T209 6202 0 0 0
T210 4509 0 0 0
T211 22488 0 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2424 0 0
T66 30265 8 0 0
T127 0 49 0 0
T138 0 11 0 0
T187 0 19 0 0
T188 0 29 0 0
T190 0 2 0 0
T191 0 4 0 0
T192 0 42 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T212 0 3 0 0
T213 0 1 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2498 0 0
T66 30265 17 0 0
T110 0 225 0 0
T127 0 28 0 0
T138 0 46 0 0
T187 0 11 0 0
T188 0 31 0 0
T190 0 9 0 0
T191 0 29 0 0
T192 0 6 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 22 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2588 0 0
T66 30265 37 0 0
T110 0 197 0 0
T127 0 32 0 0
T138 0 22 0 0
T187 0 10 0 0
T188 0 17 0 0
T190 0 3 0 0
T191 0 49 0 0
T192 0 18 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 20 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2671 0 0
T66 30265 4 0 0
T110 0 218 0 0
T127 0 31 0 0
T138 0 32 0 0
T187 0 1 0 0
T188 0 30 0 0
T190 0 14 0 0
T191 0 30 0 0
T192 0 14 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 18 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2978 0 0
T7 0 23 0 0
T8 0 70 0 0
T48 178320 15 0 0
T55 1898 0 0 0
T60 0 8 0 0
T66 0 21 0 0
T127 0 37 0 0
T129 8403 0 0 0
T130 23528 0 0 0
T131 1752 0 0 0
T132 23834 0 0 0
T133 106837 0 0 0
T134 7130 0 0 0
T135 1336 0 0 0
T136 4903 0 0 0
T138 0 23 0 0
T187 0 12 0 0
T188 0 41 0 0
T214 0 25 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2555 0 0
T66 30265 5 0 0
T110 0 212 0 0
T127 0 20 0 0
T138 0 28 0 0
T187 0 16 0 0
T188 0 28 0 0
T190 0 15 0 0
T191 0 23 0 0
T192 0 11 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 27 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2697 0 0
T66 30265 14 0 0
T110 0 186 0 0
T127 0 51 0 0
T138 0 20 0 0
T187 0 16 0 0
T188 0 18 0 0
T190 0 10 0 0
T191 0 50 0 0
T192 0 9 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 22 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2493 0 0
T66 30265 6 0 0
T110 0 230 0 0
T127 0 45 0 0
T138 0 36 0 0
T187 0 19 0 0
T188 0 27 0 0
T190 0 22 0 0
T191 0 27 0 0
T192 0 22 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 20 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2556 0 0
T66 30265 12 0 0
T110 0 211 0 0
T127 0 30 0 0
T138 0 42 0 0
T187 0 10 0 0
T188 0 24 0 0
T190 0 12 0 0
T191 0 14 0 0
T192 0 25 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 22 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2528 0 0
T66 30265 16 0 0
T110 0 231 0 0
T127 0 40 0 0
T138 0 9 0 0
T187 0 20 0 0
T188 0 36 0 0
T190 0 9 0 0
T191 0 28 0 0
T192 0 21 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 16 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2539 0 0
T66 30265 25 0 0
T110 0 206 0 0
T127 0 26 0 0
T138 0 21 0 0
T187 0 9 0 0
T188 0 33 0 0
T190 0 20 0 0
T191 0 35 0 0
T192 0 20 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 11 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2584 0 0
T66 30265 14 0 0
T110 0 233 0 0
T127 0 41 0 0
T138 0 33 0 0
T187 0 7 0 0
T188 0 35 0 0
T190 0 16 0 0
T191 0 41 0 0
T192 0 3 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 22 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2618 0 0
T66 30265 31 0 0
T110 0 238 0 0
T127 0 18 0 0
T138 0 20 0 0
T187 0 17 0 0
T188 0 27 0 0
T190 0 16 0 0
T191 0 33 0 0
T192 0 11 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 11 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2641 0 0
T66 30265 20 0 0
T110 0 228 0 0
T127 0 19 0 0
T138 0 34 0 0
T187 0 4 0 0
T188 0 27 0 0
T190 0 10 0 0
T191 0 31 0 0
T192 0 32 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T215 0 5 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2610 0 0
T66 30265 10 0 0
T110 0 225 0 0
T127 0 32 0 0
T138 0 33 0 0
T187 0 22 0 0
T188 0 44 0 0
T190 0 11 0 0
T191 0 23 0 0
T192 0 25 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 28 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2557 0 0
T66 30265 17 0 0
T110 0 225 0 0
T127 0 20 0 0
T138 0 23 0 0
T187 0 6 0 0
T188 0 23 0 0
T190 0 14 0 0
T191 0 33 0 0
T192 0 17 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 25 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2662 0 0
T66 30265 34 0 0
T110 0 224 0 0
T127 0 40 0 0
T138 0 31 0 0
T187 0 13 0 0
T188 0 23 0 0
T190 0 8 0 0
T191 0 18 0 0
T192 0 27 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 17 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2627 0 0
T66 30265 6 0 0
T110 0 230 0 0
T127 0 12 0 0
T138 0 36 0 0
T187 0 1 0 0
T188 0 24 0 0
T190 0 21 0 0
T191 0 31 0 0
T192 0 12 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 30 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2482 0 0
T66 30265 10 0 0
T110 0 238 0 0
T127 0 22 0 0
T138 0 38 0 0
T187 0 21 0 0
T188 0 28 0 0
T190 0 17 0 0
T191 0 22 0 0
T192 0 19 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 14 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2597 0 0
T66 30265 15 0 0
T110 0 210 0 0
T127 0 28 0 0
T138 0 8 0 0
T187 0 22 0 0
T188 0 17 0 0
T190 0 10 0 0
T191 0 26 0 0
T192 0 23 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T216 0 1 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2514 0 0
T66 30265 8 0 0
T110 0 239 0 0
T127 0 43 0 0
T138 0 26 0 0
T187 0 7 0 0
T188 0 27 0 0
T190 0 7 0 0
T191 0 9 0 0
T192 0 16 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 10 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2566 0 0
T66 30265 33 0 0
T110 0 220 0 0
T127 0 37 0 0
T138 0 51 0 0
T187 0 20 0 0
T188 0 19 0 0
T190 0 7 0 0
T191 0 14 0 0
T192 0 11 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 10 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2520 0 0
T66 30265 33 0 0
T110 0 233 0 0
T127 0 36 0 0
T138 0 11 0 0
T187 0 16 0 0
T188 0 21 0 0
T190 0 14 0 0
T191 0 28 0 0
T192 0 26 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 20 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2547 0 0
T66 30265 17 0 0
T110 0 191 0 0
T127 0 24 0 0
T138 0 44 0 0
T187 0 14 0 0
T188 0 19 0 0
T191 0 21 0 0
T192 0 15 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 17 0 0
T217 0 7 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2503 0 0
T66 30265 24 0 0
T110 0 233 0 0
T127 0 24 0 0
T138 0 47 0 0
T187 0 1 0 0
T188 0 24 0 0
T190 0 8 0 0
T191 0 24 0 0
T192 0 14 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 13 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2674 0 0
T66 30265 12 0 0
T110 0 231 0 0
T127 0 41 0 0
T138 0 31 0 0
T187 0 19 0 0
T188 0 26 0 0
T190 0 9 0 0
T191 0 32 0 0
T192 0 18 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 15 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 37210377 2458 0 0
T66 30265 11 0 0
T110 0 224 0 0
T127 0 34 0 0
T138 0 14 0 0
T187 0 17 0 0
T188 0 16 0 0
T190 0 6 0 0
T191 0 35 0 0
T192 0 9 0 0
T193 17824 0 0 0
T194 4807 0 0 0
T195 19350 0 0 0
T196 5146 0 0 0
T197 74346 0 0 0
T198 101064 0 0 0
T199 24565 0 0 0
T200 89419 0 0 0
T201 27454 0 0 0
T202 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%