Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4125587	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

589366

1

T1

491

T2

640

T3

259

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4310786	1			T1	13491		T2	7026		T3	4102
values[0x0]	200617	1			T1	170		T2	216		T3	70
values[0x1]	203550	1			T1	173		T2	194		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2807689	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1907264

1

T1

4847

T2

2856

T3

1544

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15172	1			T1	54		T2	29		T12	1
valid_sources[0x01]	15666	1			T1	39		T2	16		T12	4
valid_sources[0x02]	14784	1			T1	84		T2	22		T12	1
valid_sources[0x03]	16727	1			T1	56		T2	28		T12	3
valid_sources[0x04]	15053	1			T1	33		T2	33		T12	1
valid_sources[0x05]	15616	1			T1	49		T2	31		T12	4
valid_sources[0x06]	15330	1			T1	71		T2	27		T12	2
valid_sources[0x07]	15170	1			T1	51		T2	23		T12	1
valid_sources[0x08]	15712	1			T1	42		T2	26		T12	1
valid_sources[0x09]	15762	1			T1	37		T2	30		T12	3
valid_sources[0x0a]	17381	1			T1	56		T2	17		T12	1
valid_sources[0x0b]	15494	1			T1	69		T2	18		T12	2
valid_sources[0x0c]	29607	1			T1	54		T2	17		T12	2
valid_sources[0x0d]	15098	1			T1	70		T2	27		T12	1
valid_sources[0x0e]	17400	1			T1	36		T2	31		T13	1
valid_sources[0x0f]	18722	1			T1	53		T2	27		T12	1
valid_sources[0x10]	14942	1			T1	65		T2	29		T12	1
valid_sources[0x11]	16106	1			T1	51		T2	31		T12	1
valid_sources[0x12]	17057	1			T1	48		T2	25		T13	4
valid_sources[0x13]	14935	1			T1	51		T2	35		T12	1
valid_sources[0x14]	29286	1			T1	70		T2	25		T12	3
valid_sources[0x15]	15619	1			T1	78		T2	38		T12	2
valid_sources[0x16]	32510	1			T1	34		T2	40		T14	7
valid_sources[0x17]	15236	1			T1	81		T2	45		T12	6
valid_sources[0x18]	16763	1			T1	41		T2	21		T12	4
valid_sources[0x19]	17173	1			T1	18		T2	33		T12	1
valid_sources[0x1a]	15127	1			T1	57		T2	26		T12	1
valid_sources[0x1b]	17082	1			T1	44		T2	27		T12	1
valid_sources[0x1c]	15608	1			T1	39		T2	27		T13	2
valid_sources[0x1d]	16284	1			T1	61		T2	28		T12	2
valid_sources[0x1e]	15618	1			T1	49		T2	29		T12	4
valid_sources[0x1f]	15306	1			T1	57		T2	24		T12	2
valid_sources[0x20]	17437	1			T1	45		T2	34		T12	4
valid_sources[0x21]	18725	1			T1	61		T2	42		T12	2
valid_sources[0x22]	16877	1			T1	83		T2	17		T12	2
valid_sources[0x23]	16412	1			T1	42		T2	44		T12	2
valid_sources[0x24]	15657	1			T1	45		T2	52		T12	5
valid_sources[0x25]	15938	1			T1	48		T2	23		T12	2
valid_sources[0x26]	15226	1			T1	84		T2	26		T12	3
valid_sources[0x27]	15359	1			T1	68		T2	28		T12	5
valid_sources[0x28]	15869	1			T1	29		T2	32		T14	2
valid_sources[0x29]	17138	1			T1	87		T2	26		T12	3
valid_sources[0x2a]	15311	1			T1	80		T2	31		T12	4
valid_sources[0x2b]	16303	1			T1	41		T2	31		T12	6
valid_sources[0x2c]	17841	1			T1	53		T2	28		T12	2
valid_sources[0x2d]	16044	1			T1	91		T2	30		T12	7
valid_sources[0x2e]	103944	1			T1	65		T2	29		T13	9
valid_sources[0x2f]	15496	1			T1	42		T2	29		T12	1
valid_sources[0x30]	15966	1			T1	86		T2	20		T12	1
valid_sources[0x31]	15872	1			T1	62		T2	27		T12	5
valid_sources[0x32]	15532	1			T1	46		T2	26		T12	8
valid_sources[0x33]	17351	1			T1	15		T2	34		T12	6
valid_sources[0x34]	16161	1			T1	39		T2	25		T12	3
valid_sources[0x35]	20292	1			T1	52		T2	31		T12	3
valid_sources[0x36]	14850	1			T1	64		T2	32		T12	1
valid_sources[0x37]	48210	1			T1	85		T2	14		T12	3
valid_sources[0x38]	15453	1			T1	65		T2	21		T12	8
valid_sources[0x39]	20059	1			T1	62		T2	29		T12	2
valid_sources[0x3a]	16052	1			T1	58		T2	47		T12	4
valid_sources[0x3b]	16762	1			T1	21		T2	30		T12	2
valid_sources[0x3c]	30610	1			T1	55		T2	41		T12	2
valid_sources[0x3d]	15216	1			T1	53		T2	38		T12	4
valid_sources[0x3e]	14999	1			T1	46		T2	22		T12	2
valid_sources[0x3f]	15382	1			T1	55		T2	18		T12	3
valid_sources[0x40]	15729	1			T1	57		T2	27		T12	2
valid_sources[0x41]	17707	1			T1	39		T2	26		T12	2
valid_sources[0x42]	16394	1			T1	32		T2	52		T12	3
valid_sources[0x43]	15291	1			T1	60		T2	29		T12	4
valid_sources[0x44]	15283	1			T1	83		T2	33		T12	2
valid_sources[0x45]	16250	1			T1	65		T2	28		T12	3
valid_sources[0x46]	15096	1			T1	43		T2	19		T12	2
valid_sources[0x47]	15387	1			T1	53		T2	27		T12	4
valid_sources[0x48]	15039	1			T1	45		T2	31		T12	7
valid_sources[0x49]	17245	1			T1	41		T2	26		T12	4
valid_sources[0x4a]	14960	1			T1	42		T2	27		T12	1
valid_sources[0x4b]	15906	1			T1	82		T2	23		T14	2
valid_sources[0x4c]	19443	1			T1	55		T2	26		T12	6
valid_sources[0x4d]	43919	1			T1	56		T2	34		T12	1
valid_sources[0x4e]	16044	1			T1	55		T2	21		T12	3
valid_sources[0x4f]	15575	1			T1	87		T2	13		T12	1
valid_sources[0x50]	15140	1			T1	73		T2	36		T12	6
valid_sources[0x51]	16932	1			T1	111		T2	41		T12	2
valid_sources[0x52]	14960	1			T1	56		T2	26		T13	3
valid_sources[0x53]	30462	1			T1	75		T2	43		T12	2
valid_sources[0x54]	15424	1			T1	79		T2	26		T12	3
valid_sources[0x55]	15881	1			T1	44		T2	27		T12	1
valid_sources[0x56]	20238	1			T1	53		T2	32		T12	7
valid_sources[0x57]	16261	1			T1	43		T2	21		T13	1
valid_sources[0x58]	17678	1			T1	66		T2	18		T12	3
valid_sources[0x59]	18121	1			T1	40		T2	19		T12	3
valid_sources[0x5a]	16454	1			T1	64		T2	16		T12	2
valid_sources[0x5b]	19548	1			T1	75		T2	34		T12	4
valid_sources[0x5c]	17174	1			T1	37		T2	26		T14	4
valid_sources[0x5d]	16445	1			T1	71		T2	40		T13	5
valid_sources[0x5e]	15083	1			T1	77		T2	33		T12	4
valid_sources[0x5f]	14869	1			T1	61		T2	23		T12	1
valid_sources[0x60]	18569	1			T1	38		T2	28		T14	8
valid_sources[0x61]	14890	1			T1	48		T2	38		T12	5
valid_sources[0x62]	15465	1			T1	54		T2	23		T12	1
valid_sources[0x63]	16336	1			T1	63		T2	29		T12	6
valid_sources[0x64]	15254	1			T1	56		T2	18		T12	2
valid_sources[0x65]	15251	1			T1	51		T2	16		T12	1
valid_sources[0x66]	16174	1			T1	34		T2	32		T13	2
valid_sources[0x67]	15240	1			T1	72		T2	14		T12	1
valid_sources[0x68]	16386	1			T1	83		T2	21		T13	4
valid_sources[0x69]	15289	1			T1	70		T2	32		T12	5
valid_sources[0x6a]	15309	1			T1	52		T2	27		T12	2
valid_sources[0x6b]	15044	1			T1	51		T2	32		T12	4
valid_sources[0x6c]	16106	1			T1	47		T2	31		T12	2
valid_sources[0x6d]	16859	1			T1	50		T2	46		T12	1
valid_sources[0x6e]	15175	1			T1	64		T2	32		T12	5
valid_sources[0x6f]	15510	1			T1	29		T2	34		T12	1
valid_sources[0x70]	22156	1			T1	44		T2	22		T12	4
valid_sources[0x71]	36872	1			T1	56		T2	21		T12	1
valid_sources[0x72]	20366	1			T1	66		T2	28		T3	4225
valid_sources[0x73]	15391	1			T1	61		T2	27		T12	1
valid_sources[0x74]	15654	1			T1	42		T2	27		T12	1
valid_sources[0x75]	19518	1			T1	50		T2	27		T12	3
valid_sources[0x76]	17713	1			T1	43		T2	28		T12	1
valid_sources[0x77]	15824	1			T1	66		T2	28		T12	2
valid_sources[0x78]	19712	1			T1	43		T2	14		T12	3
valid_sources[0x79]	15322	1			T1	78		T2	23		T12	3
valid_sources[0x7a]	20980	1			T1	66		T2	50		T12	1
valid_sources[0x7b]	17150	1			T1	60		T2	24		T12	5
valid_sources[0x7c]	29706	1			T1	47		T2	25		T12	4
valid_sources[0x7d]	18964	1			T1	27		T2	20		T12	5
valid_sources[0x7e]	15681	1			T1	67		T2	30		T12	1
valid_sources[0x7f]	15687	1			T1	61		T2	20		T13	4
valid_sources[0x80]	15121	1			T1	89		T2	32		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

315578

1

T1

284

T2

359

T3

223

values[0x0]

all_enables

biggest_size

144028

1

T1

112

T2

152

T3

27

values[0x1]

all_enables

biggest_size

129760

1

T1

95

T2

129

T3

9