Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28870181	16729	0	0
attest_sw_binding_0_rd_A	28870181	2808	0	0
attest_sw_binding_1_rd_A	28870181	2605	0	0
attest_sw_binding_2_rd_A	28870181	2757	0	0
attest_sw_binding_3_rd_A	28870181	2844	0	0
attest_sw_binding_4_rd_A	28870181	2631	0	0
attest_sw_binding_5_rd_A	28870181	2719	0	0
attest_sw_binding_6_rd_A	28870181	2748	0	0
attest_sw_binding_7_rd_A	28870181	2790	0	0
intr_enable_rd_A	28870181	3547	0	0
key_version_rd_A	28870181	2608	0	0
max_creator_key_ver_regwen_rd_A	28870181	2632	0	0
max_owner_int_key_ver_regwen_rd_A	28870181	2789	0	0
max_owner_key_ver_regwen_rd_A	28870181	2782	0	0
reseed_interval_regwen_rd_A	28870181	2787	0	0
salt_0_rd_A	28870181	2665	0	0
salt_1_rd_A	28870181	2623	0	0
salt_2_rd_A	28870181	2790	0	0
salt_3_rd_A	28870181	2605	0	0
salt_4_rd_A	28870181	2743	0	0
salt_5_rd_A	28870181	2792	0	0
salt_6_rd_A	28870181	2747	0	0
salt_7_rd_A	28870181	2608	0	0
sealing_sw_binding_0_rd_A	28870181	2630	0	0
sealing_sw_binding_1_rd_A	28870181	2789	0	0
sealing_sw_binding_2_rd_A	28870181	2747	0	0
sealing_sw_binding_3_rd_A	28870181	2547	0	0
sealing_sw_binding_4_rd_A	28870181	2749	0	0
sealing_sw_binding_5_rd_A	28870181	2589	0	0
sealing_sw_binding_6_rd_A	28870181	2505	0	0
sealing_sw_binding_7_rd_A	28870181	2767	0	0
sideload_clear_rd_A	28870181	2620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	16729	0	0
T4	10862	0	0	0
T7	10708	0	0	0
T49	11554	156	0	0
T50	61125	0	0	0
T51	11243	0	0	0
T58	0	302	0	0
T63	0	146	0	0
T66	0	48	0	0
T68	0	99	0	0
T70	9196	0	0	0
T77	0	814	0	0
T97	18172	0	0	0
T116	0	434	0	0
T127	0	588	0	0
T128	0	142	0	0
T129	28842	0	0	0
T130	34700	0	0	0
T131	24747	0	0	0
T132	0	397	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2808	0	0
T58	57025	67	0	0
T68	0	22	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	13	0	0
T148	0	5	0	0
T179	0	51	0	0
T180	0	15	0	0
T181	0	11	0	0
T182	0	68	0	0
T183	0	24	0	0
T184	0	5	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2605	0	0
T58	57025	37	0	0
T68	0	57	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	4	0	0
T148	0	9	0	0
T179	0	35	0	0
T180	0	14	0	0
T181	0	22	0	0
T182	0	45	0	0
T183	0	23	0	0
T184	0	10	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2757	0	0
T58	57025	47	0	0
T68	0	22	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	2	0	0
T148	0	9	0	0
T179	0	52	0	0
T180	0	9	0	0
T181	0	4	0	0
T182	0	47	0	0
T183	0	42	0	0
T184	0	6	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2844	0	0
T58	57025	62	0	0
T68	0	33	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	49	0	0
T148	0	10	0	0
T179	0	81	0	0
T180	0	16	0	0
T181	0	6	0	0
T182	0	66	0	0
T183	0	32	0	0
T184	0	18	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2631	0	0
T58	57025	45	0	0
T68	0	38	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	12	0	0
T148	0	12	0	0
T179	0	47	0	0
T180	0	6	0	0
T181	0	27	0	0
T182	0	51	0	0
T183	0	22	0	0
T184	0	5	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2719	0	0
T58	57025	56	0	0
T68	0	20	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	12	0	0
T148	0	1	0	0
T179	0	76	0	0
T180	0	3	0	0
T181	0	4	0	0
T182	0	35	0	0
T183	0	42	0	0
T184	0	30	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2748	0	0
T58	57025	51	0	0
T68	0	26	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T117	0	103	0	0
T128	0	15	0	0
T148	0	5	0	0
T179	0	66	0	0
T180	0	13	0	0
T181	0	6	0	0
T182	0	34	0	0
T183	0	28	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2790	0	0
T58	57025	52	0	0
T68	0	35	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	8	0	0
T148	0	10	0	0
T179	0	54	0	0
T180	0	11	0	0
T181	0	35	0	0
T182	0	54	0	0
T183	0	26	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0
T191	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	3547	0	0
T8	5953	0	0	0
T44	369462	70	0	0
T54	13295	0	0	0
T58	0	73	0	0
T64	10079	0	0	0
T65	3885	0	0	0
T68	0	54	0	0
T87	1029	0	0	0
T121	5144	0	0	0
T128	0	25	0	0
T139	0	27	0	0
T179	0	56	0	0
T192	0	50	0	0
T193	0	43	0	0
T194	0	24	0	0
T195	0	8	0	0
T196	15423	0	0	0
T197	3007	0	0	0
T198	29853	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2608	0	0
T58	57025	51	0	0
T68	0	25	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	10	0	0
T148	0	4	0	0
T179	0	57	0	0
T180	0	22	0	0
T181	0	22	0	0
T182	0	34	0	0
T183	0	18	0	0
T184	0	7	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2632	0	0
T58	57025	62	0	0
T68	0	36	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	45	0	0
T179	0	54	0	0
T180	0	15	0	0
T181	0	13	0	0
T182	0	22	0	0
T183	0	26	0	0
T184	0	10	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0
T199	0	7	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2789	0	0
T58	57025	44	0	0
T68	0	58	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	29	0	0
T148	0	7	0	0
T179	0	76	0	0
T180	0	10	0	0
T181	0	28	0	0
T182	0	55	0	0
T183	0	38	0	0
T184	0	1	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2782	0	0
T58	57025	36	0	0
T68	0	32	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	4	0	0
T148	0	3	0	0
T179	0	59	0	0
T180	0	16	0	0
T181	0	15	0	0
T182	0	40	0	0
T183	0	35	0	0
T184	0	6	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2787	0	0
T58	57025	67	0	0
T68	0	27	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	12	0	0
T148	0	15	0	0
T179	0	64	0	0
T180	0	8	0	0
T181	0	19	0	0
T182	0	73	0	0
T183	0	45	0	0
T184	0	4	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2665	0	0
T58	57025	53	0	0
T68	0	41	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	17	0	0
T148	0	3	0	0
T179	0	73	0	0
T180	0	9	0	0
T181	0	10	0	0
T182	0	44	0	0
T183	0	39	0	0
T184	0	1	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2623	0	0
T58	57025	31	0	0
T68	0	22	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	13	0	0
T148	0	7	0	0
T179	0	42	0	0
T180	0	18	0	0
T181	0	20	0	0
T182	0	49	0	0
T183	0	24	0	0
T184	0	14	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2790	0	0
T58	57025	59	0	0
T68	0	33	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	20	0	0
T148	0	5	0	0
T179	0	37	0	0
T180	0	20	0	0
T181	0	29	0	0
T182	0	27	0	0
T183	0	26	0	0
T184	0	11	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2605	0	0
T58	57025	52	0	0
T68	0	11	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	18	0	0
T179	0	56	0	0
T180	0	21	0	0
T181	0	11	0	0
T182	0	57	0	0
T183	0	17	0	0
T184	0	28	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0
T200	0	5	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2743	0	0
T58	57025	46	0	0
T68	0	31	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	14	0	0
T148	0	16	0	0
T179	0	66	0	0
T180	0	14	0	0
T181	0	7	0	0
T182	0	49	0	0
T183	0	39	0	0
T184	0	1	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2792	0	0
T58	57025	36	0	0
T68	0	32	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	12	0	0
T148	0	10	0	0
T179	0	61	0	0
T180	0	17	0	0
T181	0	17	0	0
T182	0	47	0	0
T183	0	18	0	0
T184	0	14	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2747	0	0
T58	57025	90	0	0
T68	0	27	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	13	0	0
T148	0	3	0	0
T179	0	29	0	0
T180	0	12	0	0
T181	0	11	0	0
T182	0	48	0	0
T183	0	35	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0
T201	0	4	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2608	0	0
T58	57025	59	0	0
T68	0	35	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	14	0	0
T148	0	12	0	0
T179	0	71	0	0
T180	0	18	0	0
T181	0	16	0	0
T182	0	51	0	0
T183	0	35	0	0
T184	0	12	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2630	0	0
T58	57025	51	0	0
T68	0	28	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	36	0	0
T148	0	1	0	0
T179	0	57	0	0
T180	0	11	0	0
T181	0	6	0	0
T182	0	52	0	0
T183	0	14	0	0
T184	0	4	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2789	0	0
T58	57025	40	0	0
T68	0	39	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	24	0	0
T148	0	12	0	0
T179	0	65	0	0
T180	0	3	0	0
T181	0	14	0	0
T182	0	65	0	0
T183	0	37	0	0
T184	0	12	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2747	0	0
T58	57025	71	0	0
T68	0	33	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	7	0	0
T148	0	27	0	0
T179	0	58	0	0
T180	0	20	0	0
T181	0	5	0	0
T182	0	28	0	0
T183	0	31	0	0
T184	0	4	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2547	0	0
T58	57025	41	0	0
T68	0	26	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T117	0	111	0	0
T128	0	9	0	0
T179	0	54	0	0
T180	0	10	0	0
T181	0	17	0	0
T182	0	42	0	0
T183	0	36	0	0
T184	0	3	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2749	0	0
T58	57025	54	0	0
T68	0	29	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	10	0	0
T148	0	10	0	0
T179	0	60	0	0
T180	0	17	0	0
T181	0	23	0	0
T182	0	58	0	0
T183	0	28	0	0
T184	0	14	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2589	0	0
T58	57025	69	0	0
T68	0	33	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	5	0	0
T148	0	5	0	0
T179	0	57	0	0
T180	0	24	0	0
T181	0	14	0	0
T182	0	32	0	0
T183	0	30	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0
T201	0	6	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2505	0	0
T58	57025	46	0	0
T68	0	26	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	10	0	0
T148	0	11	0	0
T179	0	42	0	0
T180	0	13	0	0
T181	0	26	0	0
T182	0	72	0	0
T183	0	19	0	0
T184	0	4	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2767	0	0
T58	57025	47	0	0
T68	0	41	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	23	0	0
T148	0	8	0	0
T179	0	67	0	0
T180	0	12	0	0
T181	0	22	0	0
T182	0	58	0	0
T183	0	16	0	0
T184	0	8	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28870181	2620	0	0
T58	57025	54	0	0
T68	0	18	0	0
T90	11057	0	0	0
T92	67798	0	0	0
T94	10706	0	0	0
T128	0	6	0	0
T148	0	14	0	0
T179	0	24	0	0
T180	0	13	0	0
T181	0	9	0	0
T182	0	62	0	0
T183	0	21	0	0
T184	0	7	0	0
T185	1912	0	0	0
T186	3077	0	0	0
T187	11398	0	0	0
T188	106795	0	0	0
T189	12207	0	0	0
T190	5067	0	0	0