Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3208419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

591919

1

T1

240

T2

4

T3

592

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3410016	1			T1	239		T2	1		T3	851
values[0x0]	194148	1			T1	138		T2	8		T3	214
values[0x1]	196174	1			T1	118		T2	11		T3	213

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1602507

1

T1

310

T2

7

T3

772

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11490	1			T4	6		T13	5		T16	6
valid_sources[0x01]	11694	1			T4	3		T16	5		T18	13
valid_sources[0x02]	13905	1			T4	5		T13	2		T14	3
valid_sources[0x03]	11272	1			T4	6		T13	1		T14	14
valid_sources[0x04]	11522	1			T4	5		T14	151		T16	8
valid_sources[0x05]	13390	1			T4	5		T14	190		T16	2
valid_sources[0x06]	12411	1			T4	10		T16	5		T18	19
valid_sources[0x07]	12157	1			T4	2		T14	201		T16	2
valid_sources[0x08]	20908	1			T4	5		T16	4		T18	6
valid_sources[0x09]	11098	1			T4	4		T14	24		T16	2
valid_sources[0x0a]	10645	1			T4	5		T13	5		T16	1
valid_sources[0x0b]	12840	1			T4	5		T13	1		T14	4
valid_sources[0x0c]	15866	1			T4	1		T13	4		T16	4
valid_sources[0x0d]	15815	1			T4	4		T13	1		T14	314
valid_sources[0x0e]	13848	1			T4	3		T14	5		T16	3
valid_sources[0x0f]	13497	1			T4	5		T14	62		T15	904
valid_sources[0x10]	13938	1			T4	3		T13	7		T14	39
valid_sources[0x11]	13200	1			T4	6		T14	1		T16	1
valid_sources[0x12]	12049	1			T4	5		T13	2		T14	28
valid_sources[0x13]	11614	1			T4	12		T13	7		T16	2
valid_sources[0x14]	11792	1			T4	7		T14	63		T16	4
valid_sources[0x15]	18496	1			T4	4		T14	23		T16	5
valid_sources[0x16]	12011	1			T4	3		T14	22		T16	2
valid_sources[0x17]	11189	1			T4	4		T14	90		T16	2
valid_sources[0x18]	25703	1			T4	4		T16	1		T18	8
valid_sources[0x19]	13204	1			T4	2		T14	56		T16	3
valid_sources[0x1a]	12958	1			T4	8		T14	444		T16	3
valid_sources[0x1b]	12024	1			T4	2		T16	1		T18	14
valid_sources[0x1c]	11366	1			T4	3		T13	7		T14	3
valid_sources[0x1d]	12554	1			T4	3		T13	4		T14	6
valid_sources[0x1e]	13586	1			T4	4		T16	2		T18	11
valid_sources[0x1f]	16573	1			T4	1		T13	7		T16	2
valid_sources[0x20]	13148	1			T4	5		T16	1		T18	14
valid_sources[0x21]	28558	1			T4	1		T16	5		T18	4
valid_sources[0x22]	31724	1			T4	1		T14	364		T16	3
valid_sources[0x23]	10873	1			T4	3		T14	57		T16	4
valid_sources[0x24]	11182	1			T4	2		T13	2		T16	1
valid_sources[0x25]	13675	1			T4	5		T14	2		T16	1
valid_sources[0x26]	17634	1			T4	3		T13	2		T14	40
valid_sources[0x27]	12250	1			T4	5		T13	1		T14	175
valid_sources[0x28]	12624	1			T4	8		T14	50		T16	4
valid_sources[0x29]	12310	1			T4	3		T14	17		T16	6
valid_sources[0x2a]	48027	1			T4	4		T14	20		T16	6
valid_sources[0x2b]	11250	1			T4	6		T14	37		T16	2
valid_sources[0x2c]	12807	1			T4	4		T14	117		T16	6
valid_sources[0x2d]	11344	1			T4	7		T13	2		T14	3
valid_sources[0x2e]	11770	1			T14	10		T16	4		T18	13
valid_sources[0x2f]	12859	1			T4	6		T13	2		T14	126
valid_sources[0x30]	59218	1			T4	2		T14	87		T16	5
valid_sources[0x31]	13160	1			T1	495		T4	8		T14	161
valid_sources[0x32]	12135	1			T4	2		T14	3		T16	3
valid_sources[0x33]	11329	1			T4	3		T14	14		T16	4
valid_sources[0x34]	13985	1			T4	10		T14	35		T16	2
valid_sources[0x35]	13703	1			T4	4		T13	1		T14	158
valid_sources[0x36]	12192	1			T4	5		T14	23		T16	4
valid_sources[0x37]	12798	1			T4	3		T13	2		T14	147
valid_sources[0x38]	10947	1			T13	3		T14	110		T16	6
valid_sources[0x39]	13945	1			T4	6		T13	1		T14	73
valid_sources[0x3a]	13166	1			T4	4		T14	5		T16	4
valid_sources[0x3b]	10980	1			T4	5		T13	4		T14	40
valid_sources[0x3c]	12189	1			T4	6		T13	5		T14	1
valid_sources[0x3d]	11472	1			T4	1		T14	5		T16	2
valid_sources[0x3e]	12162	1			T4	1		T13	2		T14	19
valid_sources[0x3f]	27361	1			T4	7		T18	21		T37	2
valid_sources[0x40]	11461	1			T4	2		T14	50		T16	3
valid_sources[0x41]	14418	1			T4	4		T16	6		T18	9
valid_sources[0x42]	11794	1			T4	7		T14	38		T16	3
valid_sources[0x43]	16203	1			T4	1		T14	52		T16	6
valid_sources[0x44]	11239	1			T4	4		T14	5		T16	8
valid_sources[0x45]	12508	1			T4	8		T16	1		T18	6
valid_sources[0x46]	45703	1			T4	4		T14	5		T16	2
valid_sources[0x47]	12466	1			T4	5		T13	4		T16	5
valid_sources[0x48]	19918	1			T4	1		T14	83		T16	2
valid_sources[0x49]	11406	1			T4	4		T13	3		T16	1
valid_sources[0x4a]	12629	1			T4	3		T13	1		T14	68
valid_sources[0x4b]	13422	1			T4	3		T14	1		T16	7
valid_sources[0x4c]	11343	1			T4	8		T13	1		T14	27
valid_sources[0x4d]	11596	1			T4	8		T13	4		T14	8
valid_sources[0x4e]	11985	1			T4	5		T14	17		T16	7
valid_sources[0x4f]	11863	1			T4	5		T13	2		T14	1
valid_sources[0x50]	12041	1			T13	1		T14	2		T16	1
valid_sources[0x51]	11236	1			T4	5		T14	325		T16	2
valid_sources[0x52]	11253	1			T4	3		T13	10		T14	31
valid_sources[0x53]	11300	1			T14	224		T16	3		T18	20
valid_sources[0x54]	12366	1			T4	6		T13	15		T16	2
valid_sources[0x55]	12921	1			T4	2		T16	4		T18	14
valid_sources[0x56]	45187	1			T4	8		T13	12		T16	2
valid_sources[0x57]	11583	1			T4	1		T14	143		T16	7
valid_sources[0x58]	11446	1			T4	7		T16	1		T18	22
valid_sources[0x59]	13422	1			T4	4		T13	10		T14	260
valid_sources[0x5a]	12437	1			T4	6		T13	1		T16	2
valid_sources[0x5b]	22189	1			T4	4		T13	4		T14	91
valid_sources[0x5c]	12696	1			T4	3		T16	3		T18	10
valid_sources[0x5d]	15359	1			T4	3		T14	431		T16	8
valid_sources[0x5e]	27298	1			T4	1		T16	2		T18	9
valid_sources[0x5f]	11316	1			T4	9		T14	82		T16	4
valid_sources[0x60]	13588	1			T4	1		T13	2		T16	4
valid_sources[0x61]	11634	1			T4	4		T16	4		T18	16
valid_sources[0x62]	14367	1			T4	4		T14	16		T16	1
valid_sources[0x63]	14426	1			T2	2		T4	8		T14	20
valid_sources[0x64]	10913	1			T4	6		T16	2		T18	9
valid_sources[0x65]	11435	1			T4	3		T16	6		T18	9
valid_sources[0x66]	12196	1			T4	7		T14	93		T16	3
valid_sources[0x67]	12121	1			T4	6		T13	4		T16	2
valid_sources[0x68]	12977	1			T4	2		T16	3		T18	15
valid_sources[0x69]	13130	1			T4	5		T13	1		T14	134
valid_sources[0x6a]	11727	1			T4	2		T13	4		T14	5
valid_sources[0x6b]	19339	1			T4	6		T13	5		T14	70
valid_sources[0x6c]	11443	1			T4	7		T14	218		T16	3
valid_sources[0x6d]	121393	1			T4	6		T13	1		T14	6
valid_sources[0x6e]	10964	1			T4	4		T13	5		T14	119
valid_sources[0x6f]	11100	1			T4	4		T14	1		T16	3
valid_sources[0x70]	14697	1			T4	2		T14	48		T16	1
valid_sources[0x71]	13563	1			T4	6		T16	3		T18	11
valid_sources[0x72]	17080	1			T4	4		T14	132		T16	2
valid_sources[0x73]	11833	1			T4	3		T14	24		T16	3
valid_sources[0x74]	13280	1			T4	4		T13	13		T14	4
valid_sources[0x75]	12201	1			T4	5		T13	4		T16	2
valid_sources[0x76]	10840	1			T4	3		T14	1		T16	3
valid_sources[0x77]	11364	1			T4	3		T14	2		T16	3
valid_sources[0x78]	11575	1			T4	4		T16	2		T18	17
valid_sources[0x79]	13041	1			T2	12		T4	5		T14	56
valid_sources[0x7a]	11965	1			T2	3		T4	7		T14	1
valid_sources[0x7b]	16056	1			T13	4		T16	1		T18	17
valid_sources[0x7c]	15350	1			T4	3		T14	1		T16	2
valid_sources[0x7d]	12318	1			T4	3		T13	4		T14	24
valid_sources[0x7e]	13391	1			T4	2		T13	1		T18	19
valid_sources[0x7f]	15026	1			T13	2		T14	4		T16	2
valid_sources[0x80]	11577	1			T4	3		T14	42		T16	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

330212

1

T1

69

T2

1

T3

312

values[0x0]

all_enables

biggest_size

138327

1

T1

96

T2

2

T3

141

values[0x1]

all_enables

biggest_size

123380

1

T1

75

T2

1

T3

139