Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.04 95.95 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 26299025 10916 0 0
attest_sw_binding_0_rd_A 26299025 2949 0 0
attest_sw_binding_1_rd_A 26299025 2960 0 0
attest_sw_binding_2_rd_A 26299025 2991 0 0
attest_sw_binding_3_rd_A 26299025 3334 0 0
attest_sw_binding_4_rd_A 26299025 2820 0 0
attest_sw_binding_5_rd_A 26299025 2971 0 0
attest_sw_binding_6_rd_A 26299025 2990 0 0
attest_sw_binding_7_rd_A 26299025 3100 0 0
intr_enable_rd_A 26299025 3605 0 0
key_version_rd_A 26299025 3004 0 0
max_creator_key_ver_regwen_rd_A 26299025 3104 0 0
max_owner_int_key_ver_regwen_rd_A 26299025 2969 0 0
max_owner_key_ver_regwen_rd_A 26299025 3029 0 0
reseed_interval_regwen_rd_A 26299025 2867 0 0
salt_0_rd_A 26299025 2907 0 0
salt_1_rd_A 26299025 2952 0 0
salt_2_rd_A 26299025 2967 0 0
salt_3_rd_A 26299025 2950 0 0
salt_4_rd_A 26299025 3034 0 0
salt_5_rd_A 26299025 3159 0 0
salt_6_rd_A 26299025 2966 0 0
salt_7_rd_A 26299025 2987 0 0
sealing_sw_binding_0_rd_A 26299025 3095 0 0
sealing_sw_binding_1_rd_A 26299025 2904 0 0
sealing_sw_binding_2_rd_A 26299025 2912 0 0
sealing_sw_binding_3_rd_A 26299025 3011 0 0
sealing_sw_binding_4_rd_A 26299025 2953 0 0
sealing_sw_binding_5_rd_A 26299025 2982 0 0
sealing_sw_binding_6_rd_A 26299025 2861 0 0
sealing_sw_binding_7_rd_A 26299025 2968 0 0
sideload_clear_rd_A 26299025 2880 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 10916 0 0
T6 5920 0 0 0
T38 92790 0 0 0
T43 4963 0 0 0
T47 76197 0 0 0
T48 3718 0 0 0
T49 39299 0 0 0
T76 0 573 0 0
T104 1342 0 0 0
T105 19757 58 0 0
T109 0 94 0 0
T122 0 33 0 0
T124 0 498 0 0
T125 0 33 0 0
T126 0 1260 0 0
T127 0 218 0 0
T128 0 153 0 0
T129 2248 0 0 0
T130 6597 0 0 0
T186 0 1 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2949 0 0
T112 0 190 0 0
T119 0 26 0 0
T125 24789 10 0 0
T147 0 36 0 0
T163 0 18 0 0
T167 0 35 0 0
T169 0 35 0 0
T187 0 24 0 0
T188 0 37 0 0
T189 0 5 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2960 0 0
T112 0 235 0 0
T119 0 15 0 0
T125 24789 1 0 0
T147 0 19 0 0
T163 0 10 0 0
T167 0 52 0 0
T169 0 17 0 0
T187 0 20 0 0
T188 0 27 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 9 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2991 0 0
T112 0 198 0 0
T125 24789 13 0 0
T147 0 21 0 0
T163 0 15 0 0
T167 0 38 0 0
T169 0 33 0 0
T187 0 10 0 0
T188 0 41 0 0
T189 0 14 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 12 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3334 0 0
T112 0 218 0 0
T125 24789 9 0 0
T147 0 10 0 0
T163 0 7 0 0
T167 0 78 0 0
T169 0 13 0 0
T187 0 23 0 0
T188 0 50 0 0
T189 0 9 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 1 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2820 0 0
T112 0 203 0 0
T119 0 19 0 0
T147 0 5 0 0
T163 0 17 0 0
T167 0 30 0 0
T169 27515 15 0 0
T187 0 18 0 0
T188 0 33 0 0
T199 0 16 0 0
T200 0 10 0 0
T201 4852 0 0 0
T202 7117 0 0 0
T203 11827 0 0 0
T204 5709 0 0 0
T205 35016 0 0 0
T206 32021 0 0 0
T207 59770 0 0 0
T208 8961 0 0 0
T209 390033 0 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2971 0 0
T112 0 228 0 0
T125 24789 12 0 0
T147 0 14 0 0
T163 0 22 0 0
T167 0 41 0 0
T169 0 36 0 0
T187 0 8 0 0
T188 0 51 0 0
T189 0 10 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 8 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2990 0 0
T112 0 194 0 0
T119 0 16 0 0
T125 24789 7 0 0
T147 0 20 0 0
T163 0 13 0 0
T167 0 34 0 0
T169 0 7 0 0
T187 0 25 0 0
T188 0 41 0 0
T189 0 7 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3100 0 0
T26 6213 0 0 0
T112 0 174 0 0
T125 0 29 0 0
T147 0 30 0 0
T163 0 8 0 0
T167 0 57 0 0
T169 0 32 0 0
T187 0 15 0 0
T188 0 47 0 0
T189 0 9 0 0
T210 12631 7 0 0
T211 1742 0 0 0
T212 10226 0 0 0
T213 4816 0 0 0
T214 4735 0 0 0
T215 3885 0 0 0
T216 1287 0 0 0
T217 4919 0 0 0
T218 10062 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3605 0 0
T22 6710 0 0 0
T41 177546 10 0 0
T45 0 35 0 0
T50 5124 0 0 0
T55 5465 0 0 0
T56 10132 0 0 0
T59 0 19 0 0
T78 0 60 0 0
T82 868 0 0 0
T83 18656 0 0 0
T84 6132 0 0 0
T85 4713 0 0 0
T86 81795 0 0 0
T125 0 15 0 0
T219 0 57 0 0
T220 0 23 0 0
T221 0 23 0 0
T222 0 21 0 0
T223 0 27 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3004 0 0
T112 0 185 0 0
T125 24789 7 0 0
T147 0 16 0 0
T163 0 16 0 0
T167 0 29 0 0
T169 0 34 0 0
T187 0 4 0 0
T188 0 23 0 0
T189 0 4 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 4 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3104 0 0
T112 0 230 0 0
T125 24789 19 0 0
T147 0 33 0 0
T163 0 26 0 0
T167 0 48 0 0
T169 0 17 0 0
T187 0 15 0 0
T188 0 50 0 0
T189 0 6 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 2 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2969 0 0
T112 0 229 0 0
T119 0 25 0 0
T125 24789 13 0 0
T147 0 9 0 0
T163 0 17 0 0
T167 0 21 0 0
T169 0 31 0 0
T187 0 10 0 0
T188 0 20 0 0
T189 0 7 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3029 0 0
T112 0 202 0 0
T119 0 22 0 0
T125 24789 15 0 0
T147 0 5 0 0
T163 0 15 0 0
T167 0 26 0 0
T169 0 22 0 0
T187 0 22 0 0
T188 0 46 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 7 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2867 0 0
T112 0 205 0 0
T119 0 12 0 0
T147 0 10 0 0
T163 0 17 0 0
T167 0 23 0 0
T169 27515 15 0 0
T187 0 12 0 0
T188 0 28 0 0
T189 0 6 0 0
T199 0 17 0 0
T201 4852 0 0 0
T202 7117 0 0 0
T203 11827 0 0 0
T204 5709 0 0 0
T205 35016 0 0 0
T206 32021 0 0 0
T207 59770 0 0 0
T208 8961 0 0 0
T209 390033 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2907 0 0
T112 0 204 0 0
T125 24789 5 0 0
T147 0 12 0 0
T163 0 10 0 0
T167 0 34 0 0
T169 0 28 0 0
T187 0 15 0 0
T188 0 21 0 0
T189 0 11 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T224 0 9 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2952 0 0
T112 0 208 0 0
T119 0 22 0 0
T147 0 18 0 0
T163 0 20 0 0
T167 0 32 0 0
T169 27515 30 0 0
T187 0 11 0 0
T188 0 31 0 0
T189 0 3 0 0
T199 0 1 0 0
T201 4852 0 0 0
T202 7117 0 0 0
T203 11827 0 0 0
T204 5709 0 0 0
T205 35016 0 0 0
T206 32021 0 0 0
T207 59770 0 0 0
T208 8961 0 0 0
T209 390033 0 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2967 0 0
T112 0 231 0 0
T119 0 11 0 0
T163 0 12 0 0
T167 0 51 0 0
T169 27515 34 0 0
T187 0 12 0 0
T188 0 27 0 0
T189 0 8 0 0
T199 0 3 0 0
T200 0 7 0 0
T201 4852 0 0 0
T202 7117 0 0 0
T203 11827 0 0 0
T204 5709 0 0 0
T205 35016 0 0 0
T206 32021 0 0 0
T207 59770 0 0 0
T208 8961 0 0 0
T209 390033 0 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2950 0 0
T112 0 206 0 0
T125 24789 7 0 0
T147 0 10 0 0
T163 0 24 0 0
T167 0 33 0 0
T169 0 17 0 0
T187 0 5 0 0
T188 0 37 0 0
T189 0 6 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 11 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3034 0 0
T112 0 216 0 0
T119 0 22 0 0
T147 0 53 0 0
T163 0 19 0 0
T167 0 32 0 0
T169 27515 33 0 0
T187 0 4 0 0
T188 0 24 0 0
T189 0 9 0 0
T200 0 10 0 0
T201 4852 0 0 0
T202 7117 0 0 0
T203 11827 0 0 0
T204 5709 0 0 0
T205 35016 0 0 0
T206 32021 0 0 0
T207 59770 0 0 0
T208 8961 0 0 0
T209 390033 0 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3159 0 0
T112 0 207 0 0
T125 24789 12 0 0
T147 0 27 0 0
T163 0 22 0 0
T167 0 16 0 0
T169 0 47 0 0
T187 0 2 0 0
T188 0 43 0 0
T189 0 7 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 6 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2966 0 0
T112 0 192 0 0
T119 0 20 0 0
T125 24789 13 0 0
T147 0 17 0 0
T163 0 15 0 0
T167 0 21 0 0
T169 0 16 0 0
T187 0 18 0 0
T188 0 25 0 0
T189 0 7 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2987 0 0
T112 0 174 0 0
T125 24789 18 0 0
T147 0 37 0 0
T163 0 10 0 0
T167 0 11 0 0
T169 0 26 0 0
T187 0 7 0 0
T188 0 31 0 0
T189 0 8 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 7 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3095 0 0
T112 0 224 0 0
T119 0 9 0 0
T125 24789 29 0 0
T147 0 6 0 0
T163 0 18 0 0
T167 0 39 0 0
T169 0 29 0 0
T187 0 20 0 0
T188 0 34 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T200 0 13 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2904 0 0
T112 0 209 0 0
T119 0 17 0 0
T125 24789 19 0 0
T147 0 9 0 0
T163 0 9 0 0
T167 0 19 0 0
T169 0 34 0 0
T187 0 15 0 0
T188 0 28 0 0
T189 0 3 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2912 0 0
T112 0 200 0 0
T119 0 16 0 0
T125 24789 22 0 0
T147 0 35 0 0
T163 0 4 0 0
T167 0 26 0 0
T169 0 18 0 0
T187 0 39 0 0
T188 0 55 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 4 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 3011 0 0
T112 0 228 0 0
T119 0 19 0 0
T125 24789 9 0 0
T147 0 41 0 0
T163 0 17 0 0
T167 0 54 0 0
T169 0 30 0 0
T187 0 7 0 0
T188 0 49 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 1 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2953 0 0
T112 0 190 0 0
T119 0 19 0 0
T125 24789 7 0 0
T147 0 33 0 0
T163 0 20 0 0
T167 0 32 0 0
T169 0 12 0 0
T187 0 8 0 0
T188 0 47 0 0
T189 0 10 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2982 0 0
T112 0 228 0 0
T125 24789 17 0 0
T147 0 49 0 0
T163 0 19 0 0
T167 0 35 0 0
T169 0 15 0 0
T187 0 3 0 0
T188 0 18 0 0
T189 0 11 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 17 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2861 0 0
T112 0 196 0 0
T119 0 11 0 0
T125 24789 16 0 0
T147 0 11 0 0
T163 0 19 0 0
T167 0 26 0 0
T169 0 28 0 0
T187 0 18 0 0
T188 0 28 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T200 0 4 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2968 0 0
T112 0 213 0 0
T125 24789 18 0 0
T147 0 21 0 0
T163 0 14 0 0
T167 0 27 0 0
T169 0 19 0 0
T187 0 35 0 0
T188 0 45 0 0
T189 0 9 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 6 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26299025 2880 0 0
T112 0 202 0 0
T119 0 36 0 0
T125 24789 20 0 0
T147 0 22 0 0
T163 0 15 0 0
T167 0 30 0 0
T169 0 34 0 0
T187 0 13 0 0
T188 0 35 0 0
T190 12645 0 0 0
T191 17093 0 0 0
T192 31741 0 0 0
T193 1242 0 0 0
T194 6584 0 0 0
T195 8200 0 0 0
T196 4955 0 0 0
T197 4521 0 0 0
T198 19255 0 0 0
T199 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%