Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4456448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

598122

1

T1

655

T2

11

T3

279

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4655099	1			T1	938		T2	1		T3	2031
values[0x0]	198178	1			T1	213		T2	26		T3	117
values[0x1]	201293	1			T1	215		T2	18		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3028489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2026081

1

T1

856

T2

15

T3

877

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13688	1			T1	1		T3	10		T4	13
valid_sources[0x01]	14246	1			T1	8		T3	23		T4	9
valid_sources[0x02]	15645	1			T1	2		T5	11		T13	22
valid_sources[0x03]	17729	1			T1	10		T3	30		T5	6
valid_sources[0x04]	14290	1			T1	3		T3	1		T4	7
valid_sources[0x05]	14170	1			T1	7		T3	38		T4	2
valid_sources[0x06]	15886	1			T1	4		T3	21		T4	4
valid_sources[0x07]	15688	1			T1	1		T3	1		T5	10
valid_sources[0x08]	15225	1			T1	3		T3	8		T4	8
valid_sources[0x09]	19036	1			T1	6		T3	12		T4	1
valid_sources[0x0a]	15172	1			T1	5		T3	10		T4	1
valid_sources[0x0b]	14304	1			T1	4		T3	7		T5	5
valid_sources[0x0c]	20193	1			T1	4		T3	10		T5	11
valid_sources[0x0d]	14329	1			T1	7		T4	9		T5	10
valid_sources[0x0e]	17559	1			T1	5		T2	2		T3	12
valid_sources[0x0f]	37499	1			T1	6		T3	14		T5	14
valid_sources[0x10]	23764	1			T1	3		T5	10		T13	34
valid_sources[0x11]	15471	1			T1	11		T3	7		T5	11
valid_sources[0x12]	39015	1			T1	2		T3	44		T4	3
valid_sources[0x13]	23332	1			T1	8		T3	8		T4	1
valid_sources[0x14]	14506	1			T1	7		T2	2		T3	19
valid_sources[0x15]	14088	1			T1	3		T3	20		T5	7
valid_sources[0x16]	19021	1			T1	2		T3	9		T4	18
valid_sources[0x17]	19053	1			T1	9		T3	14		T5	13
valid_sources[0x18]	14071	1			T1	6		T3	6		T5	7
valid_sources[0x19]	14242	1			T1	9		T3	10		T4	4
valid_sources[0x1a]	20124	1			T1	5		T4	4		T5	6
valid_sources[0x1b]	14179	1			T1	3		T4	3		T5	18
valid_sources[0x1c]	14085	1			T1	8		T2	2		T3	3
valid_sources[0x1d]	16503	1			T1	2		T3	9		T4	2
valid_sources[0x1e]	13694	1			T1	5		T3	10		T5	12
valid_sources[0x1f]	35655	1			T1	2		T3	5		T4	3
valid_sources[0x20]	16257	1			T1	6		T3	4		T4	8
valid_sources[0x21]	15036	1			T1	2		T3	24		T4	2
valid_sources[0x22]	14093	1			T1	7		T4	1		T5	7
valid_sources[0x23]	14187	1			T1	4		T3	21		T4	5
valid_sources[0x24]	16401	1			T1	5		T3	21		T5	12
valid_sources[0x25]	13821	1			T1	6		T3	9		T4	2
valid_sources[0x26]	13866	1			T1	2		T5	9		T13	31
valid_sources[0x27]	15046	1			T1	16		T3	17		T5	9
valid_sources[0x28]	15733	1			T1	4		T5	8		T13	32
valid_sources[0x29]	17620	1			T1	4		T5	7		T13	29
valid_sources[0x2a]	15727	1			T1	6		T3	2		T4	1
valid_sources[0x2b]	15155	1			T1	8		T2	1		T5	6
valid_sources[0x2c]	15693	1			T1	9		T3	23		T5	8
valid_sources[0x2d]	15605	1			T1	2		T3	17		T4	3
valid_sources[0x2e]	50193	1			T1	8		T3	3		T4	4
valid_sources[0x2f]	31669	1			T1	5		T2	2		T3	10
valid_sources[0x30]	15962	1			T1	3		T3	8		T5	9
valid_sources[0x31]	14520	1			T1	5		T3	15		T5	13
valid_sources[0x32]	13982	1			T1	4		T3	2		T5	9
valid_sources[0x33]	15112	1			T1	7		T3	3		T5	8
valid_sources[0x34]	14022	1			T1	4		T2	1		T4	9
valid_sources[0x35]	15635	1			T1	6		T3	14		T5	10
valid_sources[0x36]	13871	1			T1	15		T3	10		T5	14
valid_sources[0x37]	14448	1			T1	3		T3	37		T4	4
valid_sources[0x38]	48833	1			T1	3		T5	11		T13	29
valid_sources[0x39]	17051	1			T1	2		T3	7		T5	10
valid_sources[0x3a]	13669	1			T1	5		T4	2		T5	16
valid_sources[0x3b]	21670	1			T1	8		T3	13		T4	5
valid_sources[0x3c]	28663	1			T1	5		T5	9		T13	27
valid_sources[0x3d]	14648	1			T1	8		T3	6		T4	1
valid_sources[0x3e]	18684	1			T1	7		T3	18		T5	10
valid_sources[0x3f]	14673	1			T1	4		T5	15		T13	24
valid_sources[0x40]	15035	1			T1	6		T2	1		T5	14
valid_sources[0x41]	15351	1			T1	1		T3	22		T4	1
valid_sources[0x42]	14449	1			T1	4		T3	10		T5	13
valid_sources[0x43]	14287	1			T1	2		T3	19		T5	9
valid_sources[0x44]	13908	1			T1	7		T3	8		T5	14
valid_sources[0x45]	13777	1			T1	1		T5	8		T13	28
valid_sources[0x46]	16138	1			T1	9		T2	1		T3	13
valid_sources[0x47]	13567	1			T1	8		T3	32		T5	10
valid_sources[0x48]	24771	1			T1	6		T3	6		T4	3
valid_sources[0x49]	16992	1			T1	3		T2	1		T3	14
valid_sources[0x4a]	20492	1			T1	5		T3	5		T5	6
valid_sources[0x4b]	14103	1			T1	7		T3	1		T5	12
valid_sources[0x4c]	14332	1			T1	7		T3	4		T4	12
valid_sources[0x4d]	14305	1			T1	2		T4	6		T5	12
valid_sources[0x4e]	15203	1			T1	9		T2	1		T4	1
valid_sources[0x4f]	17395	1			T1	2		T5	14		T13	22
valid_sources[0x50]	23353	1			T1	4		T3	25		T5	8
valid_sources[0x51]	16890	1			T1	6		T3	2		T5	12
valid_sources[0x52]	52237	1			T1	5		T3	2		T5	12
valid_sources[0x53]	15378	1			T1	3		T3	25		T5	13
valid_sources[0x54]	13982	1			T1	4		T3	2		T4	11
valid_sources[0x55]	13998	1			T1	7		T3	4		T4	3
valid_sources[0x56]	20734	1			T1	2		T5	12		T13	36
valid_sources[0x57]	14565	1			T1	3		T3	3		T4	11
valid_sources[0x58]	13928	1			T1	8		T3	3		T5	7
valid_sources[0x59]	18753	1			T1	12		T3	7		T5	7
valid_sources[0x5a]	16770	1			T1	3		T4	1		T5	22
valid_sources[0x5b]	15599	1			T1	5		T3	4		T4	4
valid_sources[0x5c]	14612	1			T1	5		T3	6		T4	1
valid_sources[0x5d]	14039	1			T1	10		T3	5		T5	12
valid_sources[0x5e]	14184	1			T1	6		T3	4		T4	2
valid_sources[0x5f]	22088	1			T1	1		T3	12		T5	10
valid_sources[0x60]	15431	1			T1	2		T3	8		T4	2
valid_sources[0x61]	14110	1			T1	15		T4	3		T5	14
valid_sources[0x62]	14236	1			T1	13		T3	1		T4	3
valid_sources[0x63]	15166	1			T1	4		T3	9		T4	5
valid_sources[0x64]	25901	1			T1	3		T3	5		T5	15
valid_sources[0x65]	13848	1			T1	4		T3	9		T4	2
valid_sources[0x66]	16548	1			T1	6		T4	1		T5	16
valid_sources[0x67]	14196	1			T1	5		T3	10		T4	3
valid_sources[0x68]	15430	1			T1	5		T5	9		T13	25
valid_sources[0x69]	15598	1			T1	1		T3	19		T5	17
valid_sources[0x6a]	14648	1			T1	7		T2	1		T3	11
valid_sources[0x6b]	15443	1			T1	8		T3	11		T5	18
valid_sources[0x6c]	13859	1			T1	3		T3	17		T5	6
valid_sources[0x6d]	14451	1			T1	6		T3	4		T5	12
valid_sources[0x6e]	13932	1			T1	8		T3	14		T5	14
valid_sources[0x6f]	13349	1			T1	4		T2	2		T3	15
valid_sources[0x70]	16074	1			T1	8		T3	28		T4	8
valid_sources[0x71]	15863	1			T1	9		T3	10		T4	1
valid_sources[0x72]	14172	1			T1	7		T4	1		T5	5
valid_sources[0x73]	15451	1			T1	7		T5	15		T13	15
valid_sources[0x74]	20023	1			T1	11		T3	4		T4	5
valid_sources[0x75]	16185	1			T1	9		T3	9		T4	4
valid_sources[0x76]	15593	1			T1	3		T2	1		T4	14
valid_sources[0x77]	14828	1			T1	5		T3	6		T5	16
valid_sources[0x78]	17728	1			T1	12		T2	1		T3	9
valid_sources[0x79]	14512	1			T1	5		T4	3		T5	13
valid_sources[0x7a]	320917	1			T1	2		T3	31		T5	19
valid_sources[0x7b]	17582	1			T1	11		T3	15		T5	10
valid_sources[0x7c]	14320	1			T1	7		T3	9		T5	13
valid_sources[0x7d]	15460	1			T1	2		T2	4		T3	36
valid_sources[0x7e]	14468	1			T1	15		T3	1		T4	2
valid_sources[0x7f]	14325	1			T1	6		T4	5		T5	15
valid_sources[0x80]	14958	1			T1	3		T3	14		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

327326

1

T1

330

T3

89

T4

182

values[0x0]

all_enables

biggest_size

142329

1

T1

173

T2

9

T3

96

values[0x1]

all_enables

biggest_size

128467

1

T1

152

T2

2

T3

94