Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	31277852	16242	0	0
attest_sw_binding_0_rd_A	31277852	2104	0	0
attest_sw_binding_1_rd_A	31277852	2061	0	0
attest_sw_binding_2_rd_A	31277852	2253	0	0
attest_sw_binding_3_rd_A	31277852	1955	0	0
attest_sw_binding_4_rd_A	31277852	2057	0	0
attest_sw_binding_5_rd_A	31277852	2089	0	0
attest_sw_binding_6_rd_A	31277852	2252	0	0
attest_sw_binding_7_rd_A	31277852	2123	0	0
intr_enable_rd_A	31277852	2773	0	0
key_version_rd_A	31277852	2121	0	0
max_creator_key_ver_regwen_rd_A	31277852	2010	0	0
max_owner_int_key_ver_regwen_rd_A	31277852	1939	0	0
max_owner_key_ver_regwen_rd_A	31277852	1995	0	0
reseed_interval_regwen_rd_A	31277852	2071	0	0
salt_0_rd_A	31277852	2174	0	0
salt_1_rd_A	31277852	2123	0	0
salt_2_rd_A	31277852	2142	0	0
salt_3_rd_A	31277852	2186	0	0
salt_4_rd_A	31277852	1968	0	0
salt_5_rd_A	31277852	2152	0	0
salt_6_rd_A	31277852	2112	0	0
salt_7_rd_A	31277852	2082	0	0
sealing_sw_binding_0_rd_A	31277852	2046	0	0
sealing_sw_binding_1_rd_A	31277852	2019	0	0
sealing_sw_binding_2_rd_A	31277852	2021	0	0
sealing_sw_binding_3_rd_A	31277852	2034	0	0
sealing_sw_binding_4_rd_A	31277852	2241	0	0
sealing_sw_binding_5_rd_A	31277852	2197	0	0
sealing_sw_binding_6_rd_A	31277852	2100	0	0
sealing_sw_binding_7_rd_A	31277852	2255	0	0
sideload_clear_rd_A	31277852	2120	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	16242	0	0
T35	10628	0	0	0
T36	15471	0	0	0
T45	4843	0	0	0
T50	6339	0	0	0
T51	25812	95	0	0
T54	0	560	0	0
T64	0	174	0	0
T80	6285	0	0	0
T81	10147	0	0	0
T82	21107	0	0	0
T83	7740	0	0	0
T104	20637	0	0	0
T105	0	711	0	0
T117	0	259	0	0
T118	0	96	0	0
T119	0	830	0	0
T120	0	1226	0	0
T122	0	182	0	0
T123	0	201	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2104	0	0
T110	0	34	0	0
T112	0	46	0	0
T130	0	2	0	0
T142	4567	0	0	0
T149	0	47	0	0
T152	0	25	0	0
T167	53225	53	0	0
T168	0	79	0	0
T169	0	228	0	0
T170	0	6	0	0
T171	0	1	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2061	0	0
T110	0	52	0	0
T112	0	60	0	0
T130	0	35	0	0
T142	4567	0	0	0
T149	0	40	0	0
T152	0	35	0	0
T167	53225	66	0	0
T168	0	47	0	0
T169	0	232	0	0
T171	0	1	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	9	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2253	0	0
T110	0	50	0	0
T112	0	69	0	0
T130	0	13	0	0
T142	4567	0	0	0
T149	0	30	0	0
T152	0	36	0	0
T167	53225	75	0	0
T168	0	41	0	0
T169	0	261	0	0
T170	0	2	0	0
T171	0	10	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	1955	0	0
T110	0	38	0	0
T112	0	37	0	0
T130	0	28	0	0
T142	4567	0	0	0
T149	0	30	0	0
T152	0	53	0	0
T167	53225	52	0	0
T168	0	51	0	0
T169	0	204	0	0
T170	0	29	0	0
T171	0	18	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2057	0	0
T110	0	38	0	0
T112	0	59	0	0
T130	0	18	0	0
T142	4567	0	0	0
T149	0	40	0	0
T152	0	51	0	0
T167	53225	40	0	0
T168	0	55	0	0
T169	0	216	0	0
T170	0	7	0	0
T171	0	12	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2089	0	0
T110	0	64	0	0
T112	0	58	0	0
T130	0	17	0	0
T142	4567	0	0	0
T149	0	15	0	0
T152	0	44	0	0
T167	53225	48	0	0
T168	0	73	0	0
T169	0	228	0	0
T170	0	18	0	0
T171	0	16	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2252	0	0
T110	0	44	0	0
T112	0	60	0	0
T130	0	53	0	0
T142	4567	0	0	0
T149	0	58	0	0
T152	0	47	0	0
T167	53225	62	0	0
T168	0	53	0	0
T169	0	246	0	0
T170	0	3	0	0
T171	0	19	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2123	0	0
T110	0	43	0	0
T112	0	37	0	0
T130	0	21	0	0
T142	4567	0	0	0
T149	0	35	0	0
T152	0	59	0	0
T167	53225	61	0	0
T168	0	61	0	0
T169	0	217	0	0
T171	0	14	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T181	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2773	0	0
T8	0	14	0	0
T63	11999	0	0	0
T75	0	12	0	0
T76	0	14	0	0
T79	0	41	0	0
T91	9022	0	0	0
T137	20880	0	0	0
T150	20201	22	0	0
T182	0	43	0	0
T183	0	29	0	0
T184	0	58	0	0
T185	0	32	0	0
T186	0	26	0	0
T187	2961	0	0	0
T188	14139	0	0	0
T189	179285	0	0	0
T190	12250	0	0	0
T191	7769	0	0	0
T192	12675	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2121	0	0
T110	0	32	0	0
T112	0	57	0	0
T130	0	13	0	0
T142	4567	0	0	0
T149	0	54	0	0
T152	0	33	0	0
T167	53225	56	0	0
T168	0	44	0	0
T169	0	241	0	0
T170	0	4	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	7	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2010	0	0
T110	0	37	0	0
T112	0	71	0	0
T130	0	13	0	0
T142	4567	0	0	0
T149	0	59	0	0
T152	0	46	0	0
T167	53225	51	0	0
T168	0	43	0	0
T169	0	236	0	0
T170	0	8	0	0
T171	0	16	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	1939	0	0
T110	0	33	0	0
T112	0	44	0	0
T130	0	29	0	0
T142	4567	0	0	0
T149	0	32	0	0
T152	0	39	0	0
T167	53225	46	0	0
T168	0	46	0	0
T169	0	191	0	0
T170	0	6	0	0
T171	0	10	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	1995	0	0
T110	0	59	0	0
T112	0	51	0	0
T130	0	18	0	0
T142	4567	0	0	0
T149	0	39	0	0
T152	0	45	0	0
T167	53225	36	0	0
T168	0	59	0	0
T169	0	232	0	0
T170	0	7	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T181	0	7	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2071	0	0
T110	0	41	0	0
T112	0	48	0	0
T142	4567	0	0	0
T149	0	37	0	0
T152	0	34	0	0
T167	53225	50	0	0
T168	0	55	0	0
T169	0	239	0	0
T170	0	10	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	8	0	0
T193	0	114	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2174	0	0
T110	0	53	0	0
T112	0	44	0	0
T142	4567	0	0	0
T149	0	42	0	0
T152	0	65	0	0
T167	53225	61	0	0
T168	0	80	0	0
T169	0	267	0	0
T171	0	6	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	11	0	0
T193	0	101	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2123	0	0
T110	0	31	0	0
T112	0	71	0	0
T130	0	27	0	0
T142	4567	0	0	0
T149	0	43	0	0
T152	0	18	0	0
T167	53225	69	0	0
T168	0	71	0	0
T169	0	199	0	0
T170	0	10	0	0
T171	0	22	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2142	0	0
T110	0	18	0	0
T112	0	73	0	0
T130	0	16	0	0
T142	4567	0	0	0
T149	0	49	0	0
T152	0	40	0	0
T167	53225	66	0	0
T168	0	61	0	0
T169	0	209	0	0
T170	0	9	0	0
T171	0	8	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2186	0	0
T110	0	62	0	0
T112	0	55	0	0
T130	0	14	0	0
T142	4567	0	0	0
T149	0	24	0	0
T152	0	55	0	0
T167	53225	44	0	0
T168	0	53	0	0
T169	0	208	0	0
T170	0	15	0	0
T171	0	6	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	1968	0	0
T110	0	21	0	0
T112	0	45	0	0
T130	0	15	0	0
T142	4567	0	0	0
T149	0	45	0	0
T152	0	34	0	0
T167	53225	35	0	0
T168	0	46	0	0
T169	0	194	0	0
T171	0	31	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	9	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2152	0	0
T110	0	48	0	0
T112	0	54	0	0
T130	0	31	0	0
T142	4567	0	0	0
T149	0	45	0	0
T152	0	33	0	0
T167	53225	38	0	0
T168	0	51	0	0
T169	0	234	0	0
T170	0	2	0	0
T171	0	44	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2112	0	0
T110	0	41	0	0
T112	0	53	0	0
T130	0	10	0	0
T142	4567	0	0	0
T149	0	36	0	0
T152	0	13	0	0
T167	53225	70	0	0
T168	0	71	0	0
T169	0	231	0	0
T171	0	21	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	9	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2082	0	0
T48	4155	0	0	0
T50	6339	6	0	0
T67	4435	0	0	0
T71	9857	0	0	0
T72	5163	0	0	0
T81	10147	0	0	0
T82	21107	0	0	0
T83	7740	0	0	0
T84	924	0	0	0
T110	0	38	0	0
T112	0	65	0	0
T130	0	14	0	0
T149	0	25	0	0
T152	0	28	0	0
T167	0	61	0	0
T168	0	50	0	0
T169	0	201	0	0
T170	0	7	0	0
T194	3114	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2046	0	0
T110	0	47	0	0
T112	0	62	0	0
T142	4567	0	0	0
T149	0	31	0	0
T152	0	38	0	0
T167	53225	58	0	0
T168	0	40	0	0
T169	0	211	0	0
T170	0	7	0	0
T171	0	46	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	9	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2019	0	0
T110	0	50	0	0
T112	0	56	0	0
T130	0	32	0	0
T142	4567	0	0	0
T149	0	29	0	0
T152	0	68	0	0
T167	53225	58	0	0
T168	0	46	0	0
T169	0	232	0	0
T170	0	14	0	0
T171	0	3	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2021	0	0
T110	0	33	0	0
T112	0	35	0	0
T130	0	55	0	0
T142	4567	0	0	0
T149	0	50	0	0
T152	0	36	0	0
T167	53225	55	0	0
T168	0	49	0	0
T169	0	230	0	0
T170	0	6	0	0
T171	0	20	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2034	0	0
T110	0	35	0	0
T112	0	63	0	0
T130	0	15	0	0
T142	4567	0	0	0
T149	0	25	0	0
T152	0	54	0	0
T167	53225	45	0	0
T168	0	52	0	0
T169	0	209	0	0
T170	0	26	0	0
T171	0	54	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2241	0	0
T110	0	44	0	0
T112	0	73	0	0
T130	0	35	0	0
T142	4567	0	0	0
T149	0	41	0	0
T152	0	43	0	0
T167	53225	69	0	0
T168	0	81	0	0
T169	0	260	0	0
T170	0	14	0	0
T171	0	19	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2197	0	0
T110	0	32	0	0
T112	0	65	0	0
T130	0	28	0	0
T142	4567	0	0	0
T149	0	43	0	0
T152	0	36	0	0
T167	53225	44	0	0
T168	0	51	0	0
T169	0	222	0	0
T170	0	12	0	0
T171	0	9	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2100	0	0
T110	0	75	0	0
T112	0	65	0	0
T130	0	56	0	0
T142	4567	0	0	0
T149	0	26	0	0
T152	0	39	0	0
T167	53225	42	0	0
T168	0	28	0	0
T169	0	205	0	0
T170	0	4	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T180	0	8	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2255	0	0
T110	0	59	0	0
T112	0	63	0	0
T130	0	43	0	0
T142	4567	0	0	0
T149	0	41	0	0
T152	0	19	0	0
T167	53225	57	0	0
T168	0	47	0	0
T169	0	225	0	0
T170	0	2	0	0
T171	0	27	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31277852	2120	0	0
T110	0	33	0	0
T112	0	56	0	0
T130	0	40	0	0
T142	4567	0	0	0
T149	0	43	0	0
T152	0	30	0	0
T167	53225	54	0	0
T168	0	35	0	0
T169	0	195	0	0
T171	0	27	0	0
T172	7882	0	0	0
T173	40962	0	0	0
T174	26885	0	0	0
T175	9864	0	0	0
T176	6234	0	0	0
T177	5483	0	0	0
T178	17884	0	0	0
T179	1786	0	0	0
T181	0	11	0	0