Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3341964	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

591735

1

T1

660

T2

164

T3

453

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3530929	1			T1	1723		T2	6652		T3	34914
values[0x0]	200674	1			T1	213		T2	52		T3	166
values[0x1]	202096	1			T1	233		T2	47		T3	170

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2285006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1648693

1

T1

1075

T2

2314

T3

11935

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13105	1			T1	6		T2	24		T18	8
valid_sources[0x01]	13309	1			T1	12		T2	27		T12	2
valid_sources[0x02]	13437	1			T1	13		T2	28		T12	1
valid_sources[0x03]	13171	1			T1	6		T2	38		T12	2
valid_sources[0x04]	13660	1			T1	3		T2	30		T12	4
valid_sources[0x05]	13683	1			T1	8		T2	23		T12	3
valid_sources[0x06]	12946	1			T1	18		T2	30		T12	2
valid_sources[0x07]	13145	1			T1	8		T2	32		T12	1
valid_sources[0x08]	14351	1			T1	11		T2	25		T18	4
valid_sources[0x09]	13877	1			T1	10		T2	32		T12	8
valid_sources[0x0a]	13278	1			T1	7		T2	29		T18	5
valid_sources[0x0b]	25029	1			T1	10		T2	28		T12	7
valid_sources[0x0c]	19896	1			T1	14		T2	30		T12	1
valid_sources[0x0d]	15863	1			T1	14		T2	28		T18	4
valid_sources[0x0e]	14084	1			T1	5		T2	29		T12	7
valid_sources[0x0f]	14352	1			T1	4		T2	23		T12	1
valid_sources[0x10]	13737	1			T1	8		T2	26		T12	1
valid_sources[0x11]	13907	1			T1	3		T2	31		T12	5
valid_sources[0x12]	14223	1			T1	7		T2	31		T16	936
valid_sources[0x13]	23590	1			T1	14		T2	27		T12	3
valid_sources[0x14]	13257	1			T1	7		T2	16		T12	8
valid_sources[0x15]	12785	1			T1	8		T2	27		T12	1
valid_sources[0x16]	13130	1			T1	13		T2	23		T18	3
valid_sources[0x17]	12610	1			T1	5		T2	16		T12	3
valid_sources[0x18]	13117	1			T1	3		T2	38		T12	4
valid_sources[0x19]	14331	1			T1	4		T2	18		T12	7
valid_sources[0x1a]	14906	1			T1	3		T2	29		T12	2
valid_sources[0x1b]	13611	1			T1	9		T2	25		T12	4
valid_sources[0x1c]	12898	1			T1	4		T2	23		T12	21
valid_sources[0x1d]	13679	1			T1	7		T2	28		T12	6
valid_sources[0x1e]	15714	1			T1	13		T2	24		T12	1
valid_sources[0x1f]	21299	1			T1	8		T2	27		T12	4
valid_sources[0x20]	13387	1			T1	4		T2	24		T18	3
valid_sources[0x21]	13498	1			T1	7		T2	23		T12	3
valid_sources[0x22]	13128	1			T1	7		T2	27		T12	5
valid_sources[0x23]	12472	1			T1	7		T2	32		T18	4
valid_sources[0x24]	14485	1			T1	4		T2	19		T12	6
valid_sources[0x25]	13122	1			T1	13		T2	33		T12	3
valid_sources[0x26]	14042	1			T1	5		T2	13		T18	7
valid_sources[0x27]	14743	1			T1	5		T2	26		T18	8
valid_sources[0x28]	14406	1			T1	6		T2	25		T12	2
valid_sources[0x29]	14217	1			T1	9		T2	35		T12	8
valid_sources[0x2a]	12748	1			T1	11		T2	28		T12	4
valid_sources[0x2b]	14861	1			T1	8		T2	26		T12	6
valid_sources[0x2c]	14784	1			T1	9		T2	29		T12	4
valid_sources[0x2d]	13018	1			T1	6		T2	35		T12	3
valid_sources[0x2e]	16357	1			T1	20		T2	25		T18	2
valid_sources[0x2f]	14953	1			T1	6		T2	38		T12	3
valid_sources[0x30]	13266	1			T1	3		T2	14		T12	7
valid_sources[0x31]	15126	1			T1	11		T2	23		T12	7
valid_sources[0x32]	12793	1			T1	9		T2	34		T12	5
valid_sources[0x33]	13202	1			T1	10		T2	25		T12	4
valid_sources[0x34]	13432	1			T1	14		T2	35		T12	2
valid_sources[0x35]	12732	1			T1	17		T2	28		T18	8
valid_sources[0x36]	19924	1			T1	11		T2	32		T12	5
valid_sources[0x37]	13357	1			T1	7		T2	34		T12	2
valid_sources[0x38]	14163	1			T1	13		T2	21		T12	14
valid_sources[0x39]	17269	1			T1	3		T2	23		T12	11
valid_sources[0x3a]	25012	1			T1	3		T2	21		T12	10
valid_sources[0x3b]	13150	1			T1	5		T2	31		T12	3
valid_sources[0x3c]	12661	1			T1	6		T2	25		T18	12
valid_sources[0x3d]	15423	1			T1	14		T2	21		T12	4
valid_sources[0x3e]	13745	1			T1	14		T2	32		T12	4
valid_sources[0x3f]	14357	1			T1	7		T2	24		T123	14
valid_sources[0x40]	16742	1			T1	19		T2	26		T18	7
valid_sources[0x41]	12671	1			T1	7		T2	28		T12	3
valid_sources[0x42]	16708	1			T1	8		T2	22		T12	3
valid_sources[0x43]	12796	1			T1	13		T2	26		T12	1
valid_sources[0x44]	14419	1			T1	10		T2	23		T12	10
valid_sources[0x45]	13239	1			T1	8		T2	26		T12	9
valid_sources[0x46]	14327	1			T1	14		T2	23		T12	3
valid_sources[0x47]	12781	1			T1	9		T2	25		T12	1
valid_sources[0x48]	14467	1			T1	9		T2	32		T18	4
valid_sources[0x49]	13521	1			T1	19		T2	14		T12	2
valid_sources[0x4a]	20562	1			T1	10		T2	25		T12	5
valid_sources[0x4b]	13250	1			T1	8		T2	23		T12	10
valid_sources[0x4c]	13261	1			T1	3		T2	26		T18	3
valid_sources[0x4d]	13891	1			T1	11		T2	34		T12	2
valid_sources[0x4e]	14423	1			T1	17		T2	27		T12	6
valid_sources[0x4f]	19177	1			T1	8		T2	24		T12	4
valid_sources[0x50]	28817	1			T1	11		T2	23		T12	3
valid_sources[0x51]	12773	1			T1	8		T2	20		T12	5
valid_sources[0x52]	13022	1			T1	7		T2	26		T12	5
valid_sources[0x53]	17372	1			T1	11		T2	33		T12	4
valid_sources[0x54]	12544	1			T1	11		T2	23		T18	5
valid_sources[0x55]	15061	1			T1	10		T2	27		T12	13
valid_sources[0x56]	17869	1			T1	8		T2	29		T12	2
valid_sources[0x57]	13707	1			T1	9		T2	19		T12	2
valid_sources[0x58]	12574	1			T1	10		T2	29		T12	3
valid_sources[0x59]	14658	1			T1	26		T2	23		T12	1
valid_sources[0x5a]	13137	1			T1	5		T2	25		T12	1
valid_sources[0x5b]	16791	1			T1	7		T2	19		T12	1
valid_sources[0x5c]	13141	1			T1	8		T2	30		T12	7
valid_sources[0x5d]	13211	1			T1	7		T2	20		T12	1
valid_sources[0x5e]	12735	1			T1	8		T2	24		T18	1
valid_sources[0x5f]	48469	1			T1	4		T2	32		T3	35250
valid_sources[0x60]	13185	1			T1	10		T2	22		T12	1
valid_sources[0x61]	13078	1			T1	9		T2	16		T18	2
valid_sources[0x62]	18820	1			T1	9		T2	23		T18	6
valid_sources[0x63]	14239	1			T1	2		T2	30		T18	2
valid_sources[0x64]	15677	1			T1	4		T2	26		T12	1
valid_sources[0x65]	13252	1			T1	14		T2	25		T12	1
valid_sources[0x66]	13766	1			T1	9		T2	26		T18	20
valid_sources[0x67]	12912	1			T1	3		T2	30		T12	7
valid_sources[0x68]	16309	1			T1	17		T2	31		T12	5
valid_sources[0x69]	14214	1			T1	2		T2	23		T12	3
valid_sources[0x6a]	22341	1			T1	14		T2	34		T12	1
valid_sources[0x6b]	13098	1			T1	19		T2	23		T12	11
valid_sources[0x6c]	13558	1			T1	6		T2	22		T18	1
valid_sources[0x6d]	13403	1			T1	7		T2	22		T12	3
valid_sources[0x6e]	13700	1			T1	7		T2	23		T18	4
valid_sources[0x6f]	14676	1			T1	8		T2	23		T12	5
valid_sources[0x70]	14673	1			T1	5		T2	19		T12	1
valid_sources[0x71]	16659	1			T1	8		T2	25		T18	1
valid_sources[0x72]	14661	1			T1	7		T2	27		T18	6
valid_sources[0x73]	14081	1			T1	9		T2	17		T12	7
valid_sources[0x74]	13613	1			T1	11		T2	21		T12	2
valid_sources[0x75]	13324	1			T1	12		T2	24		T12	5
valid_sources[0x76]	12722	1			T1	8		T2	25		T12	3
valid_sources[0x77]	12940	1			T1	16		T2	29		T18	5
valid_sources[0x78]	15210	1			T1	2		T2	22		T12	8
valid_sources[0x79]	17088	1			T1	13		T2	23		T12	3
valid_sources[0x7a]	16510	1			T1	6		T2	34		T12	1
valid_sources[0x7b]	16550	1			T1	11		T2	25		T12	9
valid_sources[0x7c]	15494	1			T1	5		T2	24		T12	5
valid_sources[0x7d]	13403	1			T1	13		T2	26		T18	4
valid_sources[0x7e]	14000	1			T1	7		T2	28		T12	3
valid_sources[0x7f]	13991	1			T1	10		T2	22		T12	1
valid_sources[0x80]	13206	1			T1	4		T2	27		T12	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

317688

1

T1

365

T2

140

T3

205

values[0x0]

all_enables

biggest_size

144617

1

T1

156

T2

17

T3

120

values[0x1]

all_enables

biggest_size

129430

1

T1

139

T2

7

T3

128