Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3756013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601601

1

T1

463

T2

920

T3

3849

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3951002	1			T1	3466		T2	5497		T3	18843
values[0x0]	200937	1			T1	182		T2	299		T3	1253
values[0x1]	205675	1			T1	180		T2	286		T3	1267

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2561944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1795670

1

T1

1577

T2

2519

T3

9203

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15972	1			T1	12		T13	11		T15	28
valid_sources[0x01]	14227	1			T1	12		T13	13		T15	24
valid_sources[0x02]	14470	1			T1	15		T13	12		T15	20
valid_sources[0x03]	15589	1			T1	17		T2	1		T13	7
valid_sources[0x04]	14480	1			T1	25		T13	12		T14	587
valid_sources[0x05]	14020	1			T1	15		T13	10		T15	22
valid_sources[0x06]	15902	1			T1	11		T2	3		T13	15
valid_sources[0x07]	38386	1			T1	9		T13	15		T15	20
valid_sources[0x08]	14461	1			T1	18		T13	8		T15	18
valid_sources[0x09]	19777	1			T1	16		T2	108		T13	16
valid_sources[0x0a]	14175	1			T1	12		T13	11		T15	32
valid_sources[0x0b]	15975	1			T1	19		T13	13		T15	26
valid_sources[0x0c]	17774	1			T1	17		T13	10		T15	31
valid_sources[0x0d]	14355	1			T1	16		T2	8		T13	18
valid_sources[0x0e]	19077	1			T1	8		T2	5		T13	16
valid_sources[0x0f]	14796	1			T1	22		T13	9		T15	40
valid_sources[0x10]	26753	1			T1	14		T13	12		T15	24
valid_sources[0x11]	15313	1			T1	6		T13	17		T15	23
valid_sources[0x12]	15104	1			T1	13		T2	2		T13	9
valid_sources[0x13]	14754	1			T1	13		T2	5		T13	10
valid_sources[0x14]	14086	1			T1	15		T2	1		T13	12
valid_sources[0x15]	15379	1			T1	13		T13	9		T15	33
valid_sources[0x16]	36786	1			T1	16		T13	10		T15	34
valid_sources[0x17]	14415	1			T1	14		T13	14		T15	32
valid_sources[0x18]	18239	1			T1	12		T13	10		T15	28
valid_sources[0x19]	14978	1			T1	7		T13	11		T15	27
valid_sources[0x1a]	16962	1			T1	20		T13	13		T15	38
valid_sources[0x1b]	14179	1			T1	11		T13	9		T15	20
valid_sources[0x1c]	16473	1			T1	18		T13	13		T15	30
valid_sources[0x1d]	17881	1			T1	19		T2	37		T13	4
valid_sources[0x1e]	14026	1			T1	19		T2	319		T13	13
valid_sources[0x1f]	14792	1			T1	24		T13	15		T15	33
valid_sources[0x20]	19912	1			T1	12		T2	2		T13	13
valid_sources[0x21]	17164	1			T1	9		T13	8		T15	25
valid_sources[0x22]	19166	1			T1	18		T13	6		T15	21
valid_sources[0x23]	16380	1			T1	13		T13	12		T15	29
valid_sources[0x24]	13864	1			T1	18		T2	96		T13	10
valid_sources[0x25]	13954	1			T1	27		T13	11		T15	38
valid_sources[0x26]	15153	1			T1	15		T13	8		T15	15
valid_sources[0x27]	14752	1			T1	18		T13	14		T15	34
valid_sources[0x28]	17059	1			T1	19		T2	8		T13	13
valid_sources[0x29]	14263	1			T1	22		T2	59		T13	12
valid_sources[0x2a]	15435	1			T1	10		T2	100		T13	10
valid_sources[0x2b]	16011	1			T1	21		T2	1		T13	12
valid_sources[0x2c]	15817	1			T1	17		T13	8		T15	26
valid_sources[0x2d]	14358	1			T1	22		T13	7		T15	21
valid_sources[0x2e]	14451	1			T1	21		T2	4		T13	23
valid_sources[0x2f]	14121	1			T1	11		T13	14		T15	31
valid_sources[0x30]	13974	1			T1	22		T13	13		T15	21
valid_sources[0x31]	13682	1			T1	15		T13	10		T15	19
valid_sources[0x32]	16591	1			T1	9		T2	258		T13	14
valid_sources[0x33]	14109	1			T1	11		T13	16		T15	38
valid_sources[0x34]	14851	1			T1	13		T13	16		T15	28
valid_sources[0x35]	14496	1			T1	19		T2	3		T13	6
valid_sources[0x36]	23237	1			T1	22		T13	9		T15	16
valid_sources[0x37]	14396	1			T1	16		T2	3		T13	7
valid_sources[0x38]	13920	1			T1	10		T13	12		T15	30
valid_sources[0x39]	14169	1			T1	10		T13	5		T15	23
valid_sources[0x3a]	13379	1			T1	14		T2	1		T13	9
valid_sources[0x3b]	13809	1			T1	16		T2	1		T13	11
valid_sources[0x3c]	14189	1			T1	7		T13	12		T15	28
valid_sources[0x3d]	16612	1			T1	16		T13	19		T15	23
valid_sources[0x3e]	15206	1			T1	19		T2	150		T13	10
valid_sources[0x3f]	14310	1			T1	22		T13	13		T15	24
valid_sources[0x40]	17092	1			T1	14		T2	1		T13	13
valid_sources[0x41]	14302	1			T1	16		T2	6		T13	12
valid_sources[0x42]	14365	1			T1	20		T2	28		T13	6
valid_sources[0x43]	14233	1			T1	9		T13	10		T15	28
valid_sources[0x44]	15366	1			T1	13		T2	28		T13	14
valid_sources[0x45]	14343	1			T1	13		T13	10		T15	28
valid_sources[0x46]	14468	1			T1	17		T2	3		T13	11
valid_sources[0x47]	14244	1			T1	16		T13	14		T15	30
valid_sources[0x48]	14658	1			T1	21		T13	7		T15	21
valid_sources[0x49]	14372	1			T1	22		T13	9		T15	27
valid_sources[0x4a]	15133	1			T1	22		T2	14		T13	7
valid_sources[0x4b]	37883	1			T1	16		T13	11		T15	45
valid_sources[0x4c]	18376	1			T1	11		T13	11		T15	38
valid_sources[0x4d]	56013	1			T1	20		T13	10		T15	39
valid_sources[0x4e]	15592	1			T1	17		T2	21		T13	12
valid_sources[0x4f]	13332	1			T1	13		T13	11		T15	32
valid_sources[0x50]	16127	1			T1	15		T13	7		T15	42
valid_sources[0x51]	14807	1			T1	11		T13	7		T15	41
valid_sources[0x52]	48029	1			T1	14		T13	7		T15	36
valid_sources[0x53]	14975	1			T1	17		T13	9		T15	18
valid_sources[0x54]	14036	1			T1	16		T13	9		T15	38
valid_sources[0x55]	14792	1			T1	14		T2	3		T13	17
valid_sources[0x56]	14796	1			T1	17		T2	3		T13	10
valid_sources[0x57]	15206	1			T1	11		T13	7		T15	26
valid_sources[0x58]	15118	1			T1	8		T13	10		T15	25
valid_sources[0x59]	14490	1			T1	11		T2	6		T13	3
valid_sources[0x5a]	15154	1			T1	14		T2	6		T13	9
valid_sources[0x5b]	14296	1			T1	9		T2	16		T13	15
valid_sources[0x5c]	20395	1			T1	14		T2	1		T13	18
valid_sources[0x5d]	13707	1			T1	13		T13	16		T15	35
valid_sources[0x5e]	14549	1			T1	14		T13	2		T15	34
valid_sources[0x5f]	13992	1			T1	12		T2	7		T13	5
valid_sources[0x60]	32271	1			T1	11		T2	4		T13	14
valid_sources[0x61]	21558	1			T1	12		T2	1		T13	18
valid_sources[0x62]	14060	1			T1	16		T2	124		T13	9
valid_sources[0x63]	14140	1			T1	12		T2	30		T13	11
valid_sources[0x64]	13949	1			T1	15		T13	7		T15	36
valid_sources[0x65]	14059	1			T1	14		T2	24		T13	10
valid_sources[0x66]	22261	1			T1	16		T13	10		T15	30
valid_sources[0x67]	14253	1			T1	20		T2	1		T13	18
valid_sources[0x68]	14165	1			T1	23		T13	8		T15	23
valid_sources[0x69]	14705	1			T1	14		T13	24		T15	25
valid_sources[0x6a]	14287	1			T1	17		T13	10		T15	16
valid_sources[0x6b]	16829	1			T1	15		T13	12		T15	25
valid_sources[0x6c]	35992	1			T1	24		T3	21363		T13	12
valid_sources[0x6d]	14042	1			T1	17		T13	13		T15	21
valid_sources[0x6e]	13609	1			T1	11		T13	2		T15	33
valid_sources[0x6f]	13388	1			T1	15		T13	11		T15	40
valid_sources[0x70]	15824	1			T1	12		T13	10		T15	31
valid_sources[0x71]	14858	1			T1	15		T13	14		T15	17
valid_sources[0x72]	13591	1			T1	17		T2	123		T13	14
valid_sources[0x73]	51726	1			T1	14		T2	7		T13	7
valid_sources[0x74]	15636	1			T1	14		T13	10		T15	27
valid_sources[0x75]	17092	1			T1	19		T13	14		T15	24
valid_sources[0x76]	17314	1			T1	13		T2	3		T13	10
valid_sources[0x77]	19739	1			T1	14		T13	15		T15	40
valid_sources[0x78]	13960	1			T1	12		T13	23		T15	36
valid_sources[0x79]	17664	1			T1	16		T2	4		T13	12
valid_sources[0x7a]	15277	1			T1	12		T13	7		T15	38
valid_sources[0x7b]	14121	1			T1	17		T2	5		T13	13
valid_sources[0x7c]	14743	1			T1	14		T2	5		T13	10
valid_sources[0x7d]	14436	1			T1	13		T2	47		T13	12
valid_sources[0x7e]	27820	1			T1	17		T13	16		T15	35
valid_sources[0x7f]	14082	1			T1	22		T13	16		T15	31
valid_sources[0x80]	14181	1			T1	12		T2	3		T13	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325366

1

T1

245

T2

538

T3

2444

values[0x0]

all_enables

biggest_size

145087

1

T1

113

T2

210

T3

773

values[0x1]

all_enables

biggest_size

131148

1

T1

105

T2

172

T3

632