Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30063194	16719	0	0
attest_sw_binding_0_rd_A	30063194	3006	0	0
attest_sw_binding_1_rd_A	30063194	3128	0	0
attest_sw_binding_2_rd_A	30063194	3001	0	0
attest_sw_binding_3_rd_A	30063194	3029	0	0
attest_sw_binding_4_rd_A	30063194	3025	0	0
attest_sw_binding_5_rd_A	30063194	2977	0	0
attest_sw_binding_6_rd_A	30063194	3139	0	0
attest_sw_binding_7_rd_A	30063194	2952	0	0
intr_enable_rd_A	30063194	3813	0	0
key_version_rd_A	30063194	2999	0	0
max_creator_key_ver_regwen_rd_A	30063194	3105	0	0
max_owner_int_key_ver_regwen_rd_A	30063194	3209	0	0
max_owner_key_ver_regwen_rd_A	30063194	3094	0	0
reseed_interval_regwen_rd_A	30063194	3087	0	0
salt_0_rd_A	30063194	3105	0	0
salt_1_rd_A	30063194	3018	0	0
salt_2_rd_A	30063194	3147	0	0
salt_3_rd_A	30063194	3022	0	0
salt_4_rd_A	30063194	3014	0	0
salt_5_rd_A	30063194	3058	0	0
salt_6_rd_A	30063194	3070	0	0
salt_7_rd_A	30063194	3217	0	0
sealing_sw_binding_0_rd_A	30063194	3061	0	0
sealing_sw_binding_1_rd_A	30063194	2976	0	0
sealing_sw_binding_2_rd_A	30063194	2953	0	0
sealing_sw_binding_3_rd_A	30063194	3030	0	0
sealing_sw_binding_4_rd_A	30063194	3067	0	0
sealing_sw_binding_5_rd_A	30063194	3089	0	0
sealing_sw_binding_6_rd_A	30063194	3070	0	0
sealing_sw_binding_7_rd_A	30063194	3221	0	0
sideload_clear_rd_A	30063194	3060	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	16719	0	0
T47	45532	0	0	0
T54	43186	374	0	0
T55	0	444	0	0
T102	0	78	0	0
T103	3214	0	0	0
T115	0	1766	0	0
T116	0	508	0	0
T117	0	947	0	0
T118	0	858	0	0
T119	0	378	0	0
T120	0	361	0	0
T121	0	228	0	0
T122	145055	0	0	0
T123	4664	0	0	0
T124	114330	0	0	0
T125	27334	0	0	0
T126	10124	0	0	0
T127	1103	0	0	0
T128	1563	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3006	0	0
T31	6513	0	0	0
T102	70326	21	0	0
T106	0	71	0	0
T108	0	31	0	0
T143	0	465	0	0
T173	0	28	0	0
T174	0	22	0	0
T175	0	83	0	0
T176	0	23	0	0
T177	0	34	0	0
T178	0	22	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3128	0	0
T31	6513	0	0	0
T102	70326	27	0	0
T108	0	22	0	0
T143	0	455	0	0
T173	0	20	0	0
T174	0	31	0	0
T175	0	51	0	0
T176	0	23	0	0
T177	0	12	0	0
T178	0	12	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	11	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3001	0	0
T31	6513	0	0	0
T102	70326	15	0	0
T108	0	18	0	0
T143	0	451	0	0
T173	0	42	0	0
T174	0	33	0	0
T175	0	61	0	0
T176	0	33	0	0
T177	0	19	0	0
T178	0	10	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	8	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3029	0	0
T31	6513	0	0	0
T102	70326	43	0	0
T108	0	25	0	0
T140	0	20	0	0
T143	0	510	0	0
T173	0	25	0	0
T174	0	36	0	0
T175	0	67	0	0
T176	0	23	0	0
T177	0	19	0	0
T178	0	8	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3025	0	0
T31	6513	0	0	0
T102	70326	37	0	0
T108	0	27	0	0
T143	0	444	0	0
T173	0	25	0	0
T174	0	35	0	0
T175	0	80	0	0
T176	0	20	0	0
T177	0	20	0	0
T178	0	5	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	6	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	2977	0	0
T31	6513	0	0	0
T102	70326	16	0	0
T108	0	37	0	0
T143	0	485	0	0
T173	0	32	0	0
T174	0	21	0	0
T175	0	59	0	0
T176	0	16	0	0
T177	0	26	0	0
T178	0	4	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	8	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3139	0	0
T31	6513	0	0	0
T102	70326	52	0	0
T108	0	28	0	0
T143	0	564	0	0
T173	0	21	0	0
T174	0	32	0	0
T175	0	53	0	0
T176	0	15	0	0
T177	0	16	0	0
T178	0	6	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	10	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	2952	0	0
T31	6513	0	0	0
T102	70326	36	0	0
T108	0	35	0	0
T143	0	515	0	0
T173	0	25	0	0
T174	0	22	0	0
T175	0	44	0	0
T176	0	26	0	0
T177	0	23	0	0
T178	0	10	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3813	0	0
T3	306324	22	0	0
T13	16621	0	0	0
T14	7279	0	0	0
T15	31482	0	0	0
T16	16334	0	0	0
T17	63696	0	0	0
T18	1912	0	0	0
T19	5459	0	0	0
T20	9254	0	0	0
T39	0	11	0	0
T44	0	15	0	0
T45	0	32	0	0
T58	0	28	0	0
T69	19362	22	0	0
T102	0	68	0	0
T132	0	5	0	0
T173	0	87	0	0
T188	0	47	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	2999	0	0
T31	6513	0	0	0
T102	70326	24	0	0
T108	0	28	0	0
T143	0	514	0	0
T173	0	16	0	0
T174	0	39	0	0
T175	0	49	0	0
T176	0	20	0	0
T177	0	20	0	0
T178	0	15	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T189	0	8	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3105	0	0
T31	6513	0	0	0
T102	70326	30	0	0
T108	0	27	0	0
T143	0	486	0	0
T173	0	28	0	0
T174	0	22	0	0
T175	0	70	0	0
T176	0	57	0	0
T177	0	19	0	0
T178	0	19	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	8	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3209	0	0
T31	6513	0	0	0
T102	70326	24	0	0
T108	0	36	0	0
T143	0	508	0	0
T173	0	38	0	0
T174	0	47	0	0
T175	0	43	0	0
T176	0	45	0	0
T177	0	22	0	0
T178	0	25	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	13	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3094	0	0
T31	6513	0	0	0
T102	70326	28	0	0
T108	0	30	0	0
T143	0	515	0	0
T173	0	20	0	0
T174	0	10	0	0
T175	0	48	0	0
T176	0	29	0	0
T177	0	30	0	0
T178	0	12	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	18	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3087	0	0
T31	6513	0	0	0
T102	70326	26	0	0
T108	0	30	0	0
T143	0	500	0	0
T173	0	18	0	0
T174	0	23	0	0
T175	0	56	0	0
T176	0	51	0	0
T177	0	19	0	0
T178	0	28	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T190	0	8	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3105	0	0
T31	6513	0	0	0
T102	70326	34	0	0
T108	0	33	0	0
T143	0	551	0	0
T173	0	29	0	0
T174	0	19	0	0
T175	0	56	0	0
T176	0	17	0	0
T177	0	21	0	0
T178	0	13	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	5	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3018	0	0
T31	6513	0	0	0
T102	70326	12	0	0
T108	0	28	0	0
T143	0	464	0	0
T173	0	19	0	0
T174	0	42	0	0
T175	0	42	0	0
T176	0	58	0	0
T177	0	28	0	0
T178	0	11	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3147	0	0
T31	6513	0	0	0
T102	70326	38	0	0
T108	0	37	0	0
T143	0	463	0	0
T173	0	19	0	0
T174	0	51	0	0
T175	0	47	0	0
T176	0	34	0	0
T177	0	10	0	0
T178	0	16	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3022	0	0
T31	6513	0	0	0
T102	70326	24	0	0
T108	0	20	0	0
T143	0	501	0	0
T173	0	47	0	0
T174	0	36	0	0
T175	0	55	0	0
T176	0	34	0	0
T177	0	17	0	0
T178	0	16	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	8	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3014	0	0
T31	6513	0	0	0
T102	70326	33	0	0
T108	0	47	0	0
T143	0	479	0	0
T173	0	31	0	0
T174	0	25	0	0
T175	0	72	0	0
T176	0	14	0	0
T177	0	12	0	0
T178	0	9	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	25	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3058	0	0
T31	6513	0	0	0
T102	70326	35	0	0
T108	0	35	0	0
T140	0	11	0	0
T143	0	471	0	0
T173	0	23	0	0
T174	0	17	0	0
T175	0	79	0	0
T176	0	22	0	0
T177	0	20	0	0
T178	0	12	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3070	0	0
T31	6513	0	0	0
T102	70326	32	0	0
T108	0	40	0	0
T143	0	518	0	0
T173	0	10	0	0
T174	0	29	0	0
T175	0	56	0	0
T176	0	37	0	0
T177	0	14	0	0
T178	0	18	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	1	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3217	0	0
T31	6513	0	0	0
T102	70326	43	0	0
T108	0	40	0	0
T143	0	487	0	0
T173	0	22	0	0
T174	0	32	0	0
T175	0	43	0	0
T176	0	39	0	0
T177	0	20	0	0
T178	0	14	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	22	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3061	0	0
T31	6513	0	0	0
T102	70326	31	0	0
T108	0	34	0	0
T143	0	507	0	0
T173	0	31	0	0
T174	0	24	0	0
T175	0	65	0	0
T176	0	53	0	0
T177	0	18	0	0
T178	0	5	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	8	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	2976	0	0
T31	6513	0	0	0
T102	70326	24	0	0
T108	0	27	0	0
T143	0	497	0	0
T173	0	18	0	0
T174	0	22	0	0
T175	0	58	0	0
T176	0	18	0	0
T177	0	9	0	0
T178	0	14	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	13	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	2953	0	0
T31	6513	0	0	0
T102	70326	34	0	0
T108	0	20	0	0
T143	0	477	0	0
T173	0	34	0	0
T174	0	26	0	0
T175	0	64	0	0
T176	0	24	0	0
T177	0	33	0	0
T178	0	26	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	3	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3030	0	0
T31	6513	0	0	0
T102	70326	36	0	0
T108	0	37	0	0
T143	0	481	0	0
T173	0	18	0	0
T174	0	25	0	0
T175	0	58	0	0
T176	0	23	0	0
T177	0	28	0	0
T178	0	10	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	9	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3067	0	0
T31	6513	0	0	0
T102	70326	43	0	0
T143	0	459	0	0
T173	0	22	0	0
T174	0	16	0	0
T175	0	64	0	0
T176	0	31	0	0
T177	0	19	0	0
T178	0	25	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	10	0	0
T191	0	2	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3089	0	0
T31	6513	0	0	0
T102	70326	31	0	0
T108	0	42	0	0
T143	0	514	0	0
T173	0	16	0	0
T174	0	12	0	0
T175	0	65	0	0
T176	0	12	0	0
T177	0	18	0	0
T178	0	3	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	4	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3070	0	0
T31	6513	0	0	0
T102	70326	71	0	0
T108	0	34	0	0
T140	0	16	0	0
T143	0	444	0	0
T173	0	27	0	0
T174	0	41	0	0
T175	0	68	0	0
T176	0	29	0	0
T177	0	21	0	0
T178	0	4	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3221	0	0
T31	6513	0	0	0
T102	70326	21	0	0
T108	0	40	0	0
T140	0	5	0	0
T143	0	495	0	0
T173	0	36	0	0
T174	0	34	0	0
T175	0	79	0	0
T176	0	16	0	0
T177	0	27	0	0
T178	0	11	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30063194	3060	0	0
T31	6513	0	0	0
T102	70326	32	0	0
T108	0	20	0	0
T143	0	461	0	0
T173	0	23	0	0
T174	0	26	0	0
T175	0	52	0	0
T176	0	22	0	0
T177	0	21	0	0
T178	0	13	0	0
T179	2253	0	0	0
T180	10202	0	0	0
T181	126012	0	0	0
T182	58688	0	0	0
T183	32087	0	0	0
T184	7207	0	0	0
T185	13864	0	0	0
T186	24237	0	0	0
T187	0	4	0	0