Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3961725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

612455

1

T1

196

T2

581

T3

370

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4159231	1			T1	429		T2	734		T3	828
values[0x0]	206243	1			T1	51		T2	209		T3	115
values[0x1]	208706	1			T1	60		T2	200		T3	129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2700416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1873764

1

T1

272

T2

689

T3

545

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16388	1			T3	3		T4	20		T13	286
valid_sources[0x01]	33629	1			T3	1		T4	9		T13	306
valid_sources[0x02]	16195	1			T3	3		T4	34		T13	283
valid_sources[0x03]	19969	1			T4	11		T13	329		T14	6
valid_sources[0x04]	16249	1			T3	3		T4	11		T13	309
valid_sources[0x05]	14844	1			T3	3		T4	14		T13	301
valid_sources[0x06]	14927	1			T4	19		T13	296		T14	4
valid_sources[0x07]	15690	1			T3	5		T4	9		T13	279
valid_sources[0x08]	15407	1			T3	1		T4	25		T13	321
valid_sources[0x09]	15011	1			T3	4		T4	27		T13	311
valid_sources[0x0a]	14881	1			T3	1		T4	23		T13	288
valid_sources[0x0b]	15359	1			T4	19		T13	287		T14	5
valid_sources[0x0c]	17858	1			T4	20		T13	291		T14	2
valid_sources[0x0d]	17233	1			T4	10		T13	297		T14	9
valid_sources[0x0e]	15520	1			T3	1		T4	11		T13	285
valid_sources[0x0f]	15023	1			T3	8		T4	18		T13	333
valid_sources[0x10]	15415	1			T3	3		T4	16		T13	287
valid_sources[0x11]	16579	1			T3	6		T4	18		T13	295
valid_sources[0x12]	22007	1			T3	8		T4	11		T13	296
valid_sources[0x13]	15606	1			T3	2		T4	16		T13	317
valid_sources[0x14]	16832	1			T3	3		T4	16		T13	300
valid_sources[0x15]	17947	1			T3	4		T4	31		T13	291
valid_sources[0x16]	14894	1			T3	4		T4	12		T13	300
valid_sources[0x17]	16262	1			T4	36		T13	302		T14	10
valid_sources[0x18]	16885	1			T3	7		T4	12		T13	319
valid_sources[0x19]	26631	1			T3	11		T4	22		T13	311
valid_sources[0x1a]	15453	1			T3	4		T4	15		T13	280
valid_sources[0x1b]	15444	1			T3	6		T4	24		T13	306
valid_sources[0x1c]	15658	1			T3	4		T4	21		T13	258
valid_sources[0x1d]	16443	1			T3	5		T4	16		T13	332
valid_sources[0x1e]	16117	1			T3	7		T4	25		T13	292
valid_sources[0x1f]	16327	1			T3	6		T4	14		T13	290
valid_sources[0x20]	21892	1			T3	4		T4	12		T13	309
valid_sources[0x21]	18957	1			T3	5		T4	8		T13	283
valid_sources[0x22]	18523	1			T3	5		T4	3		T13	314
valid_sources[0x23]	15383	1			T3	8		T4	16		T13	302
valid_sources[0x24]	15787	1			T3	6		T4	15		T13	328
valid_sources[0x25]	16443	1			T3	5		T4	8		T13	306
valid_sources[0x26]	15979	1			T4	11		T13	310		T14	20
valid_sources[0x27]	15393	1			T3	5		T4	17		T13	293
valid_sources[0x28]	38549	1			T3	8		T4	22		T13	300
valid_sources[0x29]	15726	1			T3	5		T4	17		T13	283
valid_sources[0x2a]	14865	1			T3	4		T4	22		T13	303
valid_sources[0x2b]	15109	1			T4	20		T13	269		T14	13
valid_sources[0x2c]	16445	1			T3	3		T4	15		T13	268
valid_sources[0x2d]	23016	1			T3	6		T4	10		T13	327
valid_sources[0x2e]	16690	1			T3	2		T4	14		T13	305
valid_sources[0x2f]	22449	1			T3	1		T4	36		T13	312
valid_sources[0x30]	15588	1			T3	5		T4	16		T13	331
valid_sources[0x31]	15016	1			T3	12		T4	26		T13	294
valid_sources[0x32]	15663	1			T3	7		T4	26		T13	315
valid_sources[0x33]	14848	1			T3	3		T4	27		T13	289
valid_sources[0x34]	15428	1			T3	5		T4	24		T13	277
valid_sources[0x35]	16382	1			T4	17		T13	292		T14	6
valid_sources[0x36]	16053	1			T3	6		T4	18		T13	275
valid_sources[0x37]	16773	1			T4	17		T13	289		T14	8
valid_sources[0x38]	17079	1			T3	3		T4	17		T13	256
valid_sources[0x39]	15303	1			T3	5		T4	6		T13	283
valid_sources[0x3a]	14369	1			T3	7		T4	18		T13	313
valid_sources[0x3b]	15974	1			T3	11		T4	13		T13	306
valid_sources[0x3c]	17529	1			T3	2		T4	27		T13	334
valid_sources[0x3d]	15048	1			T3	9		T4	21		T13	303
valid_sources[0x3e]	14679	1			T4	26		T13	300		T14	2
valid_sources[0x3f]	16258	1			T3	2		T4	34		T13	299
valid_sources[0x40]	16434	1			T3	9		T4	16		T13	303
valid_sources[0x41]	16062	1			T3	5		T4	17		T13	272
valid_sources[0x42]	15140	1			T3	6		T4	14		T13	313
valid_sources[0x43]	18962	1			T3	7		T4	12		T13	321
valid_sources[0x44]	16067	1			T3	5		T4	18		T13	306
valid_sources[0x45]	15196	1			T3	3		T4	18		T13	299
valid_sources[0x46]	15742	1			T3	6		T4	11		T13	275
valid_sources[0x47]	22064	1			T3	1		T4	18		T13	279
valid_sources[0x48]	14982	1			T3	4		T4	38		T13	305
valid_sources[0x49]	14893	1			T3	1		T4	18		T13	279
valid_sources[0x4a]	15572	1			T3	4		T4	17		T13	287
valid_sources[0x4b]	15901	1			T3	4		T4	19		T13	313
valid_sources[0x4c]	14841	1			T4	11		T13	267		T14	4
valid_sources[0x4d]	20465	1			T3	6		T4	10		T13	317
valid_sources[0x4e]	15300	1			T3	6		T4	28		T13	272
valid_sources[0x4f]	15906	1			T3	11		T4	32		T13	315
valid_sources[0x50]	17360	1			T3	1		T4	10		T13	287
valid_sources[0x51]	14987	1			T3	8		T4	21		T13	311
valid_sources[0x52]	15451	1			T4	8		T13	281		T14	10
valid_sources[0x53]	15977	1			T2	1143		T3	6		T4	39
valid_sources[0x54]	15039	1			T4	11		T13	304		T14	20
valid_sources[0x55]	15711	1			T3	3		T4	24		T13	290
valid_sources[0x56]	15105	1			T3	1		T4	14		T13	295
valid_sources[0x57]	50898	1			T3	11		T4	9		T13	288
valid_sources[0x58]	92384	1			T3	8		T4	8		T13	302
valid_sources[0x59]	15253	1			T3	6		T4	6		T13	307
valid_sources[0x5a]	16353	1			T3	4		T4	10		T13	334
valid_sources[0x5b]	19725	1			T4	20		T13	314		T14	7
valid_sources[0x5c]	15170	1			T4	18		T13	296		T14	1
valid_sources[0x5d]	15059	1			T4	15		T13	334		T14	1
valid_sources[0x5e]	15310	1			T3	5		T4	9		T13	301
valid_sources[0x5f]	15132	1			T3	3		T4	7		T13	308
valid_sources[0x60]	15016	1			T3	1		T4	21		T13	286
valid_sources[0x61]	29053	1			T3	10		T4	9		T13	273
valid_sources[0x62]	21290	1			T3	7		T4	41		T13	333
valid_sources[0x63]	14933	1			T3	2		T4	13		T13	313
valid_sources[0x64]	21997	1			T3	1		T4	8		T13	300
valid_sources[0x65]	15620	1			T4	38		T13	330		T14	17
valid_sources[0x66]	16926	1			T3	3		T4	15		T13	317
valid_sources[0x67]	20247	1			T3	1		T4	29		T13	268
valid_sources[0x68]	45121	1			T3	3		T4	6		T13	320
valid_sources[0x69]	15373	1			T3	10		T4	17		T13	280
valid_sources[0x6a]	15497	1			T3	5		T4	9		T13	318
valid_sources[0x6b]	15155	1			T3	4		T4	13		T13	259
valid_sources[0x6c]	23505	1			T3	5		T4	11		T13	284
valid_sources[0x6d]	14765	1			T3	3		T4	19		T13	282
valid_sources[0x6e]	16835	1			T3	5		T4	19		T13	318
valid_sources[0x6f]	16018	1			T3	3		T4	9		T13	299
valid_sources[0x70]	17707	1			T3	1		T4	13		T13	280
valid_sources[0x71]	15812	1			T3	5		T4	9		T13	321
valid_sources[0x72]	23466	1			T3	5		T4	24		T13	297
valid_sources[0x73]	15854	1			T3	7		T4	17		T13	283
valid_sources[0x74]	16606	1			T3	1		T4	6		T13	305
valid_sources[0x75]	15419	1			T3	4		T4	20		T13	281
valid_sources[0x76]	16205	1			T3	3		T4	12		T13	270
valid_sources[0x77]	14934	1			T3	7		T4	15		T13	322
valid_sources[0x78]	15378	1			T3	4		T4	6		T13	301
valid_sources[0x79]	15865	1			T3	3		T4	26		T13	284
valid_sources[0x7a]	18854	1			T3	4		T4	10		T13	335
valid_sources[0x7b]	15013	1			T3	6		T4	22		T13	303
valid_sources[0x7c]	18016	1			T3	2		T4	15		T13	312
valid_sources[0x7d]	15617	1			T3	1		T4	17		T13	351
valid_sources[0x7e]	16198	1			T3	1		T4	5		T13	324
valid_sources[0x7f]	23548	1			T3	2		T4	10		T13	329
valid_sources[0x80]	17628	1			T3	5		T4	15		T13	281

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331609

1

T1

165

T2

311

T3

211

values[0x0]

all_enables

biggest_size

147948

1

T1

21

T2

148

T3

74

values[0x1]

all_enables

biggest_size

132898

1

T1

10

T2

122

T3

85