Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26989801	15680	0	0
attest_sw_binding_0_rd_A	26989801	2219	0	0
attest_sw_binding_1_rd_A	26989801	2182	0	0
attest_sw_binding_2_rd_A	26989801	2090	0	0
attest_sw_binding_3_rd_A	26989801	2140	0	0
attest_sw_binding_4_rd_A	26989801	2200	0	0
attest_sw_binding_5_rd_A	26989801	1969	0	0
attest_sw_binding_6_rd_A	26989801	2087	0	0
attest_sw_binding_7_rd_A	26989801	2252	0	0
intr_enable_rd_A	26989801	2717	0	0
key_version_rd_A	26989801	2146	0	0
max_creator_key_ver_regwen_rd_A	26989801	2072	0	0
max_owner_int_key_ver_regwen_rd_A	26989801	1940	0	0
max_owner_key_ver_regwen_rd_A	26989801	2057	0	0
reseed_interval_regwen_rd_A	26989801	2204	0	0
salt_0_rd_A	26989801	2157	0	0
salt_1_rd_A	26989801	2142	0	0
salt_2_rd_A	26989801	2230	0	0
salt_3_rd_A	26989801	2106	0	0
salt_4_rd_A	26989801	2157	0	0
salt_5_rd_A	26989801	2296	0	0
salt_6_rd_A	26989801	2234	0	0
salt_7_rd_A	26989801	2220	0	0
sealing_sw_binding_0_rd_A	26989801	2170	0	0
sealing_sw_binding_1_rd_A	26989801	2286	0	0
sealing_sw_binding_2_rd_A	26989801	2064	0	0
sealing_sw_binding_3_rd_A	26989801	2323	0	0
sealing_sw_binding_4_rd_A	26989801	2272	0	0
sealing_sw_binding_5_rd_A	26989801	2177	0	0
sealing_sw_binding_6_rd_A	26989801	2182	0	0
sealing_sw_binding_7_rd_A	26989801	2090	0	0
sideload_clear_rd_A	26989801	2126	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	15680	0	0
T56	0	512	0	0
T57	0	891	0	0
T84	6055	0	0	0
T98	11278	366	0	0
T111	0	499	0	0
T112	0	92	0	0
T125	0	89	0	0
T126	0	393	0	0
T127	0	199	0	0
T128	0	566	0	0
T129	9680	0	0	0
T130	10377	0	0	0
T131	4130	0	0	0
T132	87183	0	0	0
T133	12623	0	0	0
T134	2365	0	0	0
T135	1501	0	0	0
T136	6527	0	0	0
T140	0	29	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2219	0	0
T140	28168	22	0	0
T147	0	66	0	0
T149	0	6	0	0
T154	0	60	0	0
T178	0	23	0	0
T179	0	31	0	0
T180	0	19	0	0
T181	0	25	0	0
T182	0	8	0	0
T183	0	8	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2182	0	0
T140	28168	19	0	0
T147	0	50	0	0
T149	0	10	0	0
T154	0	24	0	0
T178	0	13	0	0
T179	0	19	0	0
T180	0	27	0	0
T181	0	7	0	0
T182	0	29	0	0
T183	0	9	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2090	0	0
T140	28168	32	0	0
T147	0	68	0	0
T149	0	4	0	0
T154	0	28	0	0
T178	0	14	0	0
T179	0	21	0	0
T180	0	31	0	0
T181	0	18	0	0
T182	0	27	0	0
T183	0	4	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2140	0	0
T140	28168	37	0	0
T147	0	24	0	0
T149	0	8	0	0
T154	0	41	0	0
T178	0	17	0	0
T179	0	32	0	0
T180	0	32	0	0
T181	0	21	0	0
T182	0	36	0	0
T183	0	6	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2200	0	0
T140	28168	10	0	0
T147	0	81	0	0
T149	0	9	0	0
T154	0	50	0	0
T178	0	13	0	0
T179	0	62	0	0
T180	0	11	0	0
T181	0	3	0	0
T182	0	31	0	0
T183	0	11	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	1969	0	0
T140	28168	36	0	0
T147	0	82	0	0
T150	0	37	0	0
T154	0	22	0	0
T178	0	12	0	0
T179	0	32	0	0
T180	0	25	0	0
T181	0	7	0	0
T182	0	4	0	0
T183	0	11	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2087	0	0
T140	28168	29	0	0
T147	0	9	0	0
T149	0	10	0	0
T150	0	31	0	0
T154	0	42	0	0
T179	0	20	0	0
T180	0	37	0	0
T181	0	36	0	0
T182	0	22	0	0
T183	0	11	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2252	0	0
T140	28168	24	0	0
T147	0	71	0	0
T154	0	33	0	0
T178	0	13	0	0
T179	0	39	0	0
T180	0	28	0	0
T181	0	2	0	0
T182	0	25	0	0
T183	0	9	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0
T193	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2717	0	0
T44	0	28	0	0
T140	0	23	0	0
T175	4123	0	0	0
T178	0	38	0	0
T179	0	33	0	0
T194	112493	28	0	0
T195	0	16	0	0
T196	0	42	0	0
T197	0	31	0	0
T198	0	31	0	0
T199	0	14	0	0
T200	3658	0	0	0
T201	3327	0	0	0
T202	1591	0	0	0
T203	83953	0	0	0
T204	60163	0	0	0
T205	1055	0	0	0
T206	2047	0	0	0
T207	8292	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2146	0	0
T140	28168	23	0	0
T147	0	2	0	0
T149	0	9	0	0
T154	0	32	0	0
T178	0	14	0	0
T179	0	31	0	0
T180	0	27	0	0
T181	0	22	0	0
T182	0	31	0	0
T183	0	6	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2072	0	0
T140	28168	16	0	0
T147	0	4	0	0
T149	0	4	0	0
T154	0	46	0	0
T178	0	3	0	0
T179	0	40	0	0
T180	0	22	0	0
T181	0	27	0	0
T182	0	20	0	0
T183	0	7	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	1940	0	0
T140	28168	41	0	0
T147	0	32	0	0
T150	0	34	0	0
T154	0	40	0	0
T178	0	40	0	0
T179	0	26	0	0
T180	0	16	0	0
T182	0	11	0	0
T183	0	9	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0
T208	0	126	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2057	0	0
T140	28168	15	0	0
T147	0	13	0	0
T149	0	6	0	0
T154	0	18	0	0
T178	0	6	0	0
T179	0	33	0	0
T180	0	40	0	0
T181	0	16	0	0
T182	0	41	0	0
T183	0	15	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2204	0	0
T140	28168	27	0	0
T147	0	34	0	0
T149	0	3	0	0
T154	0	41	0	0
T178	0	19	0	0
T179	0	28	0	0
T180	0	23	0	0
T181	0	19	0	0
T182	0	23	0	0
T183	0	7	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2157	0	0
T140	28168	14	0	0
T147	0	56	0	0
T149	0	10	0	0
T154	0	41	0	0
T178	0	10	0	0
T179	0	34	0	0
T180	0	40	0	0
T181	0	11	0	0
T182	0	26	0	0
T183	0	8	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2142	0	0
T140	28168	8	0	0
T147	0	35	0	0
T150	0	49	0	0
T154	0	47	0	0
T178	0	8	0	0
T179	0	40	0	0
T180	0	37	0	0
T181	0	8	0	0
T182	0	46	0	0
T183	0	1	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2230	0	0
T140	28168	23	0	0
T147	0	53	0	0
T149	0	1	0	0
T154	0	55	0	0
T178	0	7	0	0
T179	0	37	0	0
T180	0	27	0	0
T181	0	27	0	0
T182	0	38	0	0
T183	0	10	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2106	0	0
T140	28168	33	0	0
T147	0	53	0	0
T150	0	44	0	0
T154	0	33	0	0
T178	0	14	0	0
T179	0	19	0	0
T180	0	28	0	0
T181	0	4	0	0
T182	0	20	0	0
T183	0	10	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2157	0	0
T140	28168	29	0	0
T147	0	52	0	0
T150	0	11	0	0
T154	0	41	0	0
T178	0	14	0	0
T179	0	20	0	0
T180	0	36	0	0
T181	0	19	0	0
T182	0	23	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0
T209	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2296	0	0
T140	28168	24	0	0
T147	0	86	0	0
T149	0	6	0	0
T154	0	34	0	0
T178	0	10	0	0
T179	0	51	0	0
T180	0	34	0	0
T181	0	13	0	0
T182	0	25	0	0
T183	0	16	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2234	0	0
T140	28168	24	0	0
T147	0	59	0	0
T149	0	1	0	0
T154	0	47	0	0
T178	0	27	0	0
T179	0	57	0	0
T180	0	24	0	0
T181	0	4	0	0
T182	0	27	0	0
T183	0	17	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2220	0	0
T140	0	35	0	0
T147	0	42	0	0
T154	0	35	0	0
T178	0	21	0	0
T179	0	34	0	0
T180	0	42	0	0
T181	0	5	0	0
T182	0	39	0	0
T183	0	3	0	0
T210	3857	4	0	0
T211	5537	0	0	0
T212	8622	0	0	0
T213	2044	0	0	0
T214	5630	0	0	0
T215	15186	0	0	0
T216	5106	0	0	0
T217	9279	0	0	0
T218	1928	0	0	0
T219	1435	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2170	0	0
T140	28168	20	0	0
T147	0	45	0	0
T150	0	55	0	0
T154	0	33	0	0
T178	0	16	0	0
T179	0	47	0	0
T180	0	26	0	0
T181	0	30	0	0
T182	0	14	0	0
T183	0	3	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2286	0	0
T140	28168	36	0	0
T147	0	56	0	0
T150	0	27	0	0
T154	0	52	0	0
T178	0	16	0	0
T179	0	24	0	0
T180	0	31	0	0
T181	0	6	0	0
T182	0	22	0	0
T183	0	5	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2064	0	0
T140	28168	27	0	0
T147	0	23	0	0
T149	0	13	0	0
T154	0	32	0	0
T178	0	21	0	0
T179	0	20	0	0
T180	0	39	0	0
T181	0	13	0	0
T182	0	23	0	0
T183	0	7	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2323	0	0
T140	28168	25	0	0
T147	0	41	0	0
T149	0	10	0	0
T154	0	25	0	0
T178	0	27	0	0
T179	0	37	0	0
T180	0	42	0	0
T181	0	20	0	0
T182	0	25	0	0
T183	0	12	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2272	0	0
T140	28168	33	0	0
T147	0	54	0	0
T150	0	28	0	0
T154	0	50	0	0
T178	0	14	0	0
T179	0	23	0	0
T180	0	28	0	0
T181	0	39	0	0
T182	0	21	0	0
T183	0	7	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2177	0	0
T140	28168	33	0	0
T147	0	38	0	0
T149	0	8	0	0
T154	0	30	0	0
T178	0	28	0	0
T179	0	20	0	0
T180	0	44	0	0
T181	0	16	0	0
T182	0	9	0	0
T183	0	6	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2182	0	0
T140	28168	28	0	0
T147	0	65	0	0
T150	0	33	0	0
T154	0	38	0	0
T178	0	34	0	0
T179	0	32	0	0
T180	0	40	0	0
T181	0	22	0	0
T182	0	26	0	0
T183	0	11	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2090	0	0
T140	28168	23	0	0
T147	0	30	0	0
T149	0	2	0	0
T154	0	32	0	0
T178	0	24	0	0
T179	0	52	0	0
T180	0	18	0	0
T181	0	20	0	0
T182	0	31	0	0
T183	0	13	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26989801	2126	0	0
T140	28168	23	0	0
T147	0	54	0	0
T150	0	76	0	0
T154	0	37	0	0
T178	0	6	0	0
T179	0	25	0	0
T180	0	27	0	0
T181	0	17	0	0
T182	0	27	0	0
T183	0	11	0	0
T184	8575	0	0	0
T185	33114	0	0	0
T186	20436	0	0	0
T187	1464	0	0	0
T188	3511	0	0	0
T189	3220	0	0	0
T190	11181	0	0	0
T191	23815	0	0	0
T192	5114	0	0	0