Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4226892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

594216

1

T1

167

T2

753

T3

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4423493	1			T1	207		T2	6525		T3	298
values[0x0]	197466	1			T1	70		T2	277		T3	49
values[0x1]	200149	1			T1	74		T2	250		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2874301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1946807

1

T1

207

T2

2801

T3

193

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15256	1			T1	1		T2	28		T3	2
valid_sources[0x01]	15620	1			T2	25		T13	18		T14	3
valid_sources[0x02]	14982	1			T2	30		T3	1		T13	4
valid_sources[0x03]	13228	1			T2	30		T3	1		T14	8
valid_sources[0x04]	20960	1			T2	29		T3	1		T14	9
valid_sources[0x05]	16757	1			T2	25		T3	2		T13	3
valid_sources[0x06]	13821	1			T2	34		T13	18		T14	11
valid_sources[0x07]	42066	1			T2	17		T13	20		T14	27
valid_sources[0x08]	12801	1			T2	26		T3	1		T13	1
valid_sources[0x09]	14916	1			T1	1		T2	14		T13	4
valid_sources[0x0a]	14614	1			T1	1		T2	37		T3	1
valid_sources[0x0b]	112442	1			T2	27		T3	3		T13	19
valid_sources[0x0c]	100784	1			T1	1		T2	29		T13	20
valid_sources[0x0d]	13856	1			T1	1		T2	26		T13	4
valid_sources[0x0e]	15510	1			T2	25		T13	2		T14	8
valid_sources[0x0f]	20248	1			T1	1		T2	24		T4	6791
valid_sources[0x10]	14400	1			T1	2		T2	15		T13	28
valid_sources[0x11]	14608	1			T2	39		T3	1		T13	5
valid_sources[0x12]	91269	1			T1	1		T2	27		T3	4
valid_sources[0x13]	13983	1			T2	26		T3	1		T13	15
valid_sources[0x14]	14065	1			T1	2		T2	29		T3	3
valid_sources[0x15]	15525	1			T1	4		T2	26		T3	2
valid_sources[0x16]	13685	1			T1	1		T2	30		T3	3
valid_sources[0x17]	13918	1			T1	2		T2	16		T3	1
valid_sources[0x18]	15354	1			T1	6		T2	35		T3	2
valid_sources[0x19]	13399	1			T1	1		T2	22		T3	3
valid_sources[0x1a]	18292	1			T1	1		T2	28		T13	15
valid_sources[0x1b]	13984	1			T2	26		T3	2		T13	9
valid_sources[0x1c]	13613	1			T2	19		T3	3		T13	14
valid_sources[0x1d]	20080	1			T1	2		T2	26		T3	1
valid_sources[0x1e]	16145	1			T1	4		T2	37		T3	2
valid_sources[0x1f]	13923	1			T2	26		T14	11		T15	2
valid_sources[0x20]	23269	1			T2	15		T13	13		T14	16
valid_sources[0x21]	26007	1			T2	33		T14	15		T5	60
valid_sources[0x22]	12946	1			T1	3		T2	27		T3	1
valid_sources[0x23]	18270	1			T1	2		T2	38		T3	3
valid_sources[0x24]	14745	1			T1	7		T2	21		T3	1
valid_sources[0x25]	13538	1			T1	2		T2	24		T3	5
valid_sources[0x26]	13539	1			T2	21		T13	43		T14	10
valid_sources[0x27]	13575	1			T1	9		T2	24		T13	16
valid_sources[0x28]	15439	1			T2	27		T3	1		T13	1
valid_sources[0x29]	12891	1			T1	3		T2	30		T3	3
valid_sources[0x2a]	15190	1			T2	35		T3	6		T14	5
valid_sources[0x2b]	41356	1			T2	28		T13	12		T14	23
valid_sources[0x2c]	23316	1			T2	16		T13	10		T14	6
valid_sources[0x2d]	14114	1			T1	4		T2	28		T3	2
valid_sources[0x2e]	13705	1			T1	2		T2	25		T13	12
valid_sources[0x2f]	14377	1			T2	26		T3	1		T13	19
valid_sources[0x30]	16586	1			T1	1		T2	30		T3	1
valid_sources[0x31]	14862	1			T1	2		T2	23		T3	1
valid_sources[0x32]	13650	1			T2	23		T3	1		T13	15
valid_sources[0x33]	13851	1			T2	24		T3	4		T13	6
valid_sources[0x34]	14868	1			T1	2		T2	31		T13	3
valid_sources[0x35]	13791	1			T1	1		T2	32		T3	1
valid_sources[0x36]	22676	1			T2	23		T3	1		T13	1
valid_sources[0x37]	14896	1			T2	45		T13	15		T14	12
valid_sources[0x38]	13050	1			T1	1		T2	31		T13	33
valid_sources[0x39]	14951	1			T2	30		T3	4		T13	11
valid_sources[0x3a]	13491	1			T2	22		T3	1		T14	9
valid_sources[0x3b]	14591	1			T1	1		T2	24		T3	1
valid_sources[0x3c]	20752	1			T1	4		T2	29		T3	1
valid_sources[0x3d]	16543	1			T1	3		T2	19		T3	2
valid_sources[0x3e]	13480	1			T1	1		T2	37		T3	2
valid_sources[0x3f]	13309	1			T1	1		T2	18		T13	1
valid_sources[0x40]	13677	1			T1	1		T2	22		T3	1
valid_sources[0x41]	15961	1			T1	1		T2	21		T3	1
valid_sources[0x42]	19464	1			T1	4		T2	34		T13	2
valid_sources[0x43]	25558	1			T2	18		T3	1		T13	6
valid_sources[0x44]	25852	1			T2	22		T3	3		T14	9
valid_sources[0x45]	17428	1			T1	2		T2	27		T3	4
valid_sources[0x46]	24351	1			T1	1		T2	28		T13	5
valid_sources[0x47]	12843	1			T2	22		T13	60		T14	15
valid_sources[0x48]	13247	1			T1	1		T2	28		T3	1
valid_sources[0x49]	40164	1			T1	2		T2	21		T3	1
valid_sources[0x4a]	14291	1			T1	1		T2	31		T3	2
valid_sources[0x4b]	12963	1			T2	31		T3	6		T13	7
valid_sources[0x4c]	14033	1			T2	37		T3	1		T13	10
valid_sources[0x4d]	13476	1			T1	4		T2	25		T3	4
valid_sources[0x4e]	15589	1			T1	1		T2	35		T3	1
valid_sources[0x4f]	14294	1			T1	1		T2	31		T3	1
valid_sources[0x50]	14954	1			T1	1		T2	24		T3	3
valid_sources[0x51]	15436	1			T2	29		T3	1		T13	10
valid_sources[0x52]	37498	1			T1	2		T2	25		T3	4
valid_sources[0x53]	14643	1			T1	1		T2	20		T3	4
valid_sources[0x54]	26167	1			T1	3		T2	39		T3	2
valid_sources[0x55]	15987	1			T1	3		T2	25		T3	1
valid_sources[0x56]	15736	1			T1	1		T2	25		T14	10
valid_sources[0x57]	17021	1			T1	1		T2	26		T3	2
valid_sources[0x58]	18329	1			T1	1		T2	32		T13	31
valid_sources[0x59]	14768	1			T2	32		T13	5		T14	24
valid_sources[0x5a]	14132	1			T1	1		T2	26		T3	2
valid_sources[0x5b]	15138	1			T1	2		T2	28		T13	10
valid_sources[0x5c]	48994	1			T1	1		T2	32		T3	2
valid_sources[0x5d]	13493	1			T1	1		T2	37		T3	1
valid_sources[0x5e]	17388	1			T1	3		T2	22		T3	2
valid_sources[0x5f]	14984	1			T1	4		T2	22		T3	1
valid_sources[0x60]	13877	1			T1	2		T2	30		T3	4
valid_sources[0x61]	13508	1			T1	1		T2	23		T3	1
valid_sources[0x62]	14759	1			T1	2		T2	23		T3	1
valid_sources[0x63]	14497	1			T1	2		T2	25		T3	3
valid_sources[0x64]	16303	1			T1	1		T2	27		T13	15
valid_sources[0x65]	16771	1			T2	39		T13	4		T14	13
valid_sources[0x66]	17080	1			T1	1		T2	23		T3	3
valid_sources[0x67]	16934	1			T2	44		T3	3		T13	2
valid_sources[0x68]	13454	1			T1	1		T2	24		T3	1
valid_sources[0x69]	13639	1			T1	4		T2	16		T13	18
valid_sources[0x6a]	15993	1			T2	28		T3	1		T13	4
valid_sources[0x6b]	13414	1			T1	2		T2	30		T13	25
valid_sources[0x6c]	13688	1			T1	1		T2	16		T3	2
valid_sources[0x6d]	14524	1			T2	33		T3	2		T13	13
valid_sources[0x6e]	14414	1			T1	1		T2	22		T13	10
valid_sources[0x6f]	14541	1			T1	2		T2	24		T13	25
valid_sources[0x70]	15749	1			T1	2		T2	35		T3	1
valid_sources[0x71]	13029	1			T2	35		T3	2		T13	8
valid_sources[0x72]	15126	1			T1	4		T2	25		T3	3
valid_sources[0x73]	13952	1			T2	35		T13	18		T14	2
valid_sources[0x74]	13660	1			T1	2		T2	28		T3	1
valid_sources[0x75]	15787	1			T2	38		T3	4		T13	23
valid_sources[0x76]	15410	1			T2	26		T3	1		T13	9
valid_sources[0x77]	16977	1			T1	1		T2	27		T13	19
valid_sources[0x78]	18841	1			T1	1		T2	28		T13	11
valid_sources[0x79]	15975	1			T1	1		T2	30		T3	1
valid_sources[0x7a]	13806	1			T1	1		T2	38		T3	1
valid_sources[0x7b]	14514	1			T1	2		T2	36		T3	3
valid_sources[0x7c]	18526	1			T2	21		T3	3		T13	1
valid_sources[0x7d]	17178	1			T1	4		T2	30		T3	1
valid_sources[0x7e]	12637	1			T2	31		T13	15		T14	31
valid_sources[0x7f]	13663	1			T2	35		T3	1		T13	11
valid_sources[0x80]	14888	1			T1	4		T2	20		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

323727

1

T1

79

T2

418

T3

100

values[0x0]

all_enables

biggest_size

142215

1

T1

50

T2

180

T3

23

values[0x1]

all_enables

biggest_size

128274

1

T1

38

T2

155

T3

9