Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30289577	10896	0	0
attest_sw_binding_0_rd_A	30289577	2865	0	0
attest_sw_binding_1_rd_A	30289577	2842	0	0
attest_sw_binding_2_rd_A	30289577	2790	0	0
attest_sw_binding_3_rd_A	30289577	2752	0	0
attest_sw_binding_4_rd_A	30289577	2867	0	0
attest_sw_binding_5_rd_A	30289577	2873	0	0
attest_sw_binding_6_rd_A	30289577	2637	0	0
attest_sw_binding_7_rd_A	30289577	2860	0	0
intr_enable_rd_A	30289577	3646	0	0
key_version_rd_A	30289577	2903	0	0
max_creator_key_ver_regwen_rd_A	30289577	2897	0	0
max_owner_int_key_ver_regwen_rd_A	30289577	2746	0	0
max_owner_key_ver_regwen_rd_A	30289577	2778	0	0
reseed_interval_regwen_rd_A	30289577	2830	0	0
salt_0_rd_A	30289577	2894	0	0
salt_1_rd_A	30289577	2934	0	0
salt_2_rd_A	30289577	2692	0	0
salt_3_rd_A	30289577	2664	0	0
salt_4_rd_A	30289577	2774	0	0
salt_5_rd_A	30289577	2750	0	0
salt_6_rd_A	30289577	2977	0	0
salt_7_rd_A	30289577	2787	0	0
sealing_sw_binding_0_rd_A	30289577	2980	0	0
sealing_sw_binding_1_rd_A	30289577	2794	0	0
sealing_sw_binding_2_rd_A	30289577	2684	0	0
sealing_sw_binding_3_rd_A	30289577	2737	0	0
sealing_sw_binding_4_rd_A	30289577	2824	0	0
sealing_sw_binding_5_rd_A	30289577	2717	0	0
sealing_sw_binding_6_rd_A	30289577	2910	0	0
sealing_sw_binding_7_rd_A	30289577	2925	0	0
sideload_clear_rd_A	30289577	2730	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	10896	0	0
T46	0	499	0	0
T51	0	134	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	180	0	0
T114	0	144	0	0
T115	0	744	0	0
T124	0	205	0	0
T125	0	96	0	0
T126	0	32	0	0
T127	0	26	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T171	0	32	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2865	0	0
T46	0	58	0	0
T47	0	17	0	0
T51	0	62	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	84	0	0
T114	0	7	0	0
T127	0	21	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	57	0	0
T146	0	8	0	0
T185	0	20	0	0
T186	0	30	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2842	0	0
T46	0	72	0	0
T47	0	20	0	0
T51	0	37	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	29	0	0
T114	0	46	0	0
T127	0	23	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	61	0	0
T146	0	21	0	0
T185	0	7	0	0
T186	0	44	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2790	0	0
T46	0	83	0	0
T47	0	23	0	0
T51	0	67	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	63	0	0
T114	0	59	0	0
T127	0	23	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	41	0	0
T146	0	35	0	0
T185	0	43	0	0
T186	0	26	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2752	0	0
T46	0	56	0	0
T47	0	12	0	0
T51	0	72	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	57	0	0
T114	0	22	0	0
T127	0	22	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	24	0	0
T146	0	16	0	0
T185	0	33	0	0
T186	0	21	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2867	0	0
T46	0	109	0	0
T47	0	12	0	0
T51	0	30	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	78	0	0
T114	0	19	0	0
T127	0	28	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	36	0	0
T185	0	39	0	0
T186	0	23	0	0
T187	0	2	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2873	0	0
T46	0	59	0	0
T47	0	14	0	0
T51	0	44	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	91	0	0
T114	0	21	0	0
T127	0	27	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	94	0	0
T146	0	43	0	0
T185	0	28	0	0
T186	0	49	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2637	0	0
T46	0	60	0	0
T47	0	5	0	0
T51	0	46	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	66	0	0
T114	0	26	0	0
T127	0	26	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	25	0	0
T146	0	39	0	0
T185	0	15	0	0
T186	0	32	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2860	0	0
T46	0	77	0	0
T47	0	31	0	0
T51	0	73	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	44	0	0
T114	0	29	0	0
T127	0	29	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	52	0	0
T146	0	4	0	0
T185	0	27	0	0
T186	0	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	3646	0	0
T45	0	83	0	0
T46	0	107	0	0
T51	0	106	0	0
T57	0	57	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	75	0	0
T114	0	25	0	0
T127	0	29	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T188	0	26	0	0
T189	0	54	0	0
T190	0	23	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2903	0	0
T46	0	65	0	0
T47	0	15	0	0
T51	0	34	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	60	0	0
T114	0	25	0	0
T127	0	33	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	13	0	0
T146	0	49	0	0
T185	0	24	0	0
T186	0	34	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2897	0	0
T46	0	75	0	0
T47	0	13	0	0
T51	0	49	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	64	0	0
T114	0	20	0	0
T127	0	15	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	57	0	0
T146	0	44	0	0
T185	0	37	0	0
T186	0	41	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2746	0	0
T46	0	83	0	0
T47	0	9	0	0
T51	0	53	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	65	0	0
T114	0	34	0	0
T127	0	24	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	49	0	0
T146	0	17	0	0
T185	0	52	0	0
T186	0	29	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2778	0	0
T46	0	75	0	0
T47	0	28	0	0
T51	0	42	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	62	0	0
T114	0	39	0	0
T127	0	30	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	43	0	0
T146	0	7	0	0
T185	0	21	0	0
T186	0	44	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2830	0	0
T46	0	61	0	0
T47	0	28	0	0
T51	0	39	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	58	0	0
T114	0	30	0	0
T127	0	10	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	22	0	0
T146	0	25	0	0
T185	0	21	0	0
T186	0	29	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2894	0	0
T46	0	64	0	0
T47	0	27	0	0
T51	0	52	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	65	0	0
T114	0	28	0	0
T127	0	11	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	65	0	0
T146	0	28	0	0
T185	0	27	0	0
T186	0	52	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2934	0	0
T46	0	79	0	0
T47	0	23	0	0
T51	0	55	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	48	0	0
T114	0	39	0	0
T127	0	26	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	48	0	0
T146	0	19	0	0
T185	0	26	0	0
T186	0	49	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2692	0	0
T46	0	54	0	0
T47	0	16	0	0
T51	0	38	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	67	0	0
T114	0	58	0	0
T127	0	31	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	15	0	0
T146	0	34	0	0
T185	0	16	0	0
T186	0	22	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2664	0	0
T46	0	54	0	0
T47	0	22	0	0
T51	0	60	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	54	0	0
T114	0	15	0	0
T127	0	41	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	29	0	0
T146	0	22	0	0
T185	0	45	0	0
T186	0	10	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2774	0	0
T46	0	43	0	0
T47	0	21	0	0
T51	0	50	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	54	0	0
T114	0	26	0	0
T127	0	31	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	35	0	0
T146	0	25	0	0
T185	0	23	0	0
T186	0	51	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2750	0	0
T46	0	64	0	0
T47	0	15	0	0
T51	0	55	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	55	0	0
T114	0	23	0	0
T127	0	40	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	26	0	0
T146	0	38	0	0
T185	0	22	0	0
T186	0	23	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2977	0	0
T46	0	78	0	0
T47	0	40	0	0
T51	0	59	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	84	0	0
T114	0	41	0	0
T127	0	20	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	69	0	0
T146	0	27	0	0
T185	0	37	0	0
T186	0	28	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2787	0	0
T46	0	60	0	0
T47	0	4	0	0
T51	0	40	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	73	0	0
T114	0	44	0	0
T127	0	32	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	55	0	0
T146	0	18	0	0
T185	0	22	0	0
T186	0	21	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2980	0	0
T46	0	63	0	0
T47	0	12	0	0
T51	0	49	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	72	0	0
T114	0	25	0	0
T127	0	28	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	17	0	0
T146	0	8	0	0
T185	0	61	0	0
T186	0	44	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2794	0	0
T46	0	92	0	0
T47	0	25	0	0
T51	0	33	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	48	0	0
T114	0	22	0	0
T127	0	15	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	66	0	0
T146	0	28	0	0
T185	0	37	0	0
T186	0	44	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2684	0	0
T46	0	79	0	0
T47	0	3	0	0
T51	0	78	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	65	0	0
T114	0	13	0	0
T127	0	23	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	8	0	0
T146	0	26	0	0
T185	0	29	0	0
T186	0	21	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2737	0	0
T46	0	34	0	0
T47	0	16	0	0
T51	0	65	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	76	0	0
T114	0	20	0	0
T127	0	31	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	61	0	0
T146	0	42	0	0
T185	0	32	0	0
T186	0	28	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2824	0	0
T46	0	89	0	0
T47	0	28	0	0
T51	0	65	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	68	0	0
T114	0	24	0	0
T127	0	28	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	79	0	0
T146	0	16	0	0
T185	0	33	0	0
T186	0	18	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2717	0	0
T46	0	86	0	0
T47	0	23	0	0
T51	0	45	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	32	0	0
T114	0	34	0	0
T127	0	20	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	13	0	0
T185	0	44	0	0
T186	0	32	0	0
T191	0	7	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2910	0	0
T46	0	81	0	0
T47	0	11	0	0
T51	0	40	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	55	0	0
T114	0	23	0	0
T127	0	32	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	53	0	0
T146	0	49	0	0
T185	0	35	0	0
T186	0	24	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2925	0	0
T46	0	69	0	0
T47	0	15	0	0
T51	0	84	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	63	0	0
T114	0	18	0	0
T127	0	28	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	39	0	0
T146	0	10	0	0
T185	0	21	0	0
T186	0	28	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30289577	2730	0	0
T46	0	49	0	0
T47	0	19	0	0
T51	0	42	0	0
T60	9064	0	0	0
T65	4228	0	0	0
T83	11933	0	0	0
T100	48714	60	0	0
T114	0	25	0	0
T127	0	15	0	0
T129	135360	0	0	0
T130	1087	0	0	0
T131	7188	0	0	0
T132	13609	0	0	0
T133	31230	0	0	0
T134	10496	0	0	0
T145	0	66	0	0
T146	0	5	0	0
T185	0	39	0	0
T186	0	38	0	0