Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4056161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601677

1

T1

141

T2

269

T3

535

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4262360	1			T1	2562		T2	648		T3	990
values[0x0]	196217	1			T1	45		T2	72		T3	216
values[0x1]	199261	1			T1	35		T2	72		T3	236

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2761106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1896732

1

T1

949

T2

389

T3

799

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13725	1			T1	8		T3	3		T5	6
valid_sources[0x01]	15967	1			T1	10		T3	1		T5	2
valid_sources[0x02]	20467	1			T1	7		T2	2		T3	7
valid_sources[0x03]	13155	1			T1	14		T2	1		T3	1
valid_sources[0x04]	18177	1			T1	6		T3	2		T5	9
valid_sources[0x05]	13774	1			T1	6		T2	5		T3	3
valid_sources[0x06]	13393	1			T1	3		T15	10		T4	3
valid_sources[0x07]	20800	1			T1	12		T2	2		T3	7
valid_sources[0x08]	13983	1			T1	11		T3	9		T5	10
valid_sources[0x09]	13662	1			T1	16		T2	2		T3	15
valid_sources[0x0a]	14908	1			T1	8		T3	6		T5	5
valid_sources[0x0b]	14059	1			T1	13		T3	3		T5	2
valid_sources[0x0c]	13393	1			T1	13		T3	3		T5	2
valid_sources[0x0d]	15545	1			T1	11		T2	6		T3	7
valid_sources[0x0e]	15208	1			T1	4		T3	4		T5	5
valid_sources[0x0f]	37261	1			T1	14		T3	5		T5	6
valid_sources[0x10]	14689	1			T1	8		T2	18		T3	7
valid_sources[0x11]	13030	1			T1	12		T3	4		T5	3
valid_sources[0x12]	13850	1			T1	12		T3	4		T5	2
valid_sources[0x13]	13579	1			T1	7		T3	7		T5	10
valid_sources[0x14]	13167	1			T1	13		T3	2		T5	5
valid_sources[0x15]	20250	1			T1	11		T2	2		T3	5
valid_sources[0x16]	13826	1			T1	14		T2	13		T3	9
valid_sources[0x17]	14764	1			T1	5		T3	6		T5	4
valid_sources[0x18]	14136	1			T1	14		T3	4		T5	10
valid_sources[0x19]	28478	1			T1	15		T2	6		T3	5
valid_sources[0x1a]	14722	1			T1	10		T3	10		T5	1
valid_sources[0x1b]	16805	1			T1	4		T3	14		T5	3
valid_sources[0x1c]	14459	1			T1	6		T2	1		T3	1
valid_sources[0x1d]	13979	1			T1	13		T2	1		T3	6
valid_sources[0x1e]	13237	1			T1	8		T2	2		T3	12
valid_sources[0x1f]	13084	1			T1	11		T2	3		T3	5
valid_sources[0x20]	15191	1			T1	11		T3	13		T15	2
valid_sources[0x21]	19500	1			T1	8		T2	1		T3	3
valid_sources[0x22]	14052	1			T1	13		T2	19		T3	2
valid_sources[0x23]	14453	1			T1	10		T2	5		T3	5
valid_sources[0x24]	32204	1			T1	14		T2	7		T3	8
valid_sources[0x25]	13384	1			T1	3		T2	4		T3	7
valid_sources[0x26]	13152	1			T1	7		T2	4		T3	2
valid_sources[0x27]	14658	1			T1	15		T2	3		T3	9
valid_sources[0x28]	16173	1			T1	12		T2	4		T3	6
valid_sources[0x29]	12954	1			T1	5		T2	8		T3	2
valid_sources[0x2a]	15999	1			T1	9		T2	1		T3	5
valid_sources[0x2b]	24188	1			T1	14		T2	1		T3	6
valid_sources[0x2c]	14281	1			T1	4		T2	11		T3	11
valid_sources[0x2d]	13555	1			T1	12		T2	2		T3	8
valid_sources[0x2e]	13550	1			T1	12		T3	10		T5	2
valid_sources[0x2f]	13417	1			T1	21		T2	20		T3	5
valid_sources[0x30]	15980	1			T1	2		T3	1		T15	5
valid_sources[0x31]	14782	1			T1	12		T3	10		T5	2
valid_sources[0x32]	13712	1			T1	14		T3	2		T5	3
valid_sources[0x33]	14718	1			T1	10		T3	6		T5	5
valid_sources[0x34]	13689	1			T1	9		T2	3		T3	4
valid_sources[0x35]	14124	1			T1	12		T2	2		T3	4
valid_sources[0x36]	13730	1			T1	13		T2	2		T3	10
valid_sources[0x37]	13389	1			T1	8		T2	1		T3	7
valid_sources[0x38]	15761	1			T1	6		T3	1		T5	8
valid_sources[0x39]	18107	1			T1	13		T3	9		T15	2
valid_sources[0x3a]	13690	1			T1	3		T2	6		T3	3
valid_sources[0x3b]	13425	1			T1	15		T2	1		T3	11
valid_sources[0x3c]	72405	1			T1	6		T3	1		T5	3
valid_sources[0x3d]	13641	1			T1	7		T2	7		T3	13
valid_sources[0x3e]	14594	1			T1	12		T2	7		T3	1
valid_sources[0x3f]	13199	1			T1	12		T2	1		T3	1
valid_sources[0x40]	13758	1			T1	8		T3	3		T5	5
valid_sources[0x41]	14131	1			T1	14		T2	11		T3	3
valid_sources[0x42]	33590	1			T1	7		T2	6		T3	7
valid_sources[0x43]	33315	1			T1	13		T3	5		T5	6
valid_sources[0x44]	14024	1			T1	14		T2	3		T3	5
valid_sources[0x45]	14273	1			T1	8		T3	5		T5	4
valid_sources[0x46]	14377	1			T1	16		T2	8		T3	7
valid_sources[0x47]	13408	1			T1	8		T2	6		T3	6
valid_sources[0x48]	16615	1			T1	9		T3	5		T5	1
valid_sources[0x49]	14112	1			T1	13		T2	4		T3	8
valid_sources[0x4a]	14328	1			T1	15		T2	1		T3	9
valid_sources[0x4b]	13129	1			T1	11		T3	5		T5	1
valid_sources[0x4c]	14548	1			T1	14		T2	4		T3	1
valid_sources[0x4d]	13751	1			T1	9		T2	1		T3	12
valid_sources[0x4e]	21206	1			T1	8		T2	2		T3	8
valid_sources[0x4f]	159220	1			T1	6		T2	1		T3	2
valid_sources[0x50]	14330	1			T1	9		T3	3		T5	4
valid_sources[0x51]	14486	1			T1	16		T2	5		T3	15
valid_sources[0x52]	14304	1			T1	10		T2	15		T3	4
valid_sources[0x53]	15291	1			T1	7		T3	7		T5	2
valid_sources[0x54]	13205	1			T1	14		T3	5		T5	11
valid_sources[0x55]	14260	1			T1	12		T2	11		T3	3
valid_sources[0x56]	13141	1			T1	28		T3	7		T5	2
valid_sources[0x57]	15556	1			T1	8		T2	9		T3	4
valid_sources[0x58]	16773	1			T1	7		T2	3		T3	3
valid_sources[0x59]	33370	1			T1	7		T3	7		T5	1
valid_sources[0x5a]	15671	1			T1	15		T2	13		T3	2
valid_sources[0x5b]	14773	1			T1	12		T2	13		T3	4
valid_sources[0x5c]	14123	1			T1	9		T3	1		T5	1
valid_sources[0x5d]	14936	1			T1	12		T5	6		T15	7
valid_sources[0x5e]	16049	1			T1	11		T3	3		T15	1
valid_sources[0x5f]	14497	1			T1	14		T2	3		T3	9
valid_sources[0x60]	17554	1			T1	4		T2	2		T3	3
valid_sources[0x61]	14805	1			T1	11		T2	9		T3	15
valid_sources[0x62]	26394	1			T1	14		T3	1		T15	1
valid_sources[0x63]	13750	1			T1	9		T2	8		T3	3
valid_sources[0x64]	18599	1			T1	10		T2	7		T3	6
valid_sources[0x65]	15755	1			T1	13		T3	5		T5	4
valid_sources[0x66]	15878	1			T1	12		T3	3		T5	2
valid_sources[0x67]	13642	1			T1	14		T2	1		T3	4
valid_sources[0x68]	16329	1			T1	9		T3	8		T5	6
valid_sources[0x69]	13862	1			T1	11		T2	2		T3	3
valid_sources[0x6a]	15235	1			T1	14		T3	9		T5	1
valid_sources[0x6b]	13628	1			T1	3		T3	7		T5	3
valid_sources[0x6c]	13051	1			T1	9		T2	6		T3	1
valid_sources[0x6d]	13580	1			T1	12		T2	2		T3	11
valid_sources[0x6e]	13840	1			T1	11		T2	4		T3	3
valid_sources[0x6f]	15627	1			T1	12		T2	3		T3	7
valid_sources[0x70]	13081	1			T1	5		T2	3		T3	5
valid_sources[0x71]	13884	1			T1	7		T3	5		T5	3
valid_sources[0x72]	17881	1			T1	7		T5	8		T15	1
valid_sources[0x73]	14989	1			T1	9		T2	1		T3	5
valid_sources[0x74]	13366	1			T1	9		T2	2		T3	7
valid_sources[0x75]	13696	1			T1	9		T3	9		T5	7
valid_sources[0x76]	16348	1			T1	7		T3	6		T5	6
valid_sources[0x77]	13135	1			T1	14		T3	5		T5	6
valid_sources[0x78]	13682	1			T1	11		T2	1		T3	7
valid_sources[0x79]	23111	1			T1	15		T2	7		T3	9
valid_sources[0x7a]	22573	1			T1	7		T2	10		T3	6
valid_sources[0x7b]	16851	1			T1	6		T2	8		T3	3
valid_sources[0x7c]	14048	1			T1	13		T3	3		T5	7
valid_sources[0x7d]	14972	1			T1	9		T2	3		T3	4
valid_sources[0x7e]	13901	1			T1	9		T2	4		T3	8
valid_sources[0x7f]	13712	1			T1	9		T2	3		T3	10
valid_sources[0x80]	13878	1			T1	13		T2	2		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333222

1

T1

119

T2

227

T3

224

values[0x0]

all_enables

biggest_size

141126

1

T1

16

T2

28

T3

159

values[0x1]

all_enables

biggest_size

127329

1

T1

6

T2

14

T3

152