Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30264418	14097	0	0
attest_sw_binding_0_rd_A	30264418	3010	0	0
attest_sw_binding_1_rd_A	30264418	3074	0	0
attest_sw_binding_2_rd_A	30264418	3121	0	0
attest_sw_binding_3_rd_A	30264418	2983	0	0
attest_sw_binding_4_rd_A	30264418	2965	0	0
attest_sw_binding_5_rd_A	30264418	3172	0	0
attest_sw_binding_6_rd_A	30264418	3074	0	0
attest_sw_binding_7_rd_A	30264418	3287	0	0
intr_enable_rd_A	30264418	3742	0	0
key_version_rd_A	30264418	3292	0	0
max_creator_key_ver_regwen_rd_A	30264418	3367	0	0
max_owner_int_key_ver_regwen_rd_A	30264418	3189	0	0
max_owner_key_ver_regwen_rd_A	30264418	3100	0	0
reseed_interval_regwen_rd_A	30264418	2962	0	0
salt_0_rd_A	30264418	3173	0	0
salt_1_rd_A	30264418	3081	0	0
salt_2_rd_A	30264418	2965	0	0
salt_3_rd_A	30264418	3172	0	0
salt_4_rd_A	30264418	3215	0	0
salt_5_rd_A	30264418	3121	0	0
salt_6_rd_A	30264418	3272	0	0
salt_7_rd_A	30264418	3166	0	0
sealing_sw_binding_0_rd_A	30264418	3176	0	0
sealing_sw_binding_1_rd_A	30264418	3146	0	0
sealing_sw_binding_2_rd_A	30264418	3257	0	0
sealing_sw_binding_3_rd_A	30264418	3064	0	0
sealing_sw_binding_4_rd_A	30264418	3157	0	0
sealing_sw_binding_5_rd_A	30264418	3117	0	0
sealing_sw_binding_6_rd_A	30264418	3135	0	0
sealing_sw_binding_7_rd_A	30264418	3099	0	0
sideload_clear_rd_A	30264418	3213	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	14097	0	0
T8	0	154	0	0
T25	11034	0	0	0
T33	9665	0	0	0
T44	0	631	0	0
T50	22716	612	0	0
T51	57708	0	0	0
T63	8003	0	0	0
T66	9251	0	0	0
T67	37179	881	0	0
T122	0	962	0	0
T123	0	888	0	0
T124	0	468	0	0
T125	0	468	0	0
T126	0	515	0	0
T127	4783	0	0	0
T128	3562	0	0	0
T129	899	0	0	0
T164	0	192	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3010	0	0
T8	21307	21	0	0
T60	28725	0	0	0
T78	0	20	0	0
T111	0	107	0	0
T113	0	67	0	0
T119	0	16	0	0
T130	2633	0	0	0
T142	0	15	0	0
T165	0	18	0	0
T166	0	42	0	0
T167	0	13	0	0
T168	0	17	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3074	0	0
T8	21307	9	0	0
T60	28725	0	0	0
T78	0	45	0	0
T111	0	93	0	0
T113	0	65	0	0
T119	0	29	0	0
T130	2633	0	0	0
T142	0	9	0	0
T165	0	13	0	0
T166	0	37	0	0
T167	0	15	0	0
T168	0	22	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3121	0	0
T8	21307	24	0	0
T60	28725	0	0	0
T78	0	13	0	0
T111	0	125	0	0
T113	0	121	0	0
T119	0	17	0	0
T130	2633	0	0	0
T142	0	6	0	0
T165	0	18	0	0
T166	0	55	0	0
T167	0	33	0	0
T168	0	10	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	2983	0	0
T8	21307	8	0	0
T60	28725	0	0	0
T78	0	18	0	0
T111	0	88	0	0
T113	0	110	0	0
T119	0	15	0	0
T130	2633	0	0	0
T142	0	4	0	0
T165	0	7	0	0
T166	0	60	0	0
T167	0	13	0	0
T168	0	8	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	2965	0	0
T8	21307	3	0	0
T60	28725	0	0	0
T78	0	19	0	0
T111	0	125	0	0
T113	0	95	0	0
T119	0	31	0	0
T130	2633	0	0	0
T142	0	9	0	0
T165	0	5	0	0
T166	0	56	0	0
T167	0	16	0	0
T168	0	16	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3172	0	0
T8	21307	12	0	0
T60	28725	0	0	0
T78	0	5	0	0
T111	0	159	0	0
T113	0	86	0	0
T118	0	100	0	0
T119	0	33	0	0
T130	2633	0	0	0
T142	0	8	0	0
T166	0	74	0	0
T167	0	18	0	0
T168	0	31	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3074	0	0
T8	21307	24	0	0
T60	28725	0	0	0
T78	0	21	0	0
T111	0	167	0	0
T113	0	102	0	0
T119	0	32	0	0
T130	2633	0	0	0
T142	0	15	0	0
T165	0	23	0	0
T166	0	43	0	0
T167	0	14	0	0
T168	0	18	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3287	0	0
T8	21307	12	0	0
T60	28725	0	0	0
T78	0	27	0	0
T111	0	134	0	0
T113	0	90	0	0
T119	0	23	0	0
T130	2633	0	0	0
T142	0	10	0	0
T165	0	15	0	0
T166	0	83	0	0
T167	0	10	0	0
T168	0	20	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3742	0	0
T8	0	41	0	0
T61	105261	18	0	0
T76	0	42	0	0
T78	0	33	0	0
T90	14995	0	0	0
T165	0	36	0	0
T166	0	75	0	0
T176	0	18	0	0
T177	0	10	0	0
T178	0	22	0	0
T179	0	75	0	0
T180	24625	0	0	0
T181	3127	0	0	0
T182	16165	0	0	0
T183	6915	0	0	0
T184	9348	0	0	0
T185	7504	0	0	0
T186	2067	0	0	0
T187	13386	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3292	0	0
T8	21307	18	0	0
T60	28725	0	0	0
T78	0	19	0	0
T111	0	135	0	0
T113	0	76	0	0
T119	0	47	0	0
T130	2633	0	0	0
T142	0	18	0	0
T165	0	9	0	0
T166	0	57	0	0
T167	0	12	0	0
T168	0	25	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3367	0	0
T8	21307	9	0	0
T60	28725	0	0	0
T78	0	22	0	0
T111	0	144	0	0
T113	0	97	0	0
T119	0	46	0	0
T130	2633	0	0	0
T142	0	3	0	0
T165	0	27	0	0
T166	0	51	0	0
T167	0	18	0	0
T168	0	9	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3189	0	0
T8	21307	10	0	0
T60	28725	0	0	0
T78	0	28	0	0
T111	0	128	0	0
T113	0	98	0	0
T119	0	34	0	0
T130	2633	0	0	0
T142	0	8	0	0
T165	0	9	0	0
T166	0	39	0	0
T167	0	16	0	0
T168	0	14	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3100	0	0
T8	21307	14	0	0
T60	28725	0	0	0
T78	0	27	0	0
T111	0	92	0	0
T113	0	69	0	0
T119	0	29	0	0
T130	2633	0	0	0
T142	0	15	0	0
T165	0	14	0	0
T166	0	33	0	0
T167	0	19	0	0
T168	0	5	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	2962	0	0
T8	21307	18	0	0
T60	28725	0	0	0
T78	0	11	0	0
T111	0	118	0	0
T113	0	87	0	0
T119	0	47	0	0
T130	2633	0	0	0
T142	0	14	0	0
T165	0	18	0	0
T166	0	51	0	0
T167	0	2	0	0
T168	0	8	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3173	0	0
T8	21307	2	0	0
T60	28725	0	0	0
T78	0	31	0	0
T111	0	99	0	0
T113	0	101	0	0
T119	0	32	0	0
T130	2633	0	0	0
T142	0	12	0	0
T165	0	23	0	0
T166	0	58	0	0
T167	0	17	0	0
T168	0	9	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3081	0	0
T8	21307	14	0	0
T60	28725	0	0	0
T78	0	28	0	0
T111	0	134	0	0
T113	0	77	0	0
T119	0	38	0	0
T130	2633	0	0	0
T142	0	14	0	0
T165	0	19	0	0
T166	0	45	0	0
T167	0	5	0	0
T168	0	15	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	2965	0	0
T8	21307	14	0	0
T60	28725	0	0	0
T78	0	37	0	0
T111	0	122	0	0
T113	0	84	0	0
T119	0	41	0	0
T130	2633	0	0	0
T142	0	9	0	0
T165	0	2	0	0
T166	0	55	0	0
T167	0	11	0	0
T168	0	9	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3172	0	0
T8	21307	15	0	0
T60	28725	0	0	0
T78	0	10	0	0
T111	0	138	0	0
T113	0	98	0	0
T119	0	37	0	0
T130	2633	0	0	0
T142	0	7	0	0
T165	0	14	0	0
T166	0	55	0	0
T167	0	1	0	0
T168	0	27	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3215	0	0
T8	21307	9	0	0
T60	28725	0	0	0
T78	0	33	0	0
T111	0	203	0	0
T113	0	108	0	0
T119	0	57	0	0
T130	2633	0	0	0
T142	0	11	0	0
T165	0	10	0	0
T166	0	47	0	0
T167	0	5	0	0
T168	0	7	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3121	0	0
T8	21307	24	0	0
T60	28725	0	0	0
T78	0	20	0	0
T111	0	114	0	0
T113	0	81	0	0
T119	0	31	0	0
T130	2633	0	0	0
T142	0	2	0	0
T165	0	9	0	0
T166	0	41	0	0
T167	0	19	0	0
T168	0	15	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3272	0	0
T8	21307	4	0	0
T60	28725	0	0	0
T78	0	24	0	0
T111	0	168	0	0
T113	0	100	0	0
T119	0	20	0	0
T130	2633	0	0	0
T142	0	9	0	0
T165	0	17	0	0
T166	0	54	0	0
T167	0	10	0	0
T168	0	12	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3166	0	0
T8	21307	22	0	0
T60	28725	0	0	0
T78	0	21	0	0
T111	0	140	0	0
T113	0	101	0	0
T119	0	39	0	0
T130	2633	0	0	0
T142	0	6	0	0
T165	0	8	0	0
T166	0	91	0	0
T167	0	15	0	0
T168	0	10	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3176	0	0
T8	21307	21	0	0
T60	28725	0	0	0
T78	0	24	0	0
T111	0	142	0	0
T113	0	113	0	0
T119	0	33	0	0
T130	2633	0	0	0
T142	0	2	0	0
T165	0	10	0	0
T166	0	78	0	0
T167	0	21	0	0
T168	0	19	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3146	0	0
T8	21307	12	0	0
T60	28725	0	0	0
T78	0	25	0	0
T111	0	145	0	0
T113	0	89	0	0
T119	0	46	0	0
T130	2633	0	0	0
T142	0	10	0	0
T165	0	11	0	0
T166	0	43	0	0
T167	0	3	0	0
T168	0	17	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3257	0	0
T8	21307	13	0	0
T60	28725	0	0	0
T78	0	17	0	0
T111	0	117	0	0
T113	0	102	0	0
T119	0	16	0	0
T130	2633	0	0	0
T142	0	9	0	0
T165	0	34	0	0
T166	0	60	0	0
T167	0	15	0	0
T168	0	23	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3064	0	0
T8	21307	15	0	0
T60	28725	0	0	0
T78	0	35	0	0
T111	0	113	0	0
T113	0	90	0	0
T119	0	29	0	0
T130	2633	0	0	0
T142	0	7	0	0
T165	0	14	0	0
T166	0	43	0	0
T167	0	15	0	0
T168	0	19	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3157	0	0
T8	21307	19	0	0
T60	28725	0	0	0
T78	0	23	0	0
T111	0	98	0	0
T113	0	86	0	0
T119	0	32	0	0
T130	2633	0	0	0
T142	0	1	0	0
T165	0	28	0	0
T166	0	40	0	0
T167	0	19	0	0
T168	0	15	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3117	0	0
T8	0	14	0	0
T52	3275	0	0	0
T57	0	9	0	0
T59	8439	9	0	0
T78	0	21	0	0
T111	0	87	0	0
T113	0	103	0	0
T165	0	12	0	0
T166	0	70	0	0
T167	0	34	0	0
T168	0	5	0	0
T188	6099	0	0	0
T189	5854	0	0	0
T190	3062	0	0	0
T191	1330	0	0	0
T192	3474	0	0	0
T193	99106	0	0	0
T194	4585	0	0	0
T195	13334	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3135	0	0
T8	21307	11	0	0
T60	28725	0	0	0
T78	0	25	0	0
T111	0	141	0	0
T113	0	75	0	0
T119	0	14	0	0
T130	2633	0	0	0
T142	0	4	0	0
T165	0	32	0	0
T166	0	52	0	0
T167	0	23	0	0
T168	0	7	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3099	0	0
T8	21307	20	0	0
T60	28725	0	0	0
T78	0	19	0	0
T111	0	126	0	0
T113	0	112	0	0
T119	0	21	0	0
T130	2633	0	0	0
T142	0	16	0	0
T165	0	8	0	0
T166	0	53	0	0
T167	0	18	0	0
T168	0	17	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30264418	3213	0	0
T8	21307	16	0	0
T60	28725	0	0	0
T78	0	28	0	0
T111	0	102	0	0
T113	0	108	0	0
T119	0	65	0	0
T130	2633	0	0	0
T142	0	8	0	0
T165	0	31	0	0
T166	0	59	0	0
T167	0	15	0	0
T168	0	17	0	0
T169	9041	0	0	0
T170	117515	0	0	0
T171	3636	0	0	0
T172	2115	0	0	0
T173	3915	0	0	0
T174	4075	0	0	0
T175	7482	0	0	0