Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4683281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

626010

1

T1

140

T2

108

T3

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4900217	1			T1	462		T2	426		T3	1592
values[0x0]	204024	1			T1	43		T2	37		T3	29
values[0x1]	205050	1			T1	36		T2	28		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3185355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2123936

1

T1

247

T2

227

T3

611

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19292	1			T1	6		T3	23		T4	8
valid_sources[0x01]	16684	1			T1	1		T3	18		T4	8
valid_sources[0x02]	16049	1			T1	1		T3	12		T4	14
valid_sources[0x03]	23953	1			T2	62		T4	13		T5	4
valid_sources[0x04]	18593	1			T1	6		T4	9		T5	6
valid_sources[0x05]	15353	1			T4	15		T5	1		T18	14
valid_sources[0x06]	17270	1			T4	11		T5	3		T17	4
valid_sources[0x07]	20537	1			T3	5		T4	10		T18	14
valid_sources[0x08]	17064	1			T2	7		T3	12		T4	8
valid_sources[0x09]	16804	1			T2	18		T4	9		T5	3
valid_sources[0x0a]	19116	1			T1	1		T3	16		T4	10
valid_sources[0x0b]	17658	1			T1	6		T4	11		T5	3
valid_sources[0x0c]	20642	1			T3	6		T4	17		T5	3
valid_sources[0x0d]	16887	1			T4	10		T18	19		T19	1
valid_sources[0x0e]	20229	1			T3	6		T4	8		T17	4
valid_sources[0x0f]	16130	1			T1	2		T3	1		T4	7
valid_sources[0x10]	16966	1			T1	1		T3	5		T4	9
valid_sources[0x11]	17904	1			T3	8		T4	7		T5	3
valid_sources[0x12]	15984	1			T4	12		T5	5		T17	2
valid_sources[0x13]	16764	1			T3	5		T4	11		T5	2
valid_sources[0x14]	17323	1			T3	9		T4	10		T5	1
valid_sources[0x15]	18356	1			T3	21		T4	5		T5	3
valid_sources[0x16]	24223	1			T3	2		T4	7		T17	3
valid_sources[0x17]	18946	1			T1	1		T3	2		T4	3
valid_sources[0x18]	17292	1			T1	5		T3	4		T4	8
valid_sources[0x19]	16906	1			T3	7		T4	10		T5	3
valid_sources[0x1a]	16725	1			T1	1		T4	8		T17	4
valid_sources[0x1b]	16278	1			T3	3		T4	10		T5	1
valid_sources[0x1c]	17751	1			T1	2		T4	7		T5	3
valid_sources[0x1d]	26517	1			T1	8		T3	9		T4	6
valid_sources[0x1e]	28549	1			T4	9		T17	8		T18	27
valid_sources[0x1f]	16340	1			T4	6		T17	8		T18	33
valid_sources[0x20]	17667	1			T1	3		T3	13		T4	11
valid_sources[0x21]	27371	1			T3	1		T4	12		T5	1
valid_sources[0x22]	24135	1			T3	4		T4	4		T5	3
valid_sources[0x23]	45658	1			T3	4		T4	14		T5	5
valid_sources[0x24]	16960	1			T1	4		T4	4		T5	2
valid_sources[0x25]	18313	1			T4	9		T5	2		T18	19
valid_sources[0x26]	15969	1			T3	2		T4	13		T17	6
valid_sources[0x27]	16260	1			T3	9		T4	10		T18	27
valid_sources[0x28]	17071	1			T4	4		T17	1		T18	13
valid_sources[0x29]	16581	1			T2	25		T3	10		T4	5
valid_sources[0x2a]	20599	1			T3	21		T4	10		T5	3
valid_sources[0x2b]	16021	1			T1	4		T3	5		T4	17
valid_sources[0x2c]	22053	1			T4	1		T5	1		T17	2
valid_sources[0x2d]	20126	1			T4	12		T18	23		T19	1
valid_sources[0x2e]	18969	1			T1	12		T4	10		T5	6
valid_sources[0x2f]	16546	1			T1	2		T3	9		T4	13
valid_sources[0x30]	16595	1			T4	8		T5	2		T17	2
valid_sources[0x31]	27306	1			T1	1		T4	7		T17	3
valid_sources[0x32]	16239	1			T3	11		T4	11		T5	1
valid_sources[0x33]	42950	1			T1	2		T3	19		T4	5
valid_sources[0x34]	15787	1			T4	13		T17	7		T18	23
valid_sources[0x35]	16882	1			T1	2		T3	25		T4	9
valid_sources[0x36]	36507	1			T4	9		T5	2		T18	19
valid_sources[0x37]	15914	1			T3	3		T4	7		T5	3
valid_sources[0x38]	21822	1			T1	2		T3	1		T4	8
valid_sources[0x39]	17341	1			T4	9		T18	28		T19	1
valid_sources[0x3a]	18874	1			T1	4		T4	12		T5	3
valid_sources[0x3b]	17598	1			T1	1		T3	13		T4	10
valid_sources[0x3c]	16845	1			T1	3		T3	1		T4	8
valid_sources[0x3d]	28569	1			T4	14		T17	3		T18	32
valid_sources[0x3e]	17003	1			T1	1		T4	6		T5	1
valid_sources[0x3f]	15810	1			T3	8		T4	5		T5	1
valid_sources[0x40]	18907	1			T1	1		T3	12		T4	14
valid_sources[0x41]	16747	1			T4	6		T18	27		T19	3
valid_sources[0x42]	17550	1			T3	3		T4	13		T18	25
valid_sources[0x43]	22109	1			T4	10		T5	1		T18	22
valid_sources[0x44]	20510	1			T3	5		T4	21		T5	2
valid_sources[0x45]	15863	1			T1	6		T4	6		T5	3
valid_sources[0x46]	22411	1			T2	12		T4	9		T17	2
valid_sources[0x47]	28029	1			T1	3		T3	9		T4	8
valid_sources[0x48]	18707	1			T1	16		T3	10		T4	9
valid_sources[0x49]	19237	1			T1	6		T2	10		T3	21
valid_sources[0x4a]	17710	1			T3	26		T4	6		T5	7
valid_sources[0x4b]	18283	1			T4	10		T5	1		T18	27
valid_sources[0x4c]	16318	1			T3	22		T4	4		T17	8
valid_sources[0x4d]	25411	1			T3	2		T4	13		T17	7
valid_sources[0x4e]	17612	1			T3	7		T4	11		T18	22
valid_sources[0x4f]	16249	1			T4	5		T5	1		T18	21
valid_sources[0x50]	20584	1			T3	8		T4	13		T5	4
valid_sources[0x51]	27797	1			T3	13		T4	16		T5	3
valid_sources[0x52]	17514	1			T1	1		T4	11		T5	2
valid_sources[0x53]	17545	1			T3	21		T4	11		T5	3
valid_sources[0x54]	33778	1			T1	20		T4	3		T17	3
valid_sources[0x55]	39609	1			T1	8		T3	1		T4	13
valid_sources[0x56]	21708	1			T3	1		T4	10		T5	1
valid_sources[0x57]	16453	1			T3	10		T4	19		T5	5
valid_sources[0x58]	32210	1			T1	3		T2	110		T3	10
valid_sources[0x59]	16020	1			T4	7		T5	1		T17	8
valid_sources[0x5a]	16174	1			T3	1		T4	10		T5	2
valid_sources[0x5b]	19945	1			T3	18		T4	10		T5	6
valid_sources[0x5c]	26373	1			T3	13		T4	9		T5	2
valid_sources[0x5d]	16782	1			T1	3		T3	1		T4	7
valid_sources[0x5e]	17738	1			T4	11		T5	1		T18	13
valid_sources[0x5f]	33790	1			T4	16		T5	4		T17	5
valid_sources[0x60]	20181	1			T1	1		T4	15		T17	12
valid_sources[0x61]	23157	1			T4	12		T5	1		T18	18
valid_sources[0x62]	19284	1			T1	7		T3	7		T4	5
valid_sources[0x63]	19776	1			T1	4		T3	19		T4	14
valid_sources[0x64]	25846	1			T1	3		T4	13		T17	7
valid_sources[0x65]	16558	1			T1	6		T4	3		T5	13
valid_sources[0x66]	15699	1			T3	9		T4	15		T18	25
valid_sources[0x67]	16262	1			T3	16		T4	10		T5	9
valid_sources[0x68]	16223	1			T4	16		T18	19		T19	3
valid_sources[0x69]	15877	1			T1	3		T3	19		T4	18
valid_sources[0x6a]	21252	1			T1	7		T3	15		T4	7
valid_sources[0x6b]	16768	1			T1	11		T3	2		T4	3
valid_sources[0x6c]	23755	1			T4	9		T17	1		T18	16
valid_sources[0x6d]	16475	1			T3	5		T4	10		T5	4
valid_sources[0x6e]	20949	1			T3	15		T4	16		T17	3
valid_sources[0x6f]	30138	1			T3	10		T4	13		T5	3
valid_sources[0x70]	16936	1			T3	14		T4	12		T5	1
valid_sources[0x71]	16154	1			T1	1		T3	29		T4	11
valid_sources[0x72]	18060	1			T1	4		T4	4		T17	5
valid_sources[0x73]	16634	1			T4	17		T17	9		T18	27
valid_sources[0x74]	16693	1			T1	3		T4	10		T5	3
valid_sources[0x75]	19277	1			T3	28		T4	6		T5	4
valid_sources[0x76]	17632	1			T3	15		T4	10		T5	1
valid_sources[0x77]	24274	1			T1	5		T4	16		T5	2
valid_sources[0x78]	16902	1			T1	2		T3	2		T4	6
valid_sources[0x79]	16187	1			T3	14		T4	10		T5	1
valid_sources[0x7a]	18322	1			T2	10		T3	4		T4	10
valid_sources[0x7b]	16820	1			T4	14		T5	2		T17	3
valid_sources[0x7c]	16647	1			T1	5		T3	15		T4	11
valid_sources[0x7d]	19556	1			T4	8		T5	1		T17	2
valid_sources[0x7e]	18992	1			T1	2		T4	5		T17	5
valid_sources[0x7f]	17876	1			T1	4		T2	19		T4	12
valid_sources[0x80]	23305	1			T3	35		T4	12		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

351042

1

T1

118

T2

63

T3

115

values[0x0]

all_enables

biggest_size

145380

1

T1

18

T2

24

T3

11

values[0x1]

all_enables

biggest_size

129588

1

T1

4

T2

21

T3

6