Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
30306880 |
30134489 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30306880 |
30134489 |
0 |
0 |
T1 |
4915 |
4824 |
0 |
0 |
T2 |
5364 |
5298 |
0 |
0 |
T3 |
14641 |
14551 |
0 |
0 |
T4 |
24905 |
24812 |
0 |
0 |
T5 |
2149 |
2086 |
0 |
0 |
T15 |
5634 |
5572 |
0 |
0 |
T16 |
27103 |
27050 |
0 |
0 |
T17 |
7837 |
7767 |
0 |
0 |
T18 |
20738 |
20641 |
0 |
0 |
T19 |
4035 |
3973 |
0 |
0 |