Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	32829498	12185	0	0
attest_sw_binding_0_rd_A	32829498	3736	0	0
attest_sw_binding_1_rd_A	32829498	3872	0	0
attest_sw_binding_2_rd_A	32829498	3827	0	0
attest_sw_binding_3_rd_A	32829498	3885	0	0
attest_sw_binding_4_rd_A	32829498	3549	0	0
attest_sw_binding_5_rd_A	32829498	3935	0	0
attest_sw_binding_6_rd_A	32829498	3744	0	0
attest_sw_binding_7_rd_A	32829498	3794	0	0
intr_enable_rd_A	32829498	4630	0	0
key_version_rd_A	32829498	3757	0	0
max_creator_key_ver_regwen_rd_A	32829498	3857	0	0
max_owner_int_key_ver_regwen_rd_A	32829498	3827	0	0
max_owner_key_ver_regwen_rd_A	32829498	3834	0	0
reseed_interval_regwen_rd_A	32829498	3895	0	0
salt_0_rd_A	32829498	3764	0	0
salt_1_rd_A	32829498	3922	0	0
salt_2_rd_A	32829498	3811	0	0
salt_3_rd_A	32829498	3724	0	0
salt_4_rd_A	32829498	3987	0	0
salt_5_rd_A	32829498	3763	0	0
salt_6_rd_A	32829498	3813	0	0
salt_7_rd_A	32829498	3845	0	0
sealing_sw_binding_0_rd_A	32829498	3795	0	0
sealing_sw_binding_1_rd_A	32829498	3940	0	0
sealing_sw_binding_2_rd_A	32829498	3691	0	0
sealing_sw_binding_3_rd_A	32829498	3869	0	0
sealing_sw_binding_4_rd_A	32829498	3711	0	0
sealing_sw_binding_5_rd_A	32829498	3870	0	0
sealing_sw_binding_6_rd_A	32829498	3741	0	0
sealing_sw_binding_7_rd_A	32829498	3812	0	0
sideload_clear_rd_A	32829498	3786	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	12185	0	0
T4	24905	60	0	0
T5	2149	0	0	0
T7	0	765	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	231	0	0
T62	0	128	0	0
T71	0	316	0	0
T78	0	194	0	0
T101	0	13	0	0
T125	0	1119	0	0
T126	0	618	0	0
T129	0	976	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3736	0	0
T4	24905	22	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	48	0	0
T101	0	30	0	0
T114	0	86	0	0
T115	0	132	0	0
T167	0	16	0	0
T168	0	15	0	0
T169	0	29	0	0
T170	0	55	0	0
T171	0	1	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3872	0	0
T4	24905	6	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	53	0	0
T101	0	30	0	0
T114	0	150	0	0
T115	0	102	0	0
T167	0	34	0	0
T168	0	30	0	0
T169	0	27	0	0
T170	0	74	0	0
T171	0	1	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3827	0	0
T4	24905	20	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	26	0	0
T101	0	17	0	0
T114	0	131	0	0
T115	0	130	0	0
T167	0	18	0	0
T168	0	20	0	0
T169	0	31	0	0
T170	0	74	0	0
T172	0	1	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3885	0	0
T4	24905	16	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	41	0	0
T101	0	26	0	0
T114	0	133	0	0
T115	0	135	0	0
T167	0	29	0	0
T168	0	18	0	0
T169	0	20	0	0
T170	0	47	0	0
T171	0	5	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3549	0	0
T4	24905	22	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	27	0	0
T101	0	11	0	0
T114	0	120	0	0
T115	0	129	0	0
T167	0	25	0	0
T168	0	20	0	0
T169	0	17	0	0
T170	0	58	0	0
T171	0	3	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3935	0	0
T4	24905	18	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	29	0	0
T101	0	46	0	0
T114	0	105	0	0
T115	0	94	0	0
T167	0	26	0	0
T168	0	26	0	0
T169	0	18	0	0
T170	0	35	0	0
T171	0	4	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3744	0	0
T4	24905	6	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	34	0	0
T101	0	27	0	0
T114	0	127	0	0
T115	0	107	0	0
T120	0	32	0	0
T167	0	23	0	0
T168	0	48	0	0
T169	0	24	0	0
T170	0	53	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3794	0	0
T4	24905	34	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	17	0	0
T101	0	34	0	0
T114	0	99	0	0
T115	0	99	0	0
T120	0	17	0	0
T167	0	33	0	0
T168	0	24	0	0
T169	0	19	0	0
T170	0	75	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	4630	0	0
T4	24905	15	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T57	0	29	0	0
T60	0	40	0	0
T101	0	56	0	0
T167	0	31	0	0
T173	0	1	0	0
T174	0	7	0	0
T175	0	4	0	0
T176	0	71	0	0
T177	0	19	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3757	0	0
T4	24905	18	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	25	0	0
T101	0	36	0	0
T114	0	111	0	0
T115	0	137	0	0
T167	0	31	0	0
T168	0	27	0	0
T169	0	34	0	0
T170	0	77	0	0
T171	0	9	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3857	0	0
T4	24905	37	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	47	0	0
T101	0	22	0	0
T114	0	120	0	0
T115	0	114	0	0
T167	0	34	0	0
T168	0	42	0	0
T169	0	21	0	0
T170	0	55	0	0
T171	0	5	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3827	0	0
T4	24905	14	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	20	0	0
T101	0	21	0	0
T114	0	105	0	0
T115	0	105	0	0
T120	0	22	0	0
T167	0	28	0	0
T168	0	33	0	0
T169	0	17	0	0
T170	0	48	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3834	0	0
T4	24905	1	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	51	0	0
T101	0	11	0	0
T114	0	118	0	0
T115	0	106	0	0
T167	0	19	0	0
T168	0	46	0	0
T169	0	23	0	0
T170	0	77	0	0
T171	0	2	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3895	0	0
T4	24905	13	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	49	0	0
T101	0	30	0	0
T114	0	97	0	0
T115	0	99	0	0
T120	0	26	0	0
T167	0	35	0	0
T168	0	31	0	0
T169	0	21	0	0
T170	0	63	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3764	0	0
T4	24905	14	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	32	0	0
T101	0	22	0	0
T114	0	140	0	0
T115	0	81	0	0
T120	0	33	0	0
T167	0	30	0	0
T168	0	19	0	0
T169	0	14	0	0
T170	0	71	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3922	0	0
T4	24905	1	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	34	0	0
T101	0	27	0	0
T114	0	155	0	0
T115	0	147	0	0
T167	0	34	0	0
T168	0	17	0	0
T169	0	27	0	0
T170	0	54	0	0
T171	0	10	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3811	0	0
T60	0	42	0	0
T75	15080	0	0	0
T88	13217	0	0	0
T99	16255	0	0	0
T100	10057	0	0	0
T101	15680	25	0	0
T114	0	137	0	0
T115	0	105	0	0
T120	0	32	0	0
T167	0	22	0	0
T168	0	18	0	0
T169	0	25	0	0
T170	0	78	0	0
T171	0	5	0	0
T178	12872	0	0	0
T179	34009	0	0	0
T180	19661	0	0	0
T181	14769	0	0	0
T182	9925	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3724	0	0
T4	24905	22	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	35	0	0
T101	0	13	0	0
T114	0	94	0	0
T115	0	104	0	0
T167	0	25	0	0
T168	0	33	0	0
T169	0	21	0	0
T170	0	41	0	0
T171	0	2	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3987	0	0
T4	24905	20	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	30	0	0
T101	0	15	0	0
T114	0	109	0	0
T115	0	92	0	0
T167	0	24	0	0
T168	0	28	0	0
T169	0	31	0	0
T170	0	57	0	0
T171	0	6	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3763	0	0
T4	24905	11	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	32	0	0
T101	0	20	0	0
T114	0	128	0	0
T115	0	102	0	0
T167	0	20	0	0
T168	0	27	0	0
T169	0	27	0	0
T170	0	49	0	0
T171	0	5	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3813	0	0
T4	24905	21	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	28	0	0
T101	0	23	0	0
T114	0	116	0	0
T115	0	93	0	0
T167	0	39	0	0
T168	0	13	0	0
T169	0	20	0	0
T170	0	78	0	0
T171	0	5	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3845	0	0
T4	24905	18	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	20	0	0
T101	0	22	0	0
T114	0	140	0	0
T115	0	105	0	0
T120	0	23	0	0
T167	0	54	0	0
T168	0	28	0	0
T169	0	21	0	0
T170	0	65	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3795	0	0
T4	24905	7	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	21	0	0
T101	0	24	0	0
T114	0	103	0	0
T115	0	96	0	0
T167	0	29	0	0
T168	0	28	0	0
T169	0	21	0	0
T170	0	67	0	0
T171	0	1	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3940	0	0
T4	24905	11	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	8	0	0
T101	0	19	0	0
T114	0	180	0	0
T115	0	105	0	0
T167	0	39	0	0
T168	0	30	0	0
T169	0	31	0	0
T170	0	94	0	0
T171	0	2	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3691	0	0
T4	24905	11	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	37	0	0
T101	0	28	0	0
T114	0	87	0	0
T115	0	93	0	0
T167	0	14	0	0
T168	0	34	0	0
T169	0	35	0	0
T170	0	80	0	0
T171	0	3	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3869	0	0
T4	24905	19	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	18	0	0
T101	0	28	0	0
T114	0	116	0	0
T115	0	99	0	0
T167	0	33	0	0
T168	0	45	0	0
T169	0	22	0	0
T170	0	48	0	0
T171	0	5	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3711	0	0
T4	24905	19	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	28	0	0
T101	0	34	0	0
T114	0	132	0	0
T115	0	80	0	0
T167	0	22	0	0
T168	0	19	0	0
T169	0	16	0	0
T170	0	36	0	0
T171	0	2	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3870	0	0
T4	24905	18	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	40	0	0
T101	0	24	0	0
T114	0	140	0	0
T115	0	117	0	0
T167	0	20	0	0
T168	0	13	0	0
T169	0	26	0	0
T170	0	64	0	0
T171	0	2	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3741	0	0
T4	24905	19	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	40	0	0
T101	0	25	0	0
T114	0	117	0	0
T115	0	125	0	0
T167	0	26	0	0
T168	0	14	0	0
T169	0	25	0	0
T170	0	63	0	0
T171	0	5	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3812	0	0
T4	24905	6	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	32	0	0
T101	0	29	0	0
T114	0	107	0	0
T115	0	122	0	0
T167	0	26	0	0
T168	0	17	0	0
T169	0	15	0	0
T170	0	57	0	0
T171	0	2	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32829498	3786	0	0
T4	24905	15	0	0
T5	2149	0	0	0
T15	5634	0	0	0
T16	27103	0	0	0
T17	7837	0	0	0
T18	20738	0	0	0
T19	4035	0	0	0
T41	5883	0	0	0
T43	6720	0	0	0
T47	2720	0	0	0
T60	0	25	0	0
T101	0	19	0	0
T114	0	155	0	0
T115	0	86	0	0
T167	0	26	0	0
T168	0	35	0	0
T169	0	28	0	0
T170	0	50	0	0
T171	0	1	0	0