b938dde05c
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 47.360s | 3.178ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.605m | 5.491ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.610s | 42.861us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 32.010s | 1.335ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 16.550s | 449.739us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.220s | 51.942us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 16.550s | 449.739us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.129m | 4.816ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 1.355m | 21.721ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 57.780s | 1.985ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 50.360s | 9.452ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.354m | 7.916ms | 49 | 50 | 98.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 55.340s | 5.318ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 23.390s | 1.590ms | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 1.960m | 23.784ms | 46 | 50 | 92.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.715m | 5.546ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 58.530s | 20.172ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 31.530s | 5.254ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 6.413m | 150.488ms | 47 | 50 | 94.00 |
V2 | intr_test | keymgr_intr_test | 0.940s | 26.036us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.040s | 21.590us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.210s | 545.071us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.210s | 545.071us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.610s | 42.861us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 16.550s | 449.739us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.130s | 271.513us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.610s | 42.861us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 16.550s | 449.739us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.130s | 271.513us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 731 | 740 | 98.78 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 1.320m | 11.390ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 24.890s | 1.144ms | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 24.890s | 1.144ms | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 24.890s | 1.144ms | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 24.890s | 1.144ms | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.970s | 1.069ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 1.320m | 11.390ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 24.890s | 1.144ms | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.129m | 4.816ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.605m | 5.491ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.605m | 5.491ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.605m | 5.491ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.550s | 34.062us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 23.390s | 1.590ms | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 58.530s | 20.172ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 58.530s | 20.172ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.605m | 5.491ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 19.000s | 697.411us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 1.111m | 1.524ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 23.390s | 1.590ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 1.111m | 1.524ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 1.111m | 1.524ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 1.111m | 1.524ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 1.979m | 42.885ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 1.111m | 1.524ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 23.830s | 1.153ms | 20 | 50 | 40.00 |
V3 | TOTAL | 20 | 50 | 40.00 | |||
TOTAL | 1071 | 1110 | 96.49 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.80 | 99.07 | 98.03 | 98.29 | 100.00 | 99.19 | 98.41 | 91.61 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 20 failures:
4.keymgr_stress_all_with_rand_reset.52970708195128263271675658660730346293928640272238205515286409480305812848552
Line 333, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 428919699 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 428919699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_stress_all_with_rand_reset.2574376465733673891327729566824265125761218369990843425213250231974457472863
Line 679, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 465711838 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 465711838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * [])` has 9 failures:
0.keymgr_stress_all_with_rand_reset.14233024233715966446484818545514007462166302891809975135720637375351086431175
Line 868, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 192178987 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2848689332 [0xa9cb8cb4] vs 2848689332 [0xa9cb8cb4])
UVM_INFO @ 192178987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_stress_all_with_rand_reset.111042657770305856425105182649256984711686038079794432473435978946459148471768
Line 1586, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 437018963 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (416505121 [0x18d35d21] vs 416505121 [0x18d35d21])
UVM_INFO @ 437018963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation
has 4 failures:
35.keymgr_kmac_rsp_err.93493360286811322078991020083310634415021175870003043222856259531774740476615
Line 474, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 873117170 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (190086239154150923414000405996253091356790814153373338070908976992925511112043876315434230937378102049401256413991157550921628084538904574880504505531562573799916483412555669762823313993910646117665773759467702520204100842912155770295585069849878089655551237956349657767007216938082269236770953012384718930198354884350126003453138999959609390610214667429101159236126318811506801601011229110016136290753066167536741389006379 [0x6deb8550295f848ce333cd154d73797e28e64ee16d7613ecd63b2c89f3ad11f3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9ea1044a1127d6e08031ef3f04661911ba1db55700ff8460855fd336372f1bb23ff71d39bf9d32bd8b74d2aa95582df01fe3d2082d19a571171213c7427bf2bdeabe6fea53e0899ec10082e577c29a240c8ef0b0f9ce9149ebfa066534b7cac969dc59fdd2ba435bc3fb79a67f3b9762b] vs 190086239154150923414000405996253091356790814153373338070908976992925511112043876315434230937378102049401256413991157550921628084538904574880504505531562573799916483412555669762823313993910646117665773759467702520204100842912155770295585069849878089655551237956349657767007216938082269236770953012384718930198354884350126003453138999959609390610214667429101159236126318811506801601011229110016136290753066167536741389006379 [0x6deb8550295f848ce333cd154d73797e28e64ee16d7613ecd63b2c89f3ad11f3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9ea1044a1127d6e08031ef3f04661911ba1db55700ff8460855fd336372f1bb23ff71d39bf9d32bd8b74d2aa95582df01fe3d2082d19a571171213c7427bf2bdeabe6fea53e0899ec10082e577c29a240c8ef0b0f9ce9149ebfa066534b7cac969dc59fdd2ba435bc3fb79a67f3b9762b]) cdi_type: Attestation
DiversificationKey act: 0xc8ef0b0f9ce9149ebfa066534b7cac969dc59fdd2ba435bc3fb79a67f3b9762b, exp: 0xc8ef0b0f9ce9149ebfa066534b7cac969dc59fdd2ba435bc3fb79a67f3b9762b
RomDigest act: 0xfe3d2082d19a571171213c7427bf2bdeabe6fea53e0899ec10082e577c29a240, exp: 0xfe3d2082d19a571171213c7427bf2bdeabe6fea53e0899ec10082e577c29a240
HealthMeasurement act: 0xff71d39bf9d32bd8b74d2aa95582df01, exp: 0xff71d39bf9d32bd8b74d2aa95582df01
39.keymgr_kmac_rsp_err.92277116703065392687792475575562781296491225938384987855171962784712171978553
Line 532, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 46422105 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (13869088684237589750254652523805745455607483863801036890679746459828093165537926833747970447116820082634456235668781941977824857650589025322626962015971041384160955579574016139073596605122669855472233498398516896072534741860126662951059811034861976749879406955630023967880178055678851009446828175930912961301631380610225535879338731481008030269530 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9928a02c477cd12c78e077e29265420b6f41daa93763fe529db8b65ac58c3c52296bd5cee1cfc1a5a670daa18e320a261983b4ef809979ee44a59ebf4a3399b771303acfc1234af5c9795ba59fcb9b1ead4bd5ca44a1b036f09975bf48dd3b18443649fecc5a5e648e1f54fcc33fec05a] vs 13869088684237589750254652523805745455607483863801036890679746459828093165537926833747970447116820082634456235668781941977824857650589025322626962015971041384160955579574016139073596605122669855472233498398516896072534741860126662951059811034861976749879406955630023967880178055678851009446828175930912961301631380610225535879338731481008030269530 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9928a02c477cd12c78e077e29265420b6f41daa93763fe529db8b65ac58c3c52296bd5cee1cfc1a5a670daa18e320a261983b4ef809979ee44a59ebf4a3399b771303acfc1234af5c9795ba59fcb9b1ead4bd5ca44a1b036f09975bf48dd3b18443649fecc5a5e648e1f54fcc33fec05a]) cdi_type: Attestation
DiversificationKey act: 0xd4bd5ca44a1b036f09975bf48dd3b18443649fecc5a5e648e1f54fcc33fec05a, exp: 0xd4bd5ca44a1b036f09975bf48dd3b18443649fecc5a5e648e1f54fcc33fec05a
RomDigest act: 0x983b4ef809979ee44a59ebf4a3399b771303acfc1234af5c9795ba59fcb9b1ea, exp: 0x983b4ef809979ee44a59ebf4a3399b771303acfc1234af5c9795ba59fcb9b1ea
HealthMeasurement act: 0x96bd5cee1cfc1a5a670daa18e320a261, exp: 0x96bd5cee1cfc1a5a670daa18e320a261
... and 2 more failures.
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 3 failures:
15.keymgr_stress_all.17614695059597077322346286902179558723784074810419546142999393070901765286183
Line 2138, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log
UVM_ERROR @ 5925371889 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (3276666542 [0xc34df6ae] vs 1528708649 [0x5b1e3e29]) reg name: keymgr_reg_block.sw_share1_output_5
UVM_INFO @ 5925371889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.keymgr_stress_all.108252650029280297067077417071599640895444712629567143957616660680643512086267
Line 3763, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all/latest/run.log
UVM_ERROR @ 964785128 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2825146820 [0xa86451c4] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
UVM_INFO @ 964785128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_sideload_otbn has 1 failures.
20.keymgr_sideload_otbn.17881503273293569426415569238727368192279563120877605726237047226439162736592
Line 291, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest/run.log
UVM_ERROR @ 7802193 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 7802193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
37.keymgr_stress_all_with_rand_reset.71518771595940685875069634455794322683287324507880044139089592654667124749614
Line 799, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51467694 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 51467694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
49.keymgr_cfg_regwen.103352235185325393262789880859198901515721911692114886288598085552635782122617
Line 278, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 9741642 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 9741642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---