SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 880 | 1 | T23 | 70 | T25 | 30 | T26 | 20 | ||||
auto[OtpRootKeyValidLow] | 191 | 1 | T23 | 7 | T25 | 7 | T26 | 7 | ||||
auto[LcStateInvalid] | 72 | 1 | T346 | 36 | T412 | 36 | - | - | ||||
auto[OtpDevIdInvalid] | 108 | 1 | T317 | 12 | T259 | 36 | T413 | 24 | ||||
auto[RomDigestInvalid] | 216 | 1 | T78 | 12 | T259 | 48 | T302 | 24 | ||||
auto[RomDigestValidLow] | 24 | 1 | T414 | 12 | T412 | 12 | - | - | ||||
auto[FlashCreatorSeedInvalid] | 36 | 1 | T24 | 24 | T414 | 12 | - | - | ||||
auto[FlashOwnerSeedInvalid] | 108 | 1 | T78 | 24 | T79 | 12 | T81 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |