Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4576

1

T2

5

T3

1

T4

5

auto[1]

540

1

T3

3

T14

5

T17

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4576

1

T2

5

T3

1

T4

5

auto[1]

540

1

T3

3

T14

5

T17

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4545

1

T2

4

T3

4

T4

5

auto[1]

571

1

T2

1

T18

1

T5

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4545

1

T2

4

T3

4

T4

5

auto[1]

571

1

T2

1

T18

1

T5

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T2	1		T3	1		T4	2
auto[OpGenId]	1075	1			T2	3		T3	2		T4	3
auto[OpGenSwOut]	1089	1			T3	1		T17	7		T8	1
auto[OpGenHwOut]	2469	1			T2	1		T14	8		T15	13
auto[OpDisable]	67	1			T5	1		T41	2		T45	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T2	1		T3	1		T4	2
auto[OpGenId]	1075	1			T2	3		T3	2		T4	3
auto[OpGenSwOut]	1089	1			T3	1		T17	7		T8	1
auto[OpGenHwOut]	2469	1			T2	1		T14	8		T15	13
auto[OpDisable]	67	1			T5	1		T41	2		T45	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4577

1

T2

5

T3

4

T4

5

auto[1]

539

1

T15

5

T17

5

T5

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4577

1

T2

5

T3

4

T4

5

auto[1]

539

1

T15

5

T17

5

T5

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4857

1

T2

5

T3

4

T4

5

auto[1]

259

1

T17

13

T93

4

T109

6

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1770	1			T2	2		T3	4		T4	2
auto[1]	642	1			T4	1		T14	1		T15	2
auto[2]	661	1			T14	3		T15	1		T17	8
auto[3]	705	1			T2	1		T4	1		T15	3
auto[4]	316	1			T18	1		T5	1		T72	1
auto[5]	343	1			T5	2		T70	2		T218	1
auto[6]	325	1			T2	1		T15	2		T5	3
auto[7]	354	1			T2	1		T4	1		T14	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1338	1			T2	2		T4	1		T14	1
clear_one[1]	642	1			T4	1		T14	1		T15	2
clear_one[2]	661	1			T14	3		T15	1		T17	8
clear_one[3]	705	1			T2	1		T4	1		T15	3
clear_none	1770	1			T2	2		T3	4		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	906	1			T15	5		T18	2		T8	1
auto[StInit]	786	1			T2	1		T3	1		T14	1
auto[StCreatorRootKey]	557	1			T2	1		T14	1		T15	1
auto[StOwnerIntKey]	453	1			T2	1		T14	1		T15	1
auto[StOwnerKey]	451	1			T2	1		T3	1		T14	1
auto[StDisabled]	1803	1			T2	1		T3	2		T14	4
auto[StInvalid]	160	1			T4	5		T34	3		T38	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	906	1			T15	5		T18	2		T8	1
auto[StInit]	786	1			T2	1		T3	1		T14	1
auto[StCreatorRootKey]	557	1			T2	1		T14	1		T15	1
auto[StOwnerIntKey]	453	1			T2	1		T14	1		T15	1
auto[StOwnerKey]	451	1			T2	1		T3	1		T14	1
auto[StDisabled]	1803	1			T2	1		T3	2		T14	4
auto[StInvalid]	160	1			T4	5		T34	3		T38	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	6
[auto[2] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	6
[auto[2] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	24
[auto[2] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	6

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T244	1		T245	1		T246	1
auto[0]	auto[StReset]	auto[OpGenId]	136	1			T5	3		T75	1		T211	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	136	1			T8	1		T5	1		T24	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	259	1			T15	2		T18	1		T5	1
auto[0]	auto[StInit]	auto[OpAdvance]	47	1			T5	1		T93	1		T41	1
auto[0]	auto[StInit]	auto[OpGenId]	113	1			T2	1		T3	1		T17	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	102	1			T27	1		T90	1		T7	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	193	1			T14	1		T15	1		T23	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T2	1		T18	1		T45	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	49	1			T24	1		T213	1		T41	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	49	1			T41	1		T7	1		T198	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	69	1			T14	1		T72	1		T222	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T42	1		T247	1		T198	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	24	1			T5	1		T45	1		T248	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T70	1		T58	1		T44	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T18	1		T218	1		T41	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T3	1		T41	1		T7	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T93	1		T41	1		T57	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	24	1			T42	1		T58	1		T199	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T41	1		T204	1		T249	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	20	1			T90	1		T93	1		T95	1
auto[0]	auto[StDisabled]	auto[OpGenId]	64	1			T3	1		T93	1		T41	4
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T3	1		T213	1		T207	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	172	1			T14	1		T15	2		T72	1
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T127	1		T98	1		T132	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	5	1			T4	2		T216	1		T250	1
auto[0]	auto[StInvalid]	auto[OpGenId]	8	1			T38	1		T251	1		T252	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T253	1		T254	1		T255	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T34	1		T59	1		T256	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T257	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T5	1		T49	1		T42	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T5	1		T42	1		T43	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	34	1			T72	1		T45	1		T258	2
auto[1]	auto[StInit]	auto[OpAdvance]	11	1			T24	1		T144	1		T259	1
auto[1]	auto[StInit]	auto[OpGenId]	18	1			T41	1		T25	1		T26	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	22	1			T24	1		T41	1		T260	2
auto[1]	auto[StInit]	auto[OpGenHwOut]	18	1			T261	1		T199	1		T98	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T51	1		T57	1		T260	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	25	1			T41	1		T95	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T45	1		T58	1		T260	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T205	1		T249	1		T263	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T63	1		T264	1		T265	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T43	1		T63	1		T266	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T267	1		T43	1		T268	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T14	1		T15	1		T222	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T45	1		T269	2		T64	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	9	1			T41	1		T270	1		T271	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T212	1		T83	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T203	1		T273	1		T42	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	30	1			T70	1		T58	1		T43	1
auto[1]	auto[StDisabled]	auto[OpGenId]	41	1			T90	2		T57	1		T45	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T213	1		T90	1		T41	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	125	1			T15	1		T218	2		T273	2
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T41	1		T43	1		T274	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T49	1		T59	1		T275	2
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T4	1		T38	1		T122	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T256	1		T276	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T214	1		T220	1		T278	1
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T57	1		T279	1		T26	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	13	1			T51	1		T280	1		T199	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	38	1			T5	1		T72	1		T219	2
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T23	1		T142	1		T77	1
auto[2]	auto[StInit]	auto[OpGenId]	18	1			T23	1		T5	1		T24	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	17	1			T9	1		T262	1		T29	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	35	1			T211	1		T41	1		T26	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T281	1		T282	1		T283	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T284	1		T285	1		T44	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T258	1		T43	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T219	1		T273	1		T221	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T57	1		T142	2		T286	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T287	1		T288	1		T289	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T258	1		T290	1		T199	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T5	1		T273	1		T291	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T292	1		T293	1		T294	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	9	1			T7	1		T280	2		T295	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T57	1		T43	1		T44	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T14	1		T219	1		T205	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	22	1			T17	1		T42	1		T296	1
auto[2]	auto[StDisabled]	auto[OpGenId]	43	1			T18	1		T5	1		T41	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T17	4		T211	1		T41	3
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T14	2		T15	1		T17	3
auto[2]	auto[StDisabled]	auto[OpDisable]	5	1			T69	1		T297	1		T298	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T38	1		T214	1		T256	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T299	1		T300	1		T256	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T215	1		T254	1		T301	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T34	1		T278	1		T255	1
auto[3]	auto[StReset]	auto[OpGenId]	13	1			T41	1		T226	1		T285	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	11	1			T42	1		T258	1		T220	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	52	1			T15	2		T219	1		T95	1
auto[3]	auto[StInit]	auto[OpAdvance]	11	1			T212	1		T26	1		T216	1
auto[3]	auto[StInit]	auto[OpGenId]	16	1			T25	1		T26	1		T302	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T26	1		T126	1		T303	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	21	1			T8	1		T249	1		T304	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T305	1		T306	1		T216	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T58	2		T78	1		T307	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T5	2		T198	1		T141	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T15	1		T218	1		T41	2
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T17	1		T7	1		T281	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T45	1		T58	1		T141	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T141	1		T308	1		T295	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T249	1		T223	1		T263	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T309	1		T99	1		T310	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T5	1		T58	1		T81	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T79	1		T239	1		T311	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T2	1		T17	1		T5	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	28	1			T207	1		T109	2		T44	1
auto[3]	auto[StDisabled]	auto[OpGenId]	60	1			T17	1		T213	1		T41	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T17	2		T41	2		T95	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	172	1			T18	1		T5	1		T219	2
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T5	1		T281	1		T64	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T122	1		T220	1		T254	1
auto[3]	auto[StInvalid]	auto[OpGenId]	8	1			T4	1		T49	1		T122	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T216	1		T275	1		T312	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T49	1		T275	1		T313	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T49	1		T42	1		T7	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T41	1		T214	1		T58	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	18	1			T18	1		T29	1		T62	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T314	1		T315	1		T316	1
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T43	1		T36	1		T76	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	8	1			T317	1		T318	1		T319	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T205	1		T25	1		T44	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T320	1		T321	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T198	1		T323	1		T324	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T58	1		T325	1		T326	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T58	1		T327	1		T328	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T7	1		T83	1		T329	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T45	1		T58	1		T65	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T5	1		T36	1		T330	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T219	1		T205	1		T225	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T331	1		T298	1		T332	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T333	1		T317	1		T236	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T45	1		T333	1		T308	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T42	1		T334	1		T335	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T306	1		T281	1		T336	2
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T41	1		T42	1		T7	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	17	1			T213	1		T45	1		T58	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	58	1			T72	1		T204	1		T42	2
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T45	1		T198	1		T199	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T255	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T300	1		T256	1		T313	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T220	1		T337	2		T338	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T216	1		T251	1		T337	1
auto[5]	auto[StReset]	auto[OpGenId]	5	1			T26	1		T43	1		T98	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	13	1			T211	1		T339	1		T340	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T57	1		T44	1		T341	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T25	1		T282	1		T191	1
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T84	1		T132	1		T281	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T342	1		T343	1		T344	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	18	1			T32	1		T124	1		T345	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T346	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T19	1		T58	1		T280	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T140	1		T347	1		T348	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T41	1		T349	2		T261	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T140	1		T350	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T351	1		T30	1		T230	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T41	1		T352	1		T353	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T92	1		T203	1		T280	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T93	1		T7	1		T63	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T230	1		T354	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T70	1		T43	1		T356	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T218	1		T222	1		T357	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T5	1		T7	1		T267	1
auto[5]	auto[StDisabled]	auto[OpGenId]	39	1			T70	1		T45	2		T248	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T41	1		T7	2		T212	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T5	1		T222	1		T93	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T66	1		T358	1		T344	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T253	1		T359	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T59	1		T122	1		T360	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T361	1		T277	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T253	1		T362	1		T360	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T56	1		T315	1		T323	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	9	1			T5	1		T41	1		T349	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T15	1		T7	1		T212	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T363	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T45	1		T302	1		T364	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T365	1		T314	1		T366	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T279	1		T289	1		T199	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T316	1		T367	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T41	1		T58	1		T368	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T27	1		T42	1		T126	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T369	1		T370	1		T371	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T109	1		T307	1		T372	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T2	1		T41	1		T262	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T5	1		T24	1		T44	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T72	1		T124	1		T373	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T374	1		T375	1		T372	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T85	1		T376	1		T281	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T58	1		T99	1		T281	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T15	1		T45	1		T44	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	9	1			T41	1		T95	1		T109	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T7	1		T43	1		T44	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T5	1		T7	1		T45	2
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T222	1		T273	1		T221	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T270	1		T377	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T378	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T34	1		T275	1		T363	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T214	1		T216	1		T313	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T38	1		T220	1		T255	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T258	1		T379	1		T63	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	16	1			T5	1		T49	1		T214	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	18	1			T5	1		T304	1		T198	1
auto[7]	auto[StInit]	auto[OpAdvance]	8	1			T17	1		T259	2		T281	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T83	1		T380	1		T381	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T293	1		T382	1		T64	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	17	1			T25	1		T334	1		T383	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T349	1		T293	1		T384	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T5	1		T65	1		T385	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T17	1		T58	1		T386	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T17	1		T92	1		T223	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T260	1		T244	1		T202	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T244	1		T63	1		T283	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T387	1		T388	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T213	1		T221	1		T357	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T303	1		T257	1		T298	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T43	1		T389	1		T390	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T199	1		T63	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T72	1		T92	1		T304	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	7	1			T45	1		T392	1		T393	1
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T2	1		T41	1		T58	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T58	1		T284	1		T43	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T14	1		T218	1		T222	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T41	1		T394	1		T395	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T59	1		T361	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T4	1		T49	1		T253	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T252	1		T396	1		T363	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T300	1		T397	1		T250	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1338

1

T2

2

T4

1

T14

1

clear_one[1]

auto[0]

auto[0]

auto[0]

390

1

T4

1

T14

1

T5

2

clear_one[1]

auto[0]

auto[0]

auto[1]

88

1

T15

2

T109

1

T58

1

clear_one[1]

auto[0]

auto[1]

auto[0]

118

1

T218

2

T222

1

T90

3

clear_one[1]

auto[0]

auto[1]

auto[1]

46

1

T70

1

T41

1

T57

1

clear_one[2]

auto[0]

auto[0]

auto[0]

372

1

T17

3

T23

2

T5

3

clear_one[2]

auto[0]

auto[0]

auto[1]

129

1

T15

1

T17

4

T219

2

clear_one[2]

auto[1]

auto[0]

auto[0]

119

1

T14

3

T18

1

T41

1

clear_one[2]

auto[1]

auto[0]

auto[1]

41

1

T17

1

T5

1

T54

1

clear_one[3]

auto[0]

auto[0]

auto[0]

404

1

T4

1

T15

3

T17

5

clear_one[3]

auto[0]

auto[1]

auto[0]

132

1

T2

1

T5

1

T218

1

clear_one[3]

auto[1]

auto[0]

auto[0]

131

1

T207

1

T357

3

T58

3

clear_one[3]

auto[1]

auto[1]

auto[0]

38

1

T18

1

T90

1

T57

1

clear_none

auto[0]

auto[0]

auto[0]

1240

1

T2

2

T3

1

T4

2

clear_none

auto[0]

auto[0]

auto[1]

140

1

T15

2

T70

1

T219

2

clear_none

auto[0]

auto[1]

auto[0]

146

1

T72

2

T218

1

T222

1

clear_none

auto[0]

auto[1]

auto[1]

33

1

T93

2

T41

1

T57

1

clear_none

auto[1]

auto[0]

auto[0]

117

1

T3

3

T14

2

T18

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T7

1

T109

2

T123

1

clear_none

auto[1]

auto[1]

auto[0]

32

1

T42

1

T398

2

T99

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T44

1

T399

4

T400

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1273	1			T2	2		T4	1		T14	1
clear_all	auto[1]	65	1			T17	2		T93	1		T140	8
clear_one[1]	auto[0]	594	1			T4	1		T14	1		T15	2
clear_one[1]	auto[1]	48	1			T109	1		T126	1		T260	5
clear_one[2]	auto[0]	629	1			T14	3		T15	1		T17	1
clear_one[2]	auto[1]	32	1			T17	7		T142	5		T368	1
clear_one[3]	auto[0]	660	1			T2	1		T4	1		T15	3
clear_one[3]	auto[1]	45	1			T17	4		T109	3		T305	2
clear_none	auto[0]	1701	1			T2	2		T3	4		T4	2
clear_none	auto[1]	69	1			T93	3		T109	2		T140	2