Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11095

1

T1

8

T2

10

T3

12

auto[Attestation]

8022

1

T1

3

T2

6

T3

11

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2831	1			T1	3		T2	2		T3	6
auto[Aes]	3392	1			T1	1		T2	2		T3	5
auto[Kmac]	3500	1			T1	1		T2	3		T3	4
auto[Otbn]	3416	1			T2	1		T3	4		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7886	1			T1	8		T2	8		T3	8
auto[OpGenId]	5978	1			T1	6		T2	8		T3	4
auto[OpGenSwOut]	6081	1			T1	5		T2	4		T3	12
auto[OpGenHwOut]	7058	1			T2	4		T3	7		T4	6
auto[OpDisable]	149	1			T5	1		T41	4		T42	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10238

1

T1

8

T2

10

T3

12

auto[OpDoneFail]

16914

1

T1

11

T2

14

T3

19

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6087	1			T1	4		T2	1		T3	2
auto[StInit]	4443	1			T1	2		T2	4		T3	6
auto[StCreatorRootKey]	3045	1			T1	2		T2	1		T3	5
auto[StOwnerIntKey]	2729	1			T1	2		T2	4		T3	4
auto[StOwnerKey]	2315	1			T1	2		T2	3		T3	1
auto[StDisabled]	7575	1			T1	7		T2	11		T3	13
auto[StInvalid]	958	1			T4	21		T34	35		T38	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	274	1			T1	1		T18	2		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	118	1			T24	1		T210	1		T88	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T3	1		T5	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	82	1			T18	1		T74	1		T211	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T5	1		T211	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	211	1			T1	1		T3	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	34	1			T4	1		T38	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	298	1			T5	5		T24	2		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	123	1			T8	1		T211	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	77	1			T17	2		T5	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	56	1			T1	1		T5	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	44	1			T41	1		T212	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	237	1			T2	2		T3	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T34	1		T49	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	339	1			T8	1		T23	1		T5	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	125	1			T23	1		T27	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	75	1			T27	1		T41	1		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	58	1			T3	1		T16	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T213	1		T42	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	211	1			T18	1		T5	2		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T38	2		T59	4		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	304	1			T8	1		T5	6		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	126	1			T3	2		T8	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T5	1		T73	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T2	1		T17	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T5	1		T70	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	200	1			T17	2		T5	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	23	1			T122	2		T215	2		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	77	1			T5	4		T41	5		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	111	1			T1	1		T16	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	89	1			T71	1		T50	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	83	1			T17	1		T5	3		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T2	1		T24	1		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	213	1			T3	1		T17	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T34	3		T38	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T5	3		T41	6		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	128	1			T18	1		T24	1		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	76	1			T5	1		T27	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T17	1		T5	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	47	1			T73	1		T211	1		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	209	1			T3	1		T18	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	31	1			T4	2		T34	1		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T5	1		T41	4		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	135	1			T18	1		T23	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	72	1			T3	2		T24	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T5	1		T41	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T1	1		T217	1		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	210	1			T3	1		T17	1		T73	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	24	1			T4	2		T34	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	76	1			T5	1		T49	2		T41	7
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T17	1		T18	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	71	1			T5	1		T48	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T3	1		T5	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T5	1		T210	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	219	1			T17	1		T5	2		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T4	1		T34	2		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	283	1			T18	1		T5	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	115	1			T3	1		T8	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T38	1		T211	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T33	1		T41	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	27	1			T5	1		T41	3		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	179	1			T2	1		T5	2		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T4	1		T38	2		T214	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	388	1			T3	1		T18	1		T8	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	133	1			T3	1		T4	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T39	1		T90	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	101	1			T14	1		T18	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	89	1			T33	1		T90	1		T42	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	246	1			T14	3		T5	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	24	1			T4	1		T34	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	476	1			T18	3		T8	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	145	1			T2	1		T39	1		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T39	2		T72	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T75	1		T218	1		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	84	1			T72	1		T92	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	262	1			T17	1		T5	2		T72	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	26	1			T34	1		T38	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	443	1			T15	13		T18	1		T8	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	121	1			T23	1		T75	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	124	1			T15	1		T17	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T15	1		T18	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	86	1			T17	2		T5	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	257	1			T15	4		T17	1		T219	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	19	1			T34	1		T38	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	52	1			T5	1		T49	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T4	1		T5	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	64	1			T39	1		T24	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T5	1		T213	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T17	1		T18	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	170	1			T3	2		T17	1		T18	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	37	1			T34	1		T59	2		T122	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T5	3		T49	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	154	1			T4	1		T14	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	97	1			T14	1		T93	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	119	1			T3	1		T18	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T14	1		T211	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	248	1			T14	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	31	1			T4	1		T34	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	56	1			T5	1		T49	1		T41	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	127	1			T24	1		T72	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T17	1		T39	2		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T5	1		T72	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	95	1			T2	1		T218	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	268	1			T2	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	26	1			T34	3		T122	2		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T49	1		T41	3		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	141	1			T15	1		T24	2		T33	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T39	1		T42	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T17	1		T5	2		T75	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T15	1		T17	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	273	1			T3	1		T17	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	27	1			T49	2		T59	2		T215	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	193	1			T3	1		T18	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	650	1			T1	2		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	167	1			T1	1		T17	2		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	703	1			T2	2		T3	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	171	1			T3	1		T16	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	720	1			T18	1		T8	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T2	1		T17	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	670	1			T3	2		T17	2		T8	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	218	1			T2	1		T17	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	452	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	177	1			T17	1		T5	2		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T3	1		T4	2		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	187	1			T1	1		T3	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	469	1			T3	1		T4	2		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T3	1		T5	3		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	470	1			T4	1		T17	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T5	1		T33	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	616	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	277	1			T14	1		T39	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	810	1			T3	2		T4	2		T14	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	255	1			T39	2		T72	2		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	926	1			T2	1		T17	1		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T15	2		T17	3		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	855	1			T15	17		T17	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	159	1			T17	1		T18	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	390	1			T3	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T3	1		T14	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	523	1			T4	2		T14	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T2	1		T17	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	485	1			T2	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	248	1			T15	1		T17	3		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	503	1			T3	1		T15	1		T17	1