Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31183

1

T1

23

T2

29

T3

34

auto[1]

266

1

T17

19

T93

5

T109

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31191	1			T1	23		T2	29		T3	34
auto[134217728:268435455]	13	1			T17	1		T140	1		T142	1
auto[268435456:402653183]	5	1			T305	1		T140	1		T349	1
auto[402653184:536870911]	8	1			T109	1		T140	1		T293	1
auto[536870912:671088639]	8	1			T93	1		T425	1		T345	1
auto[671088640:805306367]	9	1			T17	1		T109	1		T140	1
auto[805306368:939524095]	11	1			T17	1		T425	1		T293	1
auto[939524096:1073741823]	7	1			T93	1		T109	1		T368	1
auto[1073741824:1207959551]	9	1			T93	1		T140	1		T406	1
auto[1207959552:1342177279]	10	1			T17	1		T345	2		T407	1
auto[1342177280:1476395007]	14	1			T17	1		T140	1		T333	2
auto[1476395008:1610612735]	11	1			T93	1		T349	1		T386	1
auto[1610612736:1744830463]	7	1			T17	1		T109	1		T126	1
auto[1744830464:1879048191]	11	1			T17	2		T333	1		T349	1
auto[1879048192:2013265919]	8	1			T17	1		T140	1		T293	1
auto[2013265920:2147483647]	10	1			T17	1		T349	1		T405	1
auto[2147483648:2281701375]	6	1			T126	1		T349	1		T425	1
auto[2281701376:2415919103]	7	1			T17	1		T109	1		T333	1
auto[2415919104:2550136831]	9	1			T109	1		T140	2		T409	1
auto[2550136832:2684354559]	6	1			T17	1		T305	1		T407	1
auto[2684354560:2818572287]	6	1			T140	1		T260	1		T407	1
auto[2818572288:2952790015]	2	1			T368	1		T426	1		-	-
auto[2952790016:3087007743]	8	1			T17	1		T140	2		T386	1
auto[3087007744:3221225471]	5	1			T144	1		T425	1		T427	1
auto[3221225472:3355443199]	9	1			T17	1		T407	1		T406	1
auto[3355443200:3489660927]	9	1			T17	1		T109	1		T126	2
auto[3489660928:3623878655]	5	1			T17	1		T126	1		T409	1
auto[3623878656:3758096383]	7	1			T93	1		T144	1		T372	1
auto[3758096384:3892314111]	6	1			T333	1		T409	1		T269	1
auto[3892314112:4026531839]	17	1			T17	3		T126	1		T144	1
auto[4026531840:4160749567]	4	1			T368	1		T265	1		T428	1
auto[4160749568:4294967295]	11	1			T109	1		T140	1		T333	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31183	1			T1	23		T2	29		T3	34
auto[0:134217727]	auto[1]	8	1			T142	1		T260	1		T368	1
auto[134217728:268435455]	auto[1]	13	1			T17	1		T140	1		T142	1
auto[268435456:402653183]	auto[1]	5	1			T305	1		T140	1		T349	1
auto[402653184:536870911]	auto[1]	8	1			T109	1		T140	1		T293	1
auto[536870912:671088639]	auto[1]	8	1			T93	1		T425	1		T345	1
auto[671088640:805306367]	auto[1]	9	1			T17	1		T109	1		T140	1
auto[805306368:939524095]	auto[1]	11	1			T17	1		T425	1		T293	1
auto[939524096:1073741823]	auto[1]	7	1			T93	1		T109	1		T368	1
auto[1073741824:1207959551]	auto[1]	9	1			T93	1		T140	1		T406	1
auto[1207959552:1342177279]	auto[1]	10	1			T17	1		T345	2		T407	1
auto[1342177280:1476395007]	auto[1]	14	1			T17	1		T140	1		T333	2
auto[1476395008:1610612735]	auto[1]	11	1			T93	1		T349	1		T386	1
auto[1610612736:1744830463]	auto[1]	7	1			T17	1		T109	1		T126	1
auto[1744830464:1879048191]	auto[1]	11	1			T17	2		T333	1		T349	1
auto[1879048192:2013265919]	auto[1]	8	1			T17	1		T140	1		T293	1
auto[2013265920:2147483647]	auto[1]	10	1			T17	1		T349	1		T405	1
auto[2147483648:2281701375]	auto[1]	6	1			T126	1		T349	1		T425	1
auto[2281701376:2415919103]	auto[1]	7	1			T17	1		T109	1		T333	1
auto[2415919104:2550136831]	auto[1]	9	1			T109	1		T140	2		T409	1
auto[2550136832:2684354559]	auto[1]	6	1			T17	1		T305	1		T407	1
auto[2684354560:2818572287]	auto[1]	6	1			T140	1		T260	1		T407	1
auto[2818572288:2952790015]	auto[1]	2	1			T368	1		T426	1		-	-
auto[2952790016:3087007743]	auto[1]	8	1			T17	1		T140	2		T386	1
auto[3087007744:3221225471]	auto[1]	5	1			T144	1		T425	1		T427	1
auto[3221225472:3355443199]	auto[1]	9	1			T17	1		T407	1		T406	1
auto[3355443200:3489660927]	auto[1]	9	1			T17	1		T109	1		T126	2
auto[3489660928:3623878655]	auto[1]	5	1			T17	1		T126	1		T409	1
auto[3623878656:3758096383]	auto[1]	7	1			T93	1		T144	1		T372	1
auto[3758096384:3892314111]	auto[1]	6	1			T333	1		T409	1		T269	1
auto[3892314112:4026531839]	auto[1]	17	1			T17	3		T126	1		T144	1
auto[4026531840:4160749567]	auto[1]	4	1			T368	1		T265	1		T428	1
auto[4160749568:4294967295]	auto[1]	11	1			T109	1		T140	1		T333	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1521

1

T2

4

T4

4

T17

1

auto[1]

1683

1

T2

2

T3

4

T17

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T75	1		T34	1		T93	1
auto[134217728:268435455]	101	1			T18	2		T9	1		T49	1
auto[268435456:402653183]	108	1			T3	1		T42	1		T262	1
auto[402653184:536870911]	92	1			T5	1		T41	1		T7	5
auto[536870912:671088639]	83	1			T27	2		T41	3		T42	1
auto[671088640:805306367]	101	1			T18	1		T5	3		T211	1
auto[805306368:939524095]	89	1			T5	3		T34	1		T42	1
auto[939524096:1073741823]	90	1			T2	1		T5	2		T93	1
auto[1073741824:1207959551]	116	1			T2	2		T4	1		T5	1
auto[1207959552:1342177279]	96	1			T38	1		T211	1		T41	1
auto[1342177280:1476395007]	98	1			T3	1		T17	1		T18	1
auto[1476395008:1610612735]	87	1			T24	1		T28	1		T41	1
auto[1610612736:1744830463]	116	1			T4	1		T39	1		T70	1
auto[1744830464:1879048191]	88	1			T17	1		T8	1		T70	1
auto[1879048192:2013265919]	91	1			T2	1		T5	1		T34	2
auto[2013265920:2147483647]	108	1			T5	1		T24	1		T41	1
auto[2147483648:2281701375]	95	1			T4	1		T5	1		T93	1
auto[2281701376:2415919103]	102	1			T3	1		T18	1		T5	2
auto[2415919104:2550136831]	95	1			T4	1		T5	1		T27	1
auto[2550136832:2684354559]	106	1			T5	1		T35	1		T42	1
auto[2684354560:2818572287]	92	1			T9	1		T90	1		T41	2
auto[2818572288:2952790015]	106	1			T2	1		T8	1		T5	1
auto[2952790016:3087007743]	98	1			T23	1		T75	1		T41	1
auto[3087007744:3221225471]	120	1			T39	1		T23	1		T5	1
auto[3221225472:3355443199]	90	1			T5	1		T24	1		T9	1
auto[3355443200:3489660927]	110	1			T17	1		T5	3		T34	1
auto[3489660928:3623878655]	98	1			T70	1		T49	1		T207	1
auto[3623878656:3758096383]	123	1			T2	1		T17	1		T18	1
auto[3758096384:3892314111]	122	1			T24	1		T211	1		T49	2
auto[3892314112:4026531839]	103	1			T23	1		T5	2		T34	1
auto[4026531840:4160749567]	96	1			T38	1		T48	1		T49	1
auto[4160749568:4294967295]	79	1			T3	1		T23	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T34	1		T93	1		T41	2
auto[0:134217727]	auto[1]	57	1			T75	1		T41	1		T95	1
auto[134217728:268435455]	auto[0]	51	1			T41	1		T7	1		T45	2
auto[134217728:268435455]	auto[1]	50	1			T18	2		T9	1		T49	1
auto[268435456:402653183]	auto[0]	53	1			T42	1		T45	1		T279	1
auto[268435456:402653183]	auto[1]	55	1			T3	1		T262	1		T57	1
auto[402653184:536870911]	auto[0]	39	1			T7	2		T54	1		T44	1
auto[402653184:536870911]	auto[1]	53	1			T5	1		T41	1		T7	3
auto[536870912:671088639]	auto[0]	46	1			T27	1		T41	1		T59	1
auto[536870912:671088639]	auto[1]	37	1			T27	1		T41	2		T42	1
auto[671088640:805306367]	auto[0]	44	1			T18	1		T5	1		T41	3
auto[671088640:805306367]	auto[1]	57	1			T5	2		T211	1		T58	1
auto[805306368:939524095]	auto[0]	42	1			T5	1		T34	1		T42	1
auto[805306368:939524095]	auto[1]	47	1			T5	2		T57	1		T45	3
auto[939524096:1073741823]	auto[0]	44	1			T2	1		T5	2		T42	2
auto[939524096:1073741823]	auto[1]	46	1			T93	1		T7	2		T58	1
auto[1073741824:1207959551]	auto[0]	53	1			T2	2		T4	1		T45	1
auto[1073741824:1207959551]	auto[1]	63	1			T5	1		T49	1		T51	2
auto[1207959552:1342177279]	auto[0]	59	1			T38	1		T211	1		T7	2
auto[1207959552:1342177279]	auto[1]	37	1			T41	1		T95	1		T198	2
auto[1342177280:1476395007]	auto[0]	44	1			T17	1		T8	1		T5	1
auto[1342177280:1476395007]	auto[1]	54	1			T3	1		T18	1		T5	2
auto[1476395008:1610612735]	auto[0]	43	1			T24	1		T28	1		T42	1
auto[1476395008:1610612735]	auto[1]	44	1			T41	1		T43	2		T44	1
auto[1610612736:1744830463]	auto[0]	49	1			T4	1		T39	1		T70	1
auto[1610612736:1744830463]	auto[1]	67	1			T48	1		T41	2		T42	1
auto[1744830464:1879048191]	auto[0]	33	1			T8	1		T41	1		T95	1
auto[1744830464:1879048191]	auto[1]	55	1			T17	1		T70	1		T41	1
auto[1879048192:2013265919]	auto[0]	42	1			T2	1		T5	1		T41	2
auto[1879048192:2013265919]	auto[1]	49	1			T34	2		T58	3		T267	1
auto[2013265920:2147483647]	auto[0]	51	1			T5	1		T7	1		T59	1
auto[2013265920:2147483647]	auto[1]	57	1			T24	1		T41	1		T42	1
auto[2147483648:2281701375]	auto[0]	43	1			T4	1		T93	1		T41	1
auto[2147483648:2281701375]	auto[1]	52	1			T5	1		T42	1		T57	1
auto[2281701376:2415919103]	auto[0]	43	1			T38	1		T41	2		T214	1
auto[2281701376:2415919103]	auto[1]	59	1			T3	1		T18	1		T5	2
auto[2415919104:2550136831]	auto[0]	42	1			T4	1		T5	1		T49	1
auto[2415919104:2550136831]	auto[1]	53	1			T27	1		T41	1		T7	2
auto[2550136832:2684354559]	auto[0]	49	1			T42	1		T45	1		T26	1
auto[2550136832:2684354559]	auto[1]	57	1			T5	1		T35	1		T7	2
auto[2684354560:2818572287]	auto[0]	51	1			T41	1		T95	1		T7	1
auto[2684354560:2818572287]	auto[1]	41	1			T9	1		T90	1		T41	1
auto[2818572288:2952790015]	auto[0]	39	1			T90	1		T51	1		T45	1
auto[2818572288:2952790015]	auto[1]	67	1			T2	1		T8	1		T5	1
auto[2952790016:3087007743]	auto[0]	46	1			T58	1		T43	1		T288	1
auto[2952790016:3087007743]	auto[1]	52	1			T23	1		T75	1		T41	1
auto[3087007744:3221225471]	auto[0]	59	1			T39	1		T23	1		T5	1
auto[3087007744:3221225471]	auto[1]	61	1			T28	1		T41	2		T207	1
auto[3221225472:3355443199]	auto[0]	48	1			T24	1		T9	1		T41	2
auto[3221225472:3355443199]	auto[1]	42	1			T5	1		T93	1		T7	1
auto[3355443200:3489660927]	auto[0]	58	1			T5	1		T34	1		T51	1
auto[3355443200:3489660927]	auto[1]	52	1			T17	1		T5	2		T48	1
auto[3489660928:3623878655]	auto[0]	54	1			T49	1		T207	1		T7	1
auto[3489660928:3623878655]	auto[1]	44	1			T70	1		T7	1		T59	1
auto[3623878656:3758096383]	auto[0]	60	1			T23	1		T93	1		T41	1
auto[3623878656:3758096383]	auto[1]	63	1			T2	1		T17	1		T18	1
auto[3758096384:3892314111]	auto[0]	55	1			T24	1		T211	1		T49	1
auto[3758096384:3892314111]	auto[1]	67	1			T49	1		T41	1		T7	1
auto[3892314112:4026531839]	auto[0]	46	1			T23	1		T5	2		T34	1
auto[3892314112:4026531839]	auto[1]	57	1			T42	1		T7	2		T58	3
auto[4026531840:4160749567]	auto[0]	44	1			T48	1		T49	1		T41	1
auto[4026531840:4160749567]	auto[1]	52	1			T38	1		T207	1		T7	1
auto[4160749568:4294967295]	auto[0]	43	1			T23	1		T24	1		T7	1
auto[4160749568:4294967295]	auto[1]	36	1			T3	1		T48	1		T41	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1542

1

T2

4

T4

4

T17

2

auto[1]

1663

1

T2

2

T3

4

T17

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T2	1		T8	1		T5	4
auto[134217728:268435455]	93	1			T5	2		T211	1		T49	1
auto[268435456:402653183]	101	1			T4	1		T75	1		T49	1
auto[402653184:536870911]	106	1			T18	1		T93	1		T41	2
auto[536870912:671088639]	90	1			T2	1		T5	1		T48	2
auto[671088640:805306367]	98	1			T5	1		T38	1		T7	1
auto[805306368:939524095]	101	1			T17	1		T5	1		T24	1
auto[939524096:1073741823]	107	1			T3	1		T5	1		T38	1
auto[1073741824:1207959551]	126	1			T34	1		T49	1		T41	1
auto[1207959552:1342177279]	112	1			T23	1		T5	1		T24	1
auto[1342177280:1476395007]	110	1			T5	1		T49	1		T57	3
auto[1476395008:1610612735]	85	1			T41	1		T42	2		T7	1
auto[1610612736:1744830463]	93	1			T3	1		T17	1		T18	1
auto[1744830464:1879048191]	91	1			T4	1		T41	1		T7	2
auto[1879048192:2013265919]	101	1			T4	1		T39	1		T5	1
auto[2013265920:2147483647]	104	1			T3	1		T23	1		T5	1
auto[2147483648:2281701375]	106	1			T2	1		T39	1		T5	1
auto[2281701376:2415919103]	99	1			T5	1		T41	1		T45	1
auto[2415919104:2550136831]	106	1			T17	1		T18	1		T35	1
auto[2550136832:2684354559]	104	1			T5	2		T41	3		T42	1
auto[2684354560:2818572287]	98	1			T5	2		T24	1		T70	1
auto[2818572288:2952790015]	110	1			T8	1		T27	1		T35	1
auto[2952790016:3087007743]	94	1			T2	1		T23	2		T5	1
auto[3087007744:3221225471]	98	1			T2	1		T5	2		T34	1
auto[3221225472:3355443199]	109	1			T5	1		T34	1		T49	1
auto[3355443200:3489660927]	99	1			T211	1		T42	1		T7	1
auto[3489660928:3623878655]	107	1			T4	1		T23	1		T93	1
auto[3623878656:3758096383]	95	1			T3	1		T18	1		T5	1
auto[3758096384:3892314111]	87	1			T18	1		T5	2		T34	2
auto[3892314112:4026531839]	93	1			T8	1		T5	1		T211	2
auto[4026531840:4160749567]	88	1			T2	1		T18	1		T41	1
auto[4160749568:4294967295]	96	1			T17	1		T5	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T2	1		T5	1		T34	1
auto[0:134217727]	auto[1]	46	1			T8	1		T5	3		T70	1
auto[134217728:268435455]	auto[0]	38	1			T5	1		T49	1		T41	3
auto[134217728:268435455]	auto[1]	55	1			T5	1		T211	1		T42	1
auto[268435456:402653183]	auto[0]	58	1			T4	1		T41	2		T7	1
auto[268435456:402653183]	auto[1]	43	1			T75	1		T49	1		T41	1
auto[402653184:536870911]	auto[0]	49	1			T7	1		T56	1		T43	3
auto[402653184:536870911]	auto[1]	57	1			T18	1		T93	1		T41	2
auto[536870912:671088639]	auto[0]	43	1			T2	1		T5	1		T48	1
auto[536870912:671088639]	auto[1]	47	1			T48	1		T41	1		T42	1
auto[671088640:805306367]	auto[0]	40	1			T5	1		T38	1		T45	1
auto[671088640:805306367]	auto[1]	58	1			T7	1		T45	1		T58	2
auto[805306368:939524095]	auto[0]	56	1			T17	1		T24	1		T70	1
auto[805306368:939524095]	auto[1]	45	1			T5	1		T41	2		T207	1
auto[939524096:1073741823]	auto[0]	48	1			T41	1		T7	1		T45	1
auto[939524096:1073741823]	auto[1]	59	1			T3	1		T5	1		T38	1
auto[1073741824:1207959551]	auto[0]	57	1			T34	1		T49	1		T41	1
auto[1073741824:1207959551]	auto[1]	69	1			T7	2		T57	3		T45	3
auto[1207959552:1342177279]	auto[0]	59	1			T23	1		T24	1		T49	1
auto[1207959552:1342177279]	auto[1]	53	1			T5	1		T41	1		T207	1
auto[1342177280:1476395007]	auto[0]	52	1			T49	1		T57	2		T43	1
auto[1342177280:1476395007]	auto[1]	58	1			T5	1		T57	1		T45	1
auto[1476395008:1610612735]	auto[0]	38	1			T59	1		T43	1		T44	2
auto[1476395008:1610612735]	auto[1]	47	1			T41	1		T42	2		T7	1
auto[1610612736:1744830463]	auto[0]	43	1			T18	1		T28	1		T211	1
auto[1610612736:1744830463]	auto[1]	50	1			T3	1		T17	1		T24	1
auto[1744830464:1879048191]	auto[0]	44	1			T4	1		T41	1		T25	1
auto[1744830464:1879048191]	auto[1]	47	1			T7	2		T58	1		T44	2
auto[1879048192:2013265919]	auto[0]	51	1			T4	1		T39	1		T95	1
auto[1879048192:2013265919]	auto[1]	50	1			T5	1		T75	1		T7	1
auto[2013265920:2147483647]	auto[0]	47	1			T23	1		T5	1		T95	1
auto[2013265920:2147483647]	auto[1]	57	1			T3	1		T90	1		T93	1
auto[2147483648:2281701375]	auto[0]	54	1			T2	1		T39	1		T5	1
auto[2147483648:2281701375]	auto[1]	52	1			T41	1		T51	1		T43	2
auto[2281701376:2415919103]	auto[0]	42	1			T45	1		T214	1		T44	1
auto[2281701376:2415919103]	auto[1]	57	1			T5	1		T41	1		T58	1
auto[2415919104:2550136831]	auto[0]	56	1			T45	1		T279	1		T58	1
auto[2415919104:2550136831]	auto[1]	50	1			T17	1		T18	1		T35	1
auto[2550136832:2684354559]	auto[0]	52	1			T41	3		T42	1		T57	1
auto[2550136832:2684354559]	auto[1]	52	1			T5	2		T7	1		T57	1
auto[2684354560:2818572287]	auto[0]	49	1			T5	2		T24	1		T41	2
auto[2684354560:2818572287]	auto[1]	49	1			T70	1		T9	1		T41	1
auto[2818572288:2952790015]	auto[0]	45	1			T8	1		T38	1		T9	1
auto[2818572288:2952790015]	auto[1]	65	1			T27	1		T35	1		T41	1
auto[2952790016:3087007743]	auto[0]	48	1			T2	1		T23	1		T42	1
auto[2952790016:3087007743]	auto[1]	46	1			T23	1		T5	1		T27	1
auto[3087007744:3221225471]	auto[0]	46	1			T5	2		T27	1		T41	2
auto[3087007744:3221225471]	auto[1]	52	1			T2	1		T34	1		T41	2
auto[3221225472:3355443199]	auto[0]	57	1			T5	1		T34	1		T42	2
auto[3221225472:3355443199]	auto[1]	52	1			T49	1		T41	1		T58	2
auto[3355443200:3489660927]	auto[0]	47	1			T7	1		T45	1		T226	1
auto[3355443200:3489660927]	auto[1]	52	1			T211	1		T42	1		T58	1
auto[3489660928:3623878655]	auto[0]	47	1			T4	1		T23	1		T93	1
auto[3489660928:3623878655]	auto[1]	60	1			T41	1		T95	1		T207	1
auto[3623878656:3758096383]	auto[0]	44	1			T5	1		T41	1		T262	1
auto[3623878656:3758096383]	auto[1]	51	1			T3	1		T18	1		T9	1
auto[3758096384:3892314111]	auto[0]	48	1			T5	2		T34	1		T49	1
auto[3758096384:3892314111]	auto[1]	39	1			T18	1		T34	1		T212	1
auto[3892314112:4026531839]	auto[0]	44	1			T8	1		T5	1		T41	1
auto[3892314112:4026531839]	auto[1]	49	1			T211	2		T48	1		T41	1
auto[4026531840:4160749567]	auto[0]	34	1			T7	2		T43	2		T305	1
auto[4026531840:4160749567]	auto[1]	54	1			T2	1		T18	1		T41	1
auto[4160749568:4294967295]	auto[0]	54	1			T17	1		T27	1		T57	1
auto[4160749568:4294967295]	auto[1]	42	1			T5	1		T38	1		T95	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1552

1

T2

4

T4

4

T17

3

auto[1]

1653

1

T2

2

T3

4

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T18	1		T23	1		T5	1
auto[134217728:268435455]	110	1			T5	1		T41	1		T262	1
auto[268435456:402653183]	90	1			T5	1		T27	1		T41	2
auto[402653184:536870911]	113	1			T3	1		T70	1		T27	1
auto[536870912:671088639]	83	1			T2	1		T75	1		T34	1
auto[671088640:805306367]	96	1			T8	1		T5	2		T28	1
auto[805306368:939524095]	103	1			T5	3		T211	1		T49	1
auto[939524096:1073741823]	98	1			T5	1		T211	1		T41	3
auto[1073741824:1207959551]	94	1			T75	1		T34	1		T9	1
auto[1207959552:1342177279]	85	1			T5	1		T41	2		T7	4
auto[1342177280:1476395007]	109	1			T17	1		T5	1		T70	1
auto[1476395008:1610612735]	97	1			T2	1		T24	1		T41	1
auto[1610612736:1744830463]	110	1			T3	1		T17	1		T18	1
auto[1744830464:1879048191]	106	1			T18	1		T5	1		T24	1
auto[1879048192:2013265919]	113	1			T4	1		T5	1		T48	2
auto[2013265920:2147483647]	85	1			T8	1		T23	1		T5	3
auto[2147483648:2281701375]	91	1			T41	1		T7	1		T45	1
auto[2281701376:2415919103]	99	1			T5	2		T34	1		T41	4
auto[2415919104:2550136831]	118	1			T23	1		T5	1		T34	1
auto[2550136832:2684354559]	80	1			T39	1		T23	1		T24	1
auto[2684354560:2818572287]	117	1			T4	1		T8	1		T5	2
auto[2818572288:2952790015]	112	1			T39	1		T38	1		T49	1
auto[2952790016:3087007743]	109	1			T17	1		T5	2		T35	2
auto[3087007744:3221225471]	106	1			T2	1		T4	1		T17	1
auto[3221225472:3355443199]	117	1			T4	1		T48	1		T90	1
auto[3355443200:3489660927]	95	1			T2	1		T18	1		T49	1
auto[3489660928:3623878655]	98	1			T2	1		T5	1		T70	1
auto[3623878656:3758096383]	84	1			T3	1		T49	1		T41	1
auto[3758096384:3892314111]	84	1			T93	1		T41	1		T95	1
auto[3892314112:4026531839]	88	1			T2	1		T18	1		T24	1
auto[4026531840:4160749567]	89	1			T211	1		T49	1		T93	1
auto[4160749568:4294967295]	116	1			T3	1		T5	2		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T18	1		T23	1		T34	1
auto[0:134217727]	auto[1]	52	1			T5	1		T41	1		T42	1
auto[134217728:268435455]	auto[0]	53	1			T5	1		T41	1		T262	1
auto[134217728:268435455]	auto[1]	57	1			T58	3		T43	1		T44	1
auto[268435456:402653183]	auto[0]	50	1			T5	1		T27	1		T41	1
auto[268435456:402653183]	auto[1]	40	1			T41	1		T57	1		T45	1
auto[402653184:536870911]	auto[0]	51	1			T27	1		T93	1		T41	2
auto[402653184:536870911]	auto[1]	62	1			T3	1		T70	1		T41	1
auto[536870912:671088639]	auto[0]	39	1			T2	1		T34	1		T41	1
auto[536870912:671088639]	auto[1]	44	1			T75	1		T45	1		T267	1
auto[671088640:805306367]	auto[0]	46	1			T5	1		T28	1		T211	1
auto[671088640:805306367]	auto[1]	50	1			T8	1		T5	1		T95	1
auto[805306368:939524095]	auto[0]	48	1			T5	1		T49	1		T59	1
auto[805306368:939524095]	auto[1]	55	1			T5	2		T211	1		T41	2
auto[939524096:1073741823]	auto[0]	52	1			T5	1		T41	2		T42	1
auto[939524096:1073741823]	auto[1]	46	1			T211	1		T41	1		T7	3
auto[1073741824:1207959551]	auto[0]	39	1			T34	1		T95	1		T44	2
auto[1073741824:1207959551]	auto[1]	55	1			T75	1		T9	1		T42	1
auto[1207959552:1342177279]	auto[0]	49	1			T5	1		T41	2		T7	3
auto[1207959552:1342177279]	auto[1]	36	1			T7	1		T58	1		T415	1
auto[1342177280:1476395007]	auto[0]	55	1			T17	1		T70	1		T7	1
auto[1342177280:1476395007]	auto[1]	54	1			T5	1		T41	1		T198	1
auto[1476395008:1610612735]	auto[0]	44	1			T2	1		T41	1		T42	1
auto[1476395008:1610612735]	auto[1]	53	1			T24	1		T95	1		T7	1
auto[1610612736:1744830463]	auto[0]	59	1			T17	1		T23	1		T5	1
auto[1610612736:1744830463]	auto[1]	51	1			T3	1		T18	1		T41	1
auto[1744830464:1879048191]	auto[0]	41	1			T5	1		T48	1		T45	1
auto[1744830464:1879048191]	auto[1]	65	1			T18	1		T24	1		T93	1
auto[1879048192:2013265919]	auto[0]	62	1			T4	1		T48	1		T41	1
auto[1879048192:2013265919]	auto[1]	51	1			T5	1		T48	1		T41	1
auto[2013265920:2147483647]	auto[0]	45	1			T8	1		T23	1		T5	2
auto[2013265920:2147483647]	auto[1]	40	1			T5	1		T34	1		T27	1
auto[2147483648:2281701375]	auto[0]	40	1			T41	1		T26	1		T305	1
auto[2147483648:2281701375]	auto[1]	51	1			T7	1		T45	1		T58	2
auto[2281701376:2415919103]	auto[0]	48	1			T5	1		T34	1		T41	2
auto[2281701376:2415919103]	auto[1]	51	1			T5	1		T41	2		T262	1
auto[2415919104:2550136831]	auto[0]	64	1			T5	1		T34	1		T90	1
auto[2415919104:2550136831]	auto[1]	54	1			T23	1		T38	1		T42	1
auto[2550136832:2684354559]	auto[0]	44	1			T39	1		T23	1		T24	1
auto[2550136832:2684354559]	auto[1]	36	1			T42	3		T43	2		T270	1
auto[2684354560:2818572287]	auto[0]	57	1			T4	1		T8	1		T5	1
auto[2684354560:2818572287]	auto[1]	60	1			T5	1		T41	1		T7	2
auto[2818572288:2952790015]	auto[0]	49	1			T39	1		T38	1		T49	1
auto[2818572288:2952790015]	auto[1]	63	1			T41	1		T7	1		T262	2
auto[2952790016:3087007743]	auto[0]	50	1			T5	2		T9	1		T28	1
auto[2952790016:3087007743]	auto[1]	59	1			T17	1		T35	2		T9	1
auto[3087007744:3221225471]	auto[0]	44	1			T2	1		T4	1		T17	1
auto[3087007744:3221225471]	auto[1]	62	1			T18	1		T5	2		T27	1
auto[3221225472:3355443199]	auto[0]	60	1			T4	1		T90	1		T19	1
auto[3221225472:3355443199]	auto[1]	57	1			T48	1		T42	1		T58	1
auto[3355443200:3489660927]	auto[0]	41	1			T93	1		T42	1		T7	1
auto[3355443200:3489660927]	auto[1]	54	1			T2	1		T18	1		T49	1
auto[3489660928:3623878655]	auto[0]	50	1			T2	1		T28	1		T42	3
auto[3489660928:3623878655]	auto[1]	48	1			T5	1		T70	1		T41	1
auto[3623878656:3758096383]	auto[0]	37	1			T41	1		T207	1		T7	1
auto[3623878656:3758096383]	auto[1]	47	1			T3	1		T49	1		T7	1
auto[3758096384:3892314111]	auto[0]	41	1			T95	1		T42	1		T45	1
auto[3758096384:3892314111]	auto[1]	43	1			T93	1		T41	1		T51	1
auto[3892314112:4026531839]	auto[0]	38	1			T24	1		T42	1		T7	4
auto[3892314112:4026531839]	auto[1]	50	1			T2	1		T18	1		T41	2
auto[4026531840:4160749567]	auto[0]	43	1			T49	1		T207	1		T45	1
auto[4026531840:4160749567]	auto[1]	46	1			T211	1		T93	1		T41	1
auto[4160749568:4294967295]	auto[0]	55	1			T5	1		T42	1		T7	2
auto[4160749568:4294967295]	auto[1]	61	1			T3	1		T5	1		T38	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1549

1

T2

4

T4

4

T17

3

auto[1]

1656

1

T2

2

T3

4

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T5	1		T24	1		T93	1
auto[134217728:268435455]	112	1			T39	1		T5	1		T90	1
auto[268435456:402653183]	118	1			T2	1		T18	1		T5	3
auto[402653184:536870911]	108	1			T3	1		T23	1		T5	1
auto[536870912:671088639]	92	1			T2	1		T4	1		T34	1
auto[671088640:805306367]	77	1			T2	1		T5	1		T93	1
auto[805306368:939524095]	104	1			T8	1		T23	1		T5	1
auto[939524096:1073741823]	92	1			T59	1		T57	1		T45	1
auto[1073741824:1207959551]	99	1			T2	1		T8	2		T5	1
auto[1207959552:1342177279]	95	1			T17	1		T5	1		T28	1
auto[1342177280:1476395007]	93	1			T4	1		T70	1		T49	1
auto[1476395008:1610612735]	101	1			T18	1		T35	1		T95	2
auto[1610612736:1744830463]	86	1			T2	1		T5	1		T49	1
auto[1744830464:1879048191]	105	1			T23	1		T48	1		T49	1
auto[1879048192:2013265919]	103	1			T3	1		T27	1		T93	1
auto[2013265920:2147483647]	108	1			T5	2		T41	3		T42	1
auto[2147483648:2281701375]	100	1			T24	1		T27	1		T41	2
auto[2281701376:2415919103]	92	1			T3	1		T4	1		T17	1
auto[2415919104:2550136831]	97	1			T5	2		T34	1		T211	1
auto[2550136832:2684354559]	110	1			T18	1		T23	1		T5	3
auto[2684354560:2818572287]	103	1			T5	1		T34	1		T211	1
auto[2818572288:2952790015]	108	1			T18	2		T39	1		T5	1
auto[2952790016:3087007743]	103	1			T27	1		T95	1		T42	2
auto[3087007744:3221225471]	112	1			T17	1		T211	1		T41	3
auto[3221225472:3355443199]	99	1			T18	1		T5	1		T90	1
auto[3355443200:3489660927]	107	1			T75	1		T34	1		T9	1
auto[3489660928:3623878655]	82	1			T5	3		T27	1		T95	1
auto[3623878656:3758096383]	108	1			T17	1		T5	1		T28	1
auto[3758096384:3892314111]	119	1			T23	1		T24	2		T35	1
auto[3892314112:4026531839]	92	1			T2	1		T5	1		T70	1
auto[4026531840:4160749567]	98	1			T4	1		T5	1		T38	2
auto[4160749568:4294967295]	91	1			T3	1		T38	1		T93	1