Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2824

1

T2

6

T3

4

T4

4

auto[1]

255

1

T17

15

T93

1

T109

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T2	2		T17	1		T5	2
auto[134217728:268435455]	118	1			T8	1		T34	1		T93	1
auto[268435456:402653183]	105	1			T17	1		T5	1		T34	1
auto[402653184:536870911]	95	1			T34	1		T211	1		T90	1
auto[536870912:671088639]	107	1			T23	1		T49	1		T41	3
auto[671088640:805306367]	100	1			T2	1		T17	1		T5	1
auto[805306368:939524095]	97	1			T8	1		T24	1		T38	1
auto[939524096:1073741823]	114	1			T17	1		T38	1		T93	1
auto[1073741824:1207959551]	106	1			T4	1		T18	1		T5	2
auto[1207959552:1342177279]	91	1			T2	1		T3	1		T17	1
auto[1342177280:1476395007]	99	1			T4	1		T17	2		T18	1
auto[1476395008:1610612735]	91	1			T17	1		T24	1		T35	1
auto[1610612736:1744830463]	95	1			T17	1		T18	1		T39	1
auto[1744830464:1879048191]	89	1			T3	1		T23	1		T5	1
auto[1879048192:2013265919]	90	1			T17	1		T5	1		T42	1
auto[2013265920:2147483647]	84	1			T17	1		T18	1		T5	1
auto[2147483648:2281701375]	88	1			T17	2		T5	2		T28	1
auto[2281701376:2415919103]	102	1			T3	1		T23	1		T5	2
auto[2415919104:2550136831]	90	1			T17	1		T18	1		T38	1
auto[2550136832:2684354559]	84	1			T17	1		T39	1		T93	1
auto[2684354560:2818572287]	112	1			T24	1		T9	1		T57	1
auto[2818572288:2952790015]	84	1			T23	1		T70	1		T27	1
auto[2952790016:3087007743]	109	1			T17	1		T5	1		T207	1
auto[3087007744:3221225471]	98	1			T4	1		T5	2		T48	1
auto[3221225472:3355443199]	89	1			T34	2		T51	1		T7	1
auto[3355443200:3489660927]	92	1			T17	1		T18	1		T5	3
auto[3489660928:3623878655]	105	1			T2	1		T17	1		T5	1
auto[3623878656:3758096383]	81	1			T3	1		T24	1		T34	1
auto[3758096384:3892314111]	97	1			T17	1		T5	2		T75	1
auto[3892314112:4026531839]	92	1			T4	1		T49	1		T207	1
auto[4026531840:4160749567]	95	1			T41	1		T95	1		T7	1
auto[4160749568:4294967295]	83	1			T2	1		T93	1		T41	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	86	1			T2	2		T5	2		T27	1
auto[0:134217727]	auto[1]	11	1			T17	1		T368	1		T407	1
auto[134217728:268435455]	auto[0]	108	1			T8	1		T34	1		T93	1
auto[134217728:268435455]	auto[1]	10	1			T126	1		T144	1		T399	1
auto[268435456:402653183]	auto[0]	96	1			T5	1		T34	1		T49	1
auto[268435456:402653183]	auto[1]	9	1			T17	1		T140	1		T349	1
auto[402653184:536870911]	auto[0]	87	1			T34	1		T211	1		T90	1
auto[402653184:536870911]	auto[1]	8	1			T109	1		T333	1		T425	1
auto[536870912:671088639]	auto[0]	97	1			T23	1		T49	1		T41	3
auto[536870912:671088639]	auto[1]	10	1			T349	1		T409	1		T244	1
auto[671088640:805306367]	auto[0]	93	1			T2	1		T5	1		T70	2
auto[671088640:805306367]	auto[1]	7	1			T17	1		T409	1		T410	1
auto[805306368:939524095]	auto[0]	89	1			T8	1		T24	1		T38	1
auto[805306368:939524095]	auto[1]	8	1			T384	1		T429	2		T432	1
auto[939524096:1073741823]	auto[0]	104	1			T38	1		T93	1		T41	1
auto[939524096:1073741823]	auto[1]	10	1			T17	1		T109	1		T126	1
auto[1073741824:1207959551]	auto[0]	101	1			T4	1		T18	1		T5	2
auto[1073741824:1207959551]	auto[1]	5	1			T368	1		T345	1		T399	1
auto[1207959552:1342177279]	auto[0]	84	1			T2	1		T3	1		T8	1
auto[1207959552:1342177279]	auto[1]	7	1			T17	1		T425	1		T293	1
auto[1342177280:1476395007]	auto[0]	83	1			T4	1		T18	1		T23	1
auto[1342177280:1476395007]	auto[1]	16	1			T17	2		T305	1		T140	1
auto[1476395008:1610612735]	auto[0]	84	1			T17	1		T24	1		T35	1
auto[1476395008:1610612735]	auto[1]	7	1			T140	1		T345	1		T407	1
auto[1610612736:1744830463]	auto[0]	87	1			T18	1		T39	1		T5	1
auto[1610612736:1744830463]	auto[1]	8	1			T17	1		T349	1		T409	1
auto[1744830464:1879048191]	auto[0]	79	1			T3	1		T23	1		T5	1
auto[1744830464:1879048191]	auto[1]	10	1			T144	1		T409	1		T408	1
auto[1879048192:2013265919]	auto[0]	79	1			T5	1		T42	1		T7	1
auto[1879048192:2013265919]	auto[1]	11	1			T17	1		T260	1		T333	1
auto[2013265920:2147483647]	auto[0]	79	1			T18	1		T5	1		T211	1
auto[2013265920:2147483647]	auto[1]	5	1			T17	1		T293	1		T436	1
auto[2147483648:2281701375]	auto[0]	83	1			T17	2		T5	2		T28	1
auto[2147483648:2281701375]	auto[1]	5	1			T345	1		T386	1		T430	1
auto[2281701376:2415919103]	auto[0]	97	1			T3	1		T23	1		T5	2
auto[2281701376:2415919103]	auto[1]	5	1			T260	1		T393	1		T245	1
auto[2415919104:2550136831]	auto[0]	82	1			T18	1		T38	1		T49	1
auto[2415919104:2550136831]	auto[1]	8	1			T17	1		T109	1		T305	1
auto[2550136832:2684354559]	auto[0]	77	1			T39	1		T93	1		T41	2
auto[2550136832:2684354559]	auto[1]	7	1			T17	1		T260	2		T333	1
auto[2684354560:2818572287]	auto[0]	105	1			T24	1		T9	1		T57	1
auto[2684354560:2818572287]	auto[1]	7	1			T109	1		T368	1		T409	1
auto[2818572288:2952790015]	auto[0]	79	1			T23	1		T70	1		T27	1
auto[2818572288:2952790015]	auto[1]	5	1			T407	1		T430	1		T384	1
auto[2952790016:3087007743]	auto[0]	99	1			T5	1		T207	1		T42	1
auto[2952790016:3087007743]	auto[1]	10	1			T17	1		T142	1		T368	1
auto[3087007744:3221225471]	auto[0]	87	1			T4	1		T5	2		T48	1
auto[3087007744:3221225471]	auto[1]	11	1			T305	1		T260	1		T368	1
auto[3221225472:3355443199]	auto[0]	84	1			T34	2		T51	1		T7	1
auto[3221225472:3355443199]	auto[1]	5	1			T109	1		T293	1		T399	1
auto[3355443200:3489660927]	auto[0]	85	1			T18	1		T5	3		T42	1
auto[3355443200:3489660927]	auto[1]	7	1			T17	1		T140	2		T144	1
auto[3489660928:3623878655]	auto[0]	97	1			T2	1		T17	1		T5	1
auto[3489660928:3623878655]	auto[1]	8	1			T140	1		T260	1		T368	1
auto[3623878656:3758096383]	auto[0]	73	1			T3	1		T24	1		T34	1
auto[3623878656:3758096383]	auto[1]	8	1			T126	1		T260	2		T144	1
auto[3758096384:3892314111]	auto[0]	89	1			T5	2		T75	1		T41	1
auto[3758096384:3892314111]	auto[1]	8	1			T17	1		T142	1		T144	1
auto[3892314112:4026531839]	auto[0]	88	1			T4	1		T49	1		T207	1
auto[3892314112:4026531839]	auto[1]	4	1			T349	1		T399	1		T408	1
auto[4026531840:4160749567]	auto[0]	84	1			T41	1		T95	1		T7	1
auto[4026531840:4160749567]	auto[1]	11	1			T407	1		T409	1		T406	1
auto[4160749568:4294967295]	auto[0]	79	1			T2	1		T41	3		T42	3
auto[4160749568:4294967295]	auto[1]	4	1			T93	1		T407	1		T429	1