Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6602

1

T2

11

T3

10

T4

7

auto[1]

258

1

T17

10

T93

1

T109

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2776	1			T2	6		T3	5		T4	3
auto[134217728:268435455]	167	1			T23	1		T5	1		T24	1
auto[268435456:402653183]	144	1			T24	1		T19	1		T207	2
auto[402653184:536870911]	151	1			T2	1		T3	1		T5	1
auto[536870912:671088639]	139	1			T23	1		T5	2		T9	1
auto[671088640:805306367]	149	1			T5	2		T24	1		T75	1
auto[805306368:939524095]	152	1			T2	1		T17	1		T5	3
auto[939524096:1073741823]	140	1			T3	1		T17	1		T41	2
auto[1073741824:1207959551]	139	1			T8	2		T5	1		T9	1
auto[1207959552:1342177279]	92	1			T17	1		T18	1		T39	1
auto[1342177280:1476395007]	130	1			T38	1		T28	1		T211	1
auto[1476395008:1610612735]	130	1			T2	1		T4	1		T8	1
auto[1610612736:1744830463]	131	1			T18	1		T5	2		T93	1
auto[1744830464:1879048191]	119	1			T18	1		T5	1		T24	1
auto[1879048192:2013265919]	126	1			T17	1		T207	1		T42	1
auto[2013265920:2147483647]	125	1			T18	1		T5	1		T34	1
auto[2147483648:2281701375]	141	1			T17	1		T18	1		T24	1
auto[2281701376:2415919103]	116	1			T2	1		T3	1		T5	1
auto[2415919104:2550136831]	136	1			T5	2		T70	1		T211	1
auto[2550136832:2684354559]	129	1			T17	1		T5	1		T70	1
auto[2684354560:2818572287]	136	1			T2	1		T4	1		T17	1
auto[2818572288:2952790015]	135	1			T4	2		T17	1		T18	1
auto[2952790016:3087007743]	106	1			T17	2		T18	2		T70	1
auto[3087007744:3221225471]	118	1			T18	1		T211	1		T90	1
auto[3221225472:3355443199]	122	1			T18	2		T23	1		T5	1
auto[3355443200:3489660927]	132	1			T24	1		T211	1		T90	1
auto[3489660928:3623878655]	125	1			T24	2		T34	1		T93	1
auto[3623878656:3758096383]	132	1			T3	1		T18	1		T5	1
auto[3758096384:3892314111]	118	1			T17	1		T93	1		T41	1
auto[3892314112:4026531839]	143	1			T3	1		T17	1		T18	1
auto[4026531840:4160749567]	141	1			T18	2		T23	1		T211	1
auto[4160749568:4294967295]	120	1			T23	1		T5	1		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2763	1			T2	6		T3	5		T4	3
auto[0:134217727]	auto[1]	13	1			T17	2		T305	1		T142	1
auto[134217728:268435455]	auto[0]	161	1			T23	1		T5	1		T24	1
auto[134217728:268435455]	auto[1]	6	1			T260	1		T393	1		T257	1
auto[268435456:402653183]	auto[0]	136	1			T24	1		T19	1		T207	2
auto[268435456:402653183]	auto[1]	8	1			T409	2		T399	1		T257	1
auto[402653184:536870911]	auto[0]	146	1			T2	1		T3	1		T5	1
auto[402653184:536870911]	auto[1]	5	1			T349	1		T409	1		T408	1
auto[536870912:671088639]	auto[0]	133	1			T23	1		T5	2		T9	1
auto[536870912:671088639]	auto[1]	6	1			T349	1		T429	1		T331	1
auto[671088640:805306367]	auto[0]	135	1			T5	2		T24	1		T75	1
auto[671088640:805306367]	auto[1]	14	1			T109	1		T140	1		T142	1
auto[805306368:939524095]	auto[0]	146	1			T2	1		T17	1		T5	3
auto[805306368:939524095]	auto[1]	6	1			T109	1		T140	1		T126	1
auto[939524096:1073741823]	auto[0]	132	1			T3	1		T17	1		T41	2
auto[939524096:1073741823]	auto[1]	8	1			T126	1		T257	1		T430	1
auto[1073741824:1207959551]	auto[0]	134	1			T8	2		T5	1		T9	1
auto[1073741824:1207959551]	auto[1]	5	1			T386	1		T408	1		T257	1
auto[1207959552:1342177279]	auto[0]	83	1			T18	1		T39	1		T70	1
auto[1207959552:1342177279]	auto[1]	9	1			T17	1		T126	1		T333	1
auto[1342177280:1476395007]	auto[0]	122	1			T38	1		T28	1		T211	1
auto[1342177280:1476395007]	auto[1]	8	1			T144	1		T333	1		T405	1
auto[1476395008:1610612735]	auto[0]	124	1			T2	1		T4	1		T8	1
auto[1476395008:1610612735]	auto[1]	6	1			T245	1		T265	1		T431	1
auto[1610612736:1744830463]	auto[0]	123	1			T18	1		T5	2		T93	1
auto[1610612736:1744830463]	auto[1]	8	1			T109	1		T429	2		T432	1
auto[1744830464:1879048191]	auto[0]	110	1			T18	1		T5	1		T24	1
auto[1744830464:1879048191]	auto[1]	9	1			T349	2		T407	1		T410	1
auto[1879048192:2013265919]	auto[0]	116	1			T207	1		T42	1		T7	2
auto[1879048192:2013265919]	auto[1]	10	1			T17	1		T109	1		T142	1
auto[2013265920:2147483647]	auto[0]	117	1			T18	1		T5	1		T34	1
auto[2013265920:2147483647]	auto[1]	8	1			T109	1		T349	1		T399	1
auto[2147483648:2281701375]	auto[0]	132	1			T18	1		T24	1		T70	1
auto[2147483648:2281701375]	auto[1]	9	1			T17	1		T142	1		T260	1
auto[2281701376:2415919103]	auto[0]	110	1			T2	1		T3	1		T5	1
auto[2281701376:2415919103]	auto[1]	6	1			T260	1		T349	1		T368	1
auto[2415919104:2550136831]	auto[0]	131	1			T5	2		T70	1		T211	1
auto[2415919104:2550136831]	auto[1]	5	1			T140	1		T126	1		T407	1
auto[2550136832:2684354559]	auto[0]	123	1			T17	1		T5	1		T70	1
auto[2550136832:2684354559]	auto[1]	6	1			T293	2		T244	2		T410	1
auto[2684354560:2818572287]	auto[0]	127	1			T2	1		T4	1		T23	1
auto[2684354560:2818572287]	auto[1]	9	1			T17	1		T140	1		T349	1
auto[2818572288:2952790015]	auto[0]	124	1			T4	2		T18	1		T23	1
auto[2818572288:2952790015]	auto[1]	11	1			T17	1		T109	1		T368	1
auto[2952790016:3087007743]	auto[0]	98	1			T17	1		T18	2		T70	1
auto[2952790016:3087007743]	auto[1]	8	1			T17	1		T142	1		T144	1
auto[3087007744:3221225471]	auto[0]	111	1			T18	1		T211	1		T90	1
auto[3087007744:3221225471]	auto[1]	7	1			T109	1		T144	1		T349	1
auto[3221225472:3355443199]	auto[0]	115	1			T18	2		T23	1		T5	1
auto[3221225472:3355443199]	auto[1]	7	1			T345	1		T384	1		T429	1
auto[3355443200:3489660927]	auto[0]	126	1			T24	1		T211	1		T90	1
auto[3355443200:3489660927]	auto[1]	6	1			T142	1		T333	1		T349	1
auto[3489660928:3623878655]	auto[0]	113	1			T24	2		T34	1		T93	1
auto[3489660928:3623878655]	auto[1]	12	1			T349	1		T406	3		T399	1
auto[3623878656:3758096383]	auto[0]	120	1			T3	1		T18	1		T5	1
auto[3623878656:3758096383]	auto[1]	12	1			T93	1		T244	1		T406	1
auto[3758096384:3892314111]	auto[0]	113	1			T93	1		T41	1		T95	2
auto[3758096384:3892314111]	auto[1]	5	1			T17	1		T406	1		T399	1
auto[3892314112:4026531839]	auto[0]	135	1			T3	1		T18	1		T39	1
auto[3892314112:4026531839]	auto[1]	8	1			T17	1		T386	2		T429	2
auto[4026531840:4160749567]	auto[0]	133	1			T18	2		T23	1		T211	1
auto[4026531840:4160749567]	auto[1]	8	1			T140	2		T333	1		T425	1
auto[4160749568:4294967295]	auto[0]	110	1			T23	1		T5	1		T38	1
auto[4160749568:4294967295]	auto[1]	10	1			T109	1		T140	1		T333	1