Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.07 98.10 98.24 100.00 99.11 98.41 91.68


Total test records in report: 1066
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1006 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3516283443 Apr 28 12:39:53 PM PDT 24 Apr 28 12:39:57 PM PDT 24 152599063 ps
T179 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.272658512 Apr 28 12:39:48 PM PDT 24 Apr 28 12:39:55 PM PDT 24 457895848 ps
T1007 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1858723951 Apr 28 12:39:44 PM PDT 24 Apr 28 12:39:50 PM PDT 24 161188663 ps
T1008 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.774963436 Apr 28 12:39:45 PM PDT 24 Apr 28 12:39:48 PM PDT 24 24846738 ps
T1009 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4230056011 Apr 28 12:39:56 PM PDT 24 Apr 28 12:39:59 PM PDT 24 24165825 ps
T1010 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3417094823 Apr 28 12:39:54 PM PDT 24 Apr 28 12:39:58 PM PDT 24 178098769 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2908090979 Apr 28 12:40:16 PM PDT 24 Apr 28 12:40:18 PM PDT 24 96491299 ps
T1012 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1451240150 Apr 28 12:40:02 PM PDT 24 Apr 28 12:40:05 PM PDT 24 14218026 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1952593349 Apr 28 12:39:58 PM PDT 24 Apr 28 12:40:00 PM PDT 24 48188255 ps
T1014 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3210040958 Apr 28 12:39:49 PM PDT 24 Apr 28 12:39:52 PM PDT 24 25269806 ps
T1015 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2508096245 Apr 28 12:40:05 PM PDT 24 Apr 28 12:40:16 PM PDT 24 1386294970 ps
T1016 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4118568303 Apr 28 12:39:46 PM PDT 24 Apr 28 12:39:47 PM PDT 24 11288886 ps
T1017 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.845317057 Apr 28 12:40:57 PM PDT 24 Apr 28 12:40:59 PM PDT 24 14348997 ps
T1018 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2803460390 Apr 28 12:40:02 PM PDT 24 Apr 28 12:40:05 PM PDT 24 14928665 ps
T185 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1124027398 Apr 28 12:39:51 PM PDT 24 Apr 28 12:39:56 PM PDT 24 242849927 ps
T1019 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2588863174 Apr 28 12:39:51 PM PDT 24 Apr 28 12:39:55 PM PDT 24 81328241 ps
T1020 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4281976216 Apr 28 12:40:00 PM PDT 24 Apr 28 12:40:02 PM PDT 24 85695721 ps
T1021 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2592238785 Apr 28 12:39:52 PM PDT 24 Apr 28 12:39:56 PM PDT 24 149002195 ps
T1022 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2160332370 Apr 28 12:40:13 PM PDT 24 Apr 28 12:40:16 PM PDT 24 208601001 ps
T1023 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4267985633 Apr 28 12:40:02 PM PDT 24 Apr 28 12:40:06 PM PDT 24 67368907 ps
T1024 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.43319671 Apr 28 12:40:01 PM PDT 24 Apr 28 12:40:18 PM PDT 24 444518441 ps
T1025 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3955135928 Apr 28 12:40:26 PM PDT 24 Apr 28 12:40:34 PM PDT 24 29291708 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2510255200 Apr 28 12:39:37 PM PDT 24 Apr 28 12:40:03 PM PDT 24 1756033141 ps
T1027 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2151974927 Apr 28 12:39:47 PM PDT 24 Apr 28 12:39:49 PM PDT 24 12330662 ps
T1028 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4004409121 Apr 28 12:39:52 PM PDT 24 Apr 28 12:39:54 PM PDT 24 10783279 ps
T1029 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.545465885 Apr 28 12:40:02 PM PDT 24 Apr 28 12:40:06 PM PDT 24 27480174 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2249428763 Apr 28 12:39:51 PM PDT 24 Apr 28 12:39:53 PM PDT 24 28553401 ps
T1031 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.959745800 Apr 28 12:40:16 PM PDT 24 Apr 28 12:40:19 PM PDT 24 10008268 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.576109630 Apr 28 12:40:01 PM PDT 24 Apr 28 12:40:04 PM PDT 24 54524967 ps
T1033 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2743486037 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:20 PM PDT 24 19578196 ps
T171 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2594153451 Apr 28 12:39:52 PM PDT 24 Apr 28 12:39:58 PM PDT 24 313034001 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.518449922 Apr 28 12:39:47 PM PDT 24 Apr 28 12:39:51 PM PDT 24 249063935 ps
T1035 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2297767976 Apr 28 12:39:57 PM PDT 24 Apr 28 12:39:59 PM PDT 24 14735697 ps
T1036 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.86382809 Apr 28 12:39:44 PM PDT 24 Apr 28 12:39:48 PM PDT 24 134197862 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2568498658 Apr 28 12:39:54 PM PDT 24 Apr 28 12:40:07 PM PDT 24 70541391 ps
T165 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3051383466 Apr 28 12:39:53 PM PDT 24 Apr 28 12:42:10 PM PDT 24 25461476025 ps
T1038 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4120888322 Apr 28 12:40:35 PM PDT 24 Apr 28 12:40:37 PM PDT 24 39836592 ps
T1039 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1368340852 Apr 28 12:39:47 PM PDT 24 Apr 28 12:39:49 PM PDT 24 53305826 ps
T1040 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1783165047 Apr 28 12:39:53 PM PDT 24 Apr 28 12:39:58 PM PDT 24 181180664 ps
T177 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3118399908 Apr 28 12:39:45 PM PDT 24 Apr 28 12:39:55 PM PDT 24 980701516 ps
T1041 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3071350570 Apr 28 12:39:47 PM PDT 24 Apr 28 12:39:52 PM PDT 24 372730536 ps
T1042 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3142373319 Apr 28 12:40:20 PM PDT 24 Apr 28 12:40:22 PM PDT 24 49232088 ps
T1043 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1626932733 Apr 28 12:39:52 PM PDT 24 Apr 28 12:39:54 PM PDT 24 159311648 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3787794899 Apr 28 12:39:38 PM PDT 24 Apr 28 12:39:40 PM PDT 24 23585077 ps
T1045 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3060533035 Apr 28 12:39:56 PM PDT 24 Apr 28 12:40:05 PM PDT 24 327302398 ps
T1046 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2700240349 Apr 28 12:39:42 PM PDT 24 Apr 28 12:39:45 PM PDT 24 30361047 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1489847949 Apr 28 12:39:37 PM PDT 24 Apr 28 12:39:43 PM PDT 24 184692309 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3805995725 Apr 28 12:39:47 PM PDT 24 Apr 28 12:40:06 PM PDT 24 3611790918 ps
T1049 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.488810274 Apr 28 12:39:46 PM PDT 24 Apr 28 12:39:47 PM PDT 24 35673104 ps
T1050 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.109078962 Apr 28 12:39:50 PM PDT 24 Apr 28 12:39:56 PM PDT 24 155183339 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.904581057 Apr 28 12:39:48 PM PDT 24 Apr 28 12:39:51 PM PDT 24 205686522 ps
T1052 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.110863596 Apr 28 12:40:01 PM PDT 24 Apr 28 12:40:06 PM PDT 24 134158594 ps
T1053 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2860062494 Apr 28 12:39:46 PM PDT 24 Apr 28 12:39:48 PM PDT 24 11065986 ps
T1054 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.654756283 Apr 28 12:40:07 PM PDT 24 Apr 28 12:40:10 PM PDT 24 58994927 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4222147776 Apr 28 12:39:45 PM PDT 24 Apr 28 12:39:50 PM PDT 24 202389652 ps
T1056 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1379708649 Apr 28 12:40:18 PM PDT 24 Apr 28 12:40:21 PM PDT 24 85580002 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2314700487 Apr 28 12:39:39 PM PDT 24 Apr 28 12:39:54 PM PDT 24 733786849 ps
T1058 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3250601635 Apr 28 12:40:00 PM PDT 24 Apr 28 12:40:02 PM PDT 24 54101212 ps
T1059 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2265915479 Apr 28 12:40:15 PM PDT 24 Apr 28 12:40:22 PM PDT 24 543329939 ps
T1060 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3417315172 Apr 28 12:40:07 PM PDT 24 Apr 28 12:40:09 PM PDT 24 9222450 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1131549514 Apr 28 12:40:02 PM PDT 24 Apr 28 12:40:10 PM PDT 24 987229565 ps
T1062 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.19608997 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:13 PM PDT 24 21283602 ps
T1063 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1721408140 Apr 28 12:39:44 PM PDT 24 Apr 28 12:39:51 PM PDT 24 160638841 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2725890643 Apr 28 12:39:49 PM PDT 24 Apr 28 12:39:51 PM PDT 24 321635763 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.878900415 Apr 28 12:39:31 PM PDT 24 Apr 28 12:39:37 PM PDT 24 308136408 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3535807630 Apr 28 12:40:16 PM PDT 24 Apr 28 12:40:20 PM PDT 24 88180432 ps

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3063706440
Short name T17
Test name
Test status
Simulation time 6784099388 ps
CPU time 84.97 seconds
Started Apr 28 12:43:58 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 214272 kb
Host smart-915a8aa0-d2aa-4fd9-8df3-c9acc6d68140
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063706440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3063706440
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1548636412
Short name T5
Test name
Test status
Simulation time 1429378547 ps
CPU time 46.1 seconds
Started Apr 28 12:42:03 PM PDT 24
Finished Apr 28 12:42:51 PM PDT 24
Peak memory 216208 kb
Host smart-ca6308dc-7c56-45df-8642-1ca91d3f9f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548636412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1548636412
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.629643340
Short name T7
Test name
Test status
Simulation time 25649813766 ps
CPU time 307.33 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:47:23 PM PDT 24
Peak memory 219232 kb
Host smart-3eb50319-dcde-474b-8d87-45fb05b642ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629643340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.629643340
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.889874245
Short name T44
Test name
Test status
Simulation time 8641853932 ps
CPU time 33.46 seconds
Started Apr 28 12:42:20 PM PDT 24
Finished Apr 28 12:42:54 PM PDT 24
Peak memory 215748 kb
Host smart-48b476b9-937f-4737-8f6b-964e8652364a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889874245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.889874245
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.722162042
Short name T6
Test name
Test status
Simulation time 41999039635 ps
CPU time 151.9 seconds
Started Apr 28 12:41:38 PM PDT 24
Finished Apr 28 12:44:11 PM PDT 24
Peak memory 263228 kb
Host smart-32d2fc7b-ea83-4535-897d-17c4e13461c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722162042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.722162042
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2607217730
Short name T100
Test name
Test status
Simulation time 580403638 ps
CPU time 21.81 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 222356 kb
Host smart-9fa1a79c-69cb-4043-a960-5a5d27654a35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607217730 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2607217730
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3562408724
Short name T8
Test name
Test status
Simulation time 1023348849 ps
CPU time 7.32 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 209992 kb
Host smart-954d986d-d097-4d6a-841b-05e43e136479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562408724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3562408724
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3654530767
Short name T41
Test name
Test status
Simulation time 4077011211 ps
CPU time 38.65 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 217236 kb
Host smart-0d6da4b3-f0fd-43db-8472-4429ef7321f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654530767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3654530767
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.280826444
Short name T104
Test name
Test status
Simulation time 273168926 ps
CPU time 4.24 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 214504 kb
Host smart-bd4b86ef-9b49-406a-841a-415e5b58c481
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280826444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.280826444
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3601996303
Short name T76
Test name
Test status
Simulation time 89036156 ps
CPU time 4.3 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 220476 kb
Host smart-654be2fe-c875-424a-a2fb-5f1868460f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601996303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3601996303
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2031704637
Short name T140
Test name
Test status
Simulation time 230823487 ps
CPU time 11.77 seconds
Started Apr 28 12:42:04 PM PDT 24
Finished Apr 28 12:42:17 PM PDT 24
Peak memory 222308 kb
Host smart-1060fdd7-7d57-4730-8384-3df40d129376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031704637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2031704637
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3394926958
Short name T58
Test name
Test status
Simulation time 27870178081 ps
CPU time 222.47 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:47:31 PM PDT 24
Peak memory 222312 kb
Host smart-12d8d47b-af3a-492d-bac7-bb969e1f6974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394926958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3394926958
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1196548602
Short name T98
Test name
Test status
Simulation time 425854239 ps
CPU time 20.58 seconds
Started Apr 28 12:42:44 PM PDT 24
Finished Apr 28 12:43:05 PM PDT 24
Peak memory 220880 kb
Host smart-8d94fd94-bb41-4e85-943d-fad54965b21f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196548602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1196548602
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.912728871
Short name T432
Test name
Test status
Simulation time 423502889 ps
CPU time 5.99 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 213948 kb
Host smart-d6489abe-280c-4a23-85f4-e93b2418523d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912728871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.912728871
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2490534507
Short name T34
Test name
Test status
Simulation time 539303014 ps
CPU time 7.16 seconds
Started Apr 28 12:42:26 PM PDT 24
Finished Apr 28 12:42:33 PM PDT 24
Peak memory 210464 kb
Host smart-946c7987-4786-4a02-99fc-bf0568243fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490534507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2490534507
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2258905947
Short name T257
Test name
Test status
Simulation time 168773618 ps
CPU time 9.34 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 215212 kb
Host smart-c6166efb-d0ff-4260-a8a5-229d86939102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258905947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2258905947
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3858429922
Short name T108
Test name
Test status
Simulation time 1177413504 ps
CPU time 25.21 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:40:18 PM PDT 24
Peak memory 220348 kb
Host smart-8be976d5-1541-4c3f-a8ed-ea06f425d18e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858429922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3858429922
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1518902394
Short name T45
Test name
Test status
Simulation time 11048842655 ps
CPU time 113.53 seconds
Started Apr 28 12:43:25 PM PDT 24
Finished Apr 28 12:45:19 PM PDT 24
Peak memory 216392 kb
Host smart-79b05822-14cb-4149-9a04-dc06092bbbcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518902394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1518902394
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1517495418
Short name T157
Test name
Test status
Simulation time 749475966 ps
CPU time 10.83 seconds
Started Apr 28 12:40:18 PM PDT 24
Finished Apr 28 12:40:30 PM PDT 24
Peak memory 209656 kb
Host smart-4b0299f8-bd55-4e8c-bc6d-40dce82e6c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517495418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1517495418
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.910921263
Short name T431
Test name
Test status
Simulation time 287472543 ps
CPU time 15.8 seconds
Started Apr 28 12:43:36 PM PDT 24
Finished Apr 28 12:43:52 PM PDT 24
Peak memory 222296 kb
Host smart-937ce777-5966-4fc5-8d11-3d81771a5d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910921263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.910921263
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2036470238
Short name T265
Test name
Test status
Simulation time 61900838 ps
CPU time 4.41 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 213932 kb
Host smart-0016f977-a12b-4237-bbab-a0712835bbaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036470238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2036470238
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2936244638
Short name T36
Test name
Test status
Simulation time 117785478 ps
CPU time 4.98 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:42:51 PM PDT 24
Peak memory 209808 kb
Host smart-a3350466-7909-43ae-a6fa-abf1ec784370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936244638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2936244638
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.154224373
Short name T78
Test name
Test status
Simulation time 154964278 ps
CPU time 4.55 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 214136 kb
Host smart-87c5a793-772c-4658-bb41-c77f73ab763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154224373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.154224373
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1577943894
Short name T29
Test name
Test status
Simulation time 246786038 ps
CPU time 3.2 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:01 PM PDT 24
Peak memory 209092 kb
Host smart-4df784ce-a32b-44e7-b02e-29e424412780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577943894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1577943894
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3270881179
Short name T199
Test name
Test status
Simulation time 2277431518 ps
CPU time 52.97 seconds
Started Apr 28 12:42:41 PM PDT 24
Finished Apr 28 12:43:35 PM PDT 24
Peak memory 222312 kb
Host smart-7443e859-7935-4e50-993d-ad4be3451eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270881179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3270881179
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.656831750
Short name T451
Test name
Test status
Simulation time 46890936 ps
CPU time 0.75 seconds
Started Apr 28 12:41:30 PM PDT 24
Finished Apr 28 12:41:31 PM PDT 24
Peak memory 205504 kb
Host smart-ad35044a-2d53-4b63-8e77-718f1f3e0332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656831750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.656831750
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.424194548
Short name T50
Test name
Test status
Simulation time 937056946 ps
CPU time 12.61 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 210764 kb
Host smart-0d974bec-ba1a-461c-b04b-9e74e3d31602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424194548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.424194548
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.696013100
Short name T153
Test name
Test status
Simulation time 2209262909 ps
CPU time 17.2 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:53 PM PDT 24
Peak memory 217108 kb
Host smart-d1af4544-0343-4a6f-a9c3-4d4a2ca3592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696013100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.696013100
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2979014255
Short name T399
Test name
Test status
Simulation time 317618418 ps
CPU time 15.6 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 214104 kb
Host smart-8ceadc4e-f260-4e89-bcd9-fe84f2bfd517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979014255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2979014255
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.855163857
Short name T216
Test name
Test status
Simulation time 80981698 ps
CPU time 3.79 seconds
Started Apr 28 12:43:13 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 222212 kb
Host smart-71130891-c252-44c4-9745-5280b6938828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855163857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.855163857
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3128771758
Short name T21
Test name
Test status
Simulation time 171792618 ps
CPU time 2.29 seconds
Started Apr 28 12:43:30 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 214256 kb
Host smart-d5d4e548-15f9-4e6d-b1a7-cef848c49f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128771758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3128771758
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2984491477
Short name T38
Test name
Test status
Simulation time 62329438 ps
CPU time 3.49 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 210652 kb
Host smart-b3c66962-a9ac-46b4-8f11-700c199adc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984491477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2984491477
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.492455218
Short name T64
Test name
Test status
Simulation time 4248372817 ps
CPU time 45.75 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:42:30 PM PDT 24
Peak memory 215852 kb
Host smart-fd5187ad-14d4-495e-8ce9-c6fe7868f8e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492455218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.492455218
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4019524294
Short name T409
Test name
Test status
Simulation time 127613057 ps
CPU time 6.72 seconds
Started Apr 28 12:42:36 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 214288 kb
Host smart-b27b53e9-d600-4cba-aace-a6af91d97f06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019524294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4019524294
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1146503129
Short name T246
Test name
Test status
Simulation time 45466954 ps
CPU time 3.42 seconds
Started Apr 28 12:43:32 PM PDT 24
Finished Apr 28 12:43:37 PM PDT 24
Peak memory 214184 kb
Host smart-66a2fd66-6b58-49c1-b711-5162912b9d20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146503129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1146503129
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.287878020
Short name T43
Test name
Test status
Simulation time 1194423647 ps
CPU time 46.39 seconds
Started Apr 28 12:43:43 PM PDT 24
Finished Apr 28 12:44:30 PM PDT 24
Peak memory 221416 kb
Host smart-f5085e30-a169-4e72-b01c-608816e61db2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287878020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.287878020
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1315568304
Short name T244
Test name
Test status
Simulation time 228784239 ps
CPU time 3.79 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 215192 kb
Host smart-8dccb6a2-495e-4431-9ffe-9549d4a8bfe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315568304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1315568304
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.181955477
Short name T323
Test name
Test status
Simulation time 189151683 ps
CPU time 7.74 seconds
Started Apr 28 12:42:28 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 210524 kb
Host smart-212defa1-b283-4ff1-9e8b-a55857a830d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181955477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.181955477
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3164390965
Short name T230
Test name
Test status
Simulation time 636067149822 ps
CPU time 1048.31 seconds
Started Apr 28 12:41:38 PM PDT 24
Finished Apr 28 12:59:08 PM PDT 24
Peak memory 234520 kb
Host smart-f43c9be8-0ba4-4076-b64e-39fae63470e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164390965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3164390965
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.430747654
Short name T166
Test name
Test status
Simulation time 272758066 ps
CPU time 9.21 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 214168 kb
Host smart-81b7fcbd-8487-4054-8ca6-177904474e01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430747654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.430747654
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2893300326
Short name T898
Test name
Test status
Simulation time 1102304177 ps
CPU time 18.03 seconds
Started Apr 28 12:42:08 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 222368 kb
Host smart-fb545efa-2111-4d4d-bc3b-bfe6c429d25a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893300326 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2893300326
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1617430619
Short name T361
Test name
Test status
Simulation time 131652769 ps
CPU time 5.9 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 213964 kb
Host smart-208d297f-e1e0-437b-a431-f82ad0c307c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617430619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1617430619
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1764527189
Short name T316
Test name
Test status
Simulation time 1974259506 ps
CPU time 61.63 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 214592 kb
Host smart-0eba40d8-49db-4c1e-aa64-0ad1c37e97f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764527189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1764527189
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.272658512
Short name T179
Test name
Test status
Simulation time 457895848 ps
CPU time 6.37 seconds
Started Apr 28 12:39:48 PM PDT 24
Finished Apr 28 12:39:55 PM PDT 24
Peak memory 214252 kb
Host smart-d6378cee-8239-4e01-961a-362c541d584a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272658512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.272658512
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1111620798
Short name T175
Test name
Test status
Simulation time 14757023602 ps
CPU time 108.19 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 226688 kb
Host smart-007ce1d9-f444-463c-880e-b0d81c7ec239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111620798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1111620798
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1527010775
Short name T968
Test name
Test status
Simulation time 63139293 ps
CPU time 2.16 seconds
Started Apr 28 12:39:38 PM PDT 24
Finished Apr 28 12:39:41 PM PDT 24
Peak memory 214548 kb
Host smart-bdda68aa-8c2c-4c20-ba0c-0a4734af26e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527010775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1527010775
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.600744360
Short name T154
Test name
Test status
Simulation time 42351640 ps
CPU time 3.16 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 218020 kb
Host smart-c377154b-29d2-46a6-b5c8-b365bbda400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600744360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.600744360
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.722370901
Short name T363
Test name
Test status
Simulation time 133392657 ps
CPU time 5.75 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 213940 kb
Host smart-0c242df4-aced-4a9c-898f-1253b0cdde38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722370901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.722370901
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1393355801
Short name T358
Test name
Test status
Simulation time 631974108 ps
CPU time 16.69 seconds
Started Apr 28 12:42:09 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 216116 kb
Host smart-44f44fe0-0061-4a01-b610-fbb71d412d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393355801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1393355801
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.79301321
Short name T300
Test name
Test status
Simulation time 607254052 ps
CPU time 12.72 seconds
Started Apr 28 12:42:38 PM PDT 24
Finished Apr 28 12:42:51 PM PDT 24
Peak memory 222204 kb
Host smart-b2f9d8aa-6618-46f1-9ae2-fdb7c2081105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79301321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.79301321
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3790201539
Short name T407
Test name
Test status
Simulation time 157996862 ps
CPU time 8.52 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 215484 kb
Host smart-e5895167-5b2a-4893-9535-feec065bb425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790201539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3790201539
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1012075234
Short name T281
Test name
Test status
Simulation time 1493904731 ps
CPU time 13.48 seconds
Started Apr 28 12:43:22 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 215496 kb
Host smart-72660716-4116-46c1-b1a6-87861c4d6877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012075234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1012075234
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3499362377
Short name T368
Test name
Test status
Simulation time 116371503 ps
CPU time 4.52 seconds
Started Apr 28 12:43:50 PM PDT 24
Finished Apr 28 12:43:55 PM PDT 24
Peak memory 214144 kb
Host smart-9e71cee6-f314-49fb-a8ea-32f08b949c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499362377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3499362377
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.982633251
Short name T174
Test name
Test status
Simulation time 718194937 ps
CPU time 22.03 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 214244 kb
Host smart-0449872f-9ca4-4a03-8b32-1d6824cbde44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982633251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.982633251
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.551882085
Short name T163
Test name
Test status
Simulation time 756441304 ps
CPU time 6.05 seconds
Started Apr 28 12:40:08 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 209468 kb
Host smart-13c9fcd9-8fd7-46ba-92f3-ec157febf97e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551882085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.551882085
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2594153451
Short name T171
Test name
Test status
Simulation time 313034001 ps
CPU time 5.01 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 209508 kb
Host smart-80756d6c-c89e-42ab-997e-0fc7413f3021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594153451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2594153451
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.741036674
Short name T233
Test name
Test status
Simulation time 3546916741 ps
CPU time 24.95 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 215872 kb
Host smart-6ad1f7f7-111c-44a6-a48b-69b6280e0c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741036674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.741036674
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1908672625
Short name T253
Test name
Test status
Simulation time 950577402 ps
CPU time 7.37 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:43:01 PM PDT 24
Peak memory 210172 kb
Host smart-ef0dab47-eade-4870-a5e4-a9a0e4e1981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908672625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1908672625
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2911106881
Short name T51
Test name
Test status
Simulation time 432186860 ps
CPU time 5.82 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 220148 kb
Host smart-62101b03-6284-4409-8795-e2ac07d247a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911106881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2911106881
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.415563574
Short name T331
Test name
Test status
Simulation time 670298305 ps
CPU time 7.26 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 214836 kb
Host smart-ba2dd489-c139-4aa1-8ad7-d34ff2a67a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415563574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.415563574
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2205971432
Short name T240
Test name
Test status
Simulation time 2157301148 ps
CPU time 16.77 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 222252 kb
Host smart-b13a8da7-75af-4607-9a81-98bb1f172c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205971432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2205971432
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2169887291
Short name T366
Test name
Test status
Simulation time 34036098 ps
CPU time 2.04 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:31 PM PDT 24
Peak memory 209148 kb
Host smart-897a0d21-1936-4803-942f-0e811eaebc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169887291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2169887291
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1463481179
Short name T33
Test name
Test status
Simulation time 422221963 ps
CPU time 3.44 seconds
Started Apr 28 12:42:16 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 210036 kb
Host smart-b1ae3481-38cb-4550-b101-869baa49c87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463481179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1463481179
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.852391049
Short name T102
Test name
Test status
Simulation time 258123036 ps
CPU time 2.7 seconds
Started Apr 28 12:43:46 PM PDT 24
Finished Apr 28 12:43:49 PM PDT 24
Peak memory 210312 kb
Host smart-f7c8cf13-a5bb-49ed-91fa-0c4d0c247cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852391049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.852391049
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2569860399
Short name T155
Test name
Test status
Simulation time 101850751 ps
CPU time 4.77 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:25 PM PDT 24
Peak memory 217648 kb
Host smart-b0293b47-51b2-4e54-b03a-883c8d3a9816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569860399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2569860399
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3324409470
Short name T412
Test name
Test status
Simulation time 574625408 ps
CPU time 4.81 seconds
Started Apr 28 12:42:01 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 213972 kb
Host smart-c75a3ed2-9565-465f-bcaf-7a55dfe86076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324409470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3324409470
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3317190558
Short name T59
Test name
Test status
Simulation time 299785715 ps
CPU time 9.79 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 209464 kb
Host smart-8d183bf6-bd5b-47b6-8cfe-d271cb04c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317190558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3317190558
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.857529609
Short name T335
Test name
Test status
Simulation time 238986487 ps
CPU time 5.54 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:31 PM PDT 24
Peak memory 207848 kb
Host smart-5243d01b-e8eb-4efc-a907-47afad0641bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857529609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.857529609
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2050833331
Short name T63
Test name
Test status
Simulation time 81054607300 ps
CPU time 751.91 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:55:08 PM PDT 24
Peak memory 233716 kb
Host smart-c58384d1-a7a0-435b-9177-d00ed3375a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050833331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2050833331
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.492900508
Short name T62
Test name
Test status
Simulation time 2177246906 ps
CPU time 24.93 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 219412 kb
Host smart-49561317-543b-4675-b392-f8b4c128258f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492900508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.492900508
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1016791197
Short name T254
Test name
Test status
Simulation time 114543866 ps
CPU time 4.47 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 222112 kb
Host smart-1fc424d5-b2ed-448a-9907-f7b1b2610c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016791197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1016791197
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2371139703
Short name T709
Test name
Test status
Simulation time 239266622 ps
CPU time 3.9 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 207132 kb
Host smart-38ec567b-6f0a-4f45-b40d-3a9ccfa82d94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371139703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2371139703
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3065990433
Short name T178
Test name
Test status
Simulation time 1583546816 ps
CPU time 5.11 seconds
Started Apr 28 12:40:07 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 214212 kb
Host smart-eb1204f4-8e41-42d6-b080-36357367271a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065990433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3065990433
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3118399908
Short name T177
Test name
Test status
Simulation time 980701516 ps
CPU time 10.09 seconds
Started Apr 28 12:39:45 PM PDT 24
Finished Apr 28 12:39:55 PM PDT 24
Peak memory 209292 kb
Host smart-71ae22d4-9fb2-4bf8-8de3-8da7e80cd2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118399908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3118399908
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.735595125
Short name T160
Test name
Test status
Simulation time 213125774 ps
CPU time 2.68 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 210052 kb
Host smart-51d6c84b-0dab-46c9-ae8d-bc4b698d48ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735595125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.735595125
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.597490697
Short name T156
Test name
Test status
Simulation time 94762425 ps
CPU time 4.3 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 222536 kb
Host smart-5f0db9b3-42a9-4ff5-9045-ceaf72c66a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597490697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.597490697
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3577426182
Short name T860
Test name
Test status
Simulation time 1008477333 ps
CPU time 6.17 seconds
Started Apr 28 12:41:29 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 208464 kb
Host smart-f70bc1ac-1394-427a-8e99-f2177ce71708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577426182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3577426182
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1906492598
Short name T387
Test name
Test status
Simulation time 818054859 ps
CPU time 29.4 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 214648 kb
Host smart-3243ce99-10c2-4b39-beed-d7ad52855323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906492598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1906492598
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1070103439
Short name T270
Test name
Test status
Simulation time 93907626 ps
CPU time 4 seconds
Started Apr 28 12:42:08 PM PDT 24
Finished Apr 28 12:42:13 PM PDT 24
Peak memory 207020 kb
Host smart-fc1d3cdc-2464-4037-9c4f-4048810fff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070103439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1070103439
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1885340097
Short name T293
Test name
Test status
Simulation time 472437124 ps
CPU time 25.42 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 215044 kb
Host smart-b75be60d-571b-4f55-bbc9-5cd6569bb0c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885340097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1885340097
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2650308381
Short name T19
Test name
Test status
Simulation time 58467754 ps
CPU time 3.04 seconds
Started Apr 28 12:42:12 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 209192 kb
Host smart-444a9b03-6f27-4c2f-8ebc-f12f9f343ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650308381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2650308381
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_random.1832073952
Short name T286
Test name
Test status
Simulation time 531924977 ps
CPU time 5.72 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 213920 kb
Host smart-cdbe09b6-b10d-48b4-a4d4-2eac390d8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832073952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1832073952
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2005368911
Short name T229
Test name
Test status
Simulation time 149245472 ps
CPU time 5.1 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 214120 kb
Host smart-f6e34535-d63c-41d9-9682-c1c5bdbdd38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005368911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2005368911
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_random.1343347702
Short name T546
Test name
Test status
Simulation time 673331325 ps
CPU time 5.16 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 209140 kb
Host smart-09ede755-35ab-4c43-a414-9499730b19ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343347702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1343347702
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.4092430400
Short name T307
Test name
Test status
Simulation time 548221820 ps
CPU time 10.85 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 208876 kb
Host smart-74662356-3f69-4a49-a349-55f699635e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092430400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.4092430400
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1412208517
Short name T430
Test name
Test status
Simulation time 61882351 ps
CPU time 4.31 seconds
Started Apr 28 12:42:26 PM PDT 24
Finished Apr 28 12:42:31 PM PDT 24
Peak memory 214424 kb
Host smart-26478e09-04ed-4e17-aa7d-c459770ef769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412208517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1412208517
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2097330130
Short name T276
Test name
Test status
Simulation time 273232806 ps
CPU time 7.62 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:59 PM PDT 24
Peak memory 214076 kb
Host smart-7050b795-b4ea-42f6-8b89-7d6795501bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097330130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2097330130
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.979040004
Short name T239
Test name
Test status
Simulation time 6498188733 ps
CPU time 49.72 seconds
Started Apr 28 12:42:24 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 222400 kb
Host smart-16839f75-e5c3-4192-8861-6413ce3580ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979040004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.979040004
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2072609604
Short name T282
Test name
Test status
Simulation time 437300571 ps
CPU time 2.88 seconds
Started Apr 28 12:42:37 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 217876 kb
Host smart-8901b244-adea-47e9-8782-ea2a8e9d4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072609604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2072609604
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4256788703
Short name T386
Test name
Test status
Simulation time 133404120 ps
CPU time 6.49 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 215092 kb
Host smart-21df682f-3fdd-46eb-927a-daeca5e7ccbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256788703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4256788703
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2889628187
Short name T346
Test name
Test status
Simulation time 180431874 ps
CPU time 4.42 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:42:50 PM PDT 24
Peak memory 213948 kb
Host smart-617573dd-0a42-417f-9e67-4843bb3548e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889628187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2889628187
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2369208586
Short name T24
Test name
Test status
Simulation time 257512056 ps
CPU time 4.2 seconds
Started Apr 28 12:42:53 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 214040 kb
Host smart-c48f7919-3be3-4c15-b77b-82422e51c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369208586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2369208586
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3162806629
Short name T243
Test name
Test status
Simulation time 1950548449 ps
CPU time 22 seconds
Started Apr 28 12:43:20 PM PDT 24
Finished Apr 28 12:43:42 PM PDT 24
Peak memory 216160 kb
Host smart-b6010ca0-b7a8-4dd4-89f8-1092af3b146e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162806629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3162806629
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3736550904
Short name T255
Test name
Test status
Simulation time 121067357 ps
CPU time 5.34 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 213972 kb
Host smart-ecc37cc1-7514-4182-b6ee-3e5f1d7a4467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736550904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3736550904
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1287983806
Short name T321
Test name
Test status
Simulation time 99165389 ps
CPU time 4.83 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 209288 kb
Host smart-890722c7-d2fb-4e00-94f6-d40426a6aae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287983806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1287983806
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.4141068090
Short name T378
Test name
Test status
Simulation time 397772960 ps
CPU time 4.23 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 213968 kb
Host smart-04e919ee-7161-4a03-a19f-63ebb371f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141068090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.4141068090
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1589445022
Short name T146
Test name
Test status
Simulation time 723454156 ps
CPU time 13.59 seconds
Started Apr 28 12:39:43 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 205856 kb
Host smart-3b2b0c80-74da-45e2-8fa2-48f5fe4c3d14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589445022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
589445022
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1865874727
Short name T979
Test name
Test status
Simulation time 3575185575 ps
CPU time 27.83 seconds
Started Apr 28 12:39:42 PM PDT 24
Finished Apr 28 12:40:11 PM PDT 24
Peak memory 206032 kb
Host smart-0a3bb39a-8fc2-4f5b-a7ff-3cb4ec513cb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865874727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
865874727
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2343731018
Short name T913
Test name
Test status
Simulation time 71133849 ps
CPU time 1.08 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 205984 kb
Host smart-f7a552be-d121-4f5d-b54e-c683f4b58c7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343731018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
343731018
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3688610409
Short name T922
Test name
Test status
Simulation time 69537518 ps
CPU time 1.66 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 217432 kb
Host smart-6d7dc0d2-9bdf-443b-8e76-f1159fbbe3fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688610409 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3688610409
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1700633050
Short name T404
Test name
Test status
Simulation time 61700237 ps
CPU time 1.13 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 205904 kb
Host smart-cb982e4f-e63d-48c6-989e-1f0bc603d1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700633050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1700633050
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3643614411
Short name T924
Test name
Test status
Simulation time 10524806 ps
CPU time 0.81 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:01 PM PDT 24
Peak memory 205636 kb
Host smart-09134065-88d6-449c-b0ae-4d176adfc0c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643614411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3643614411
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1001240484
Short name T985
Test name
Test status
Simulation time 295354864 ps
CPU time 2.38 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 206060 kb
Host smart-ade35ec6-a050-4886-956d-ff79175a5a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001240484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1001240484
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2104824731
Short name T209
Test name
Test status
Simulation time 418306533 ps
CPU time 6.84 seconds
Started Apr 28 12:39:42 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 222724 kb
Host smart-3989c6a3-3fa6-44b5-a647-7ca85a1cfbf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104824731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2104824731
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.324445400
Short name T962
Test name
Test status
Simulation time 151602087 ps
CPU time 2.27 seconds
Started Apr 28 12:39:40 PM PDT 24
Finished Apr 28 12:39:43 PM PDT 24
Peak memory 205992 kb
Host smart-506f7414-0e95-4296-8ff5-fddfa14ed472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324445400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.324445400
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2063258047
Short name T184
Test name
Test status
Simulation time 190886233 ps
CPU time 6.11 seconds
Started Apr 28 12:39:43 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 214108 kb
Host smart-ccfa90c4-bfae-43af-8210-8cf18304a7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063258047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2063258047
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1489847949
Short name T1047
Test name
Test status
Simulation time 184692309 ps
CPU time 4.92 seconds
Started Apr 28 12:39:37 PM PDT 24
Finished Apr 28 12:39:43 PM PDT 24
Peak memory 206044 kb
Host smart-5472ad6f-1cef-4e38-a227-3bc33dba146d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489847949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
489847949
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2510255200
Short name T1026
Test name
Test status
Simulation time 1756033141 ps
CPU time 25.51 seconds
Started Apr 28 12:39:37 PM PDT 24
Finished Apr 28 12:40:03 PM PDT 24
Peak memory 205920 kb
Host smart-8fb6cc36-1bf4-40e2-96f6-e32e4d5703d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510255200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
510255200
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.576109630
Short name T1032
Test name
Test status
Simulation time 54524967 ps
CPU time 0.88 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 205912 kb
Host smart-f78d9ce4-74e0-4f8f-91d9-7590fbf3e071
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576109630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.576109630
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2724843069
Short name T933
Test name
Test status
Simulation time 223241700 ps
CPU time 2.34 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:55 PM PDT 24
Peak memory 205948 kb
Host smart-9f31b27b-b3c2-48e0-809f-eb7f4eefe4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724843069 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2724843069
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.423731326
Short name T923
Test name
Test status
Simulation time 13367890 ps
CPU time 1.06 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 206096 kb
Host smart-486dad67-cb2d-4715-b281-00926511d55d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423731326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.423731326
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4118568303
Short name T1016
Test name
Test status
Simulation time 11288886 ps
CPU time 0.82 seconds
Started Apr 28 12:39:46 PM PDT 24
Finished Apr 28 12:39:47 PM PDT 24
Peak memory 205748 kb
Host smart-f94e58ad-11ce-4ded-ba1f-66bab61e6d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118568303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4118568303
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1278453938
Short name T149
Test name
Test status
Simulation time 320545890 ps
CPU time 2.76 seconds
Started Apr 28 12:39:40 PM PDT 24
Finished Apr 28 12:39:44 PM PDT 24
Peak memory 206028 kb
Host smart-155f0d67-e42f-4565-b420-a610833b51ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278453938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1278453938
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1869322056
Short name T110
Test name
Test status
Simulation time 316494828 ps
CPU time 2.74 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 222604 kb
Host smart-4f77b18b-98b3-4730-b649-341aedf5bbe5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869322056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1869322056
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2588863174
Short name T1019
Test name
Test status
Simulation time 81328241 ps
CPU time 3.57 seconds
Started Apr 28 12:39:51 PM PDT 24
Finished Apr 28 12:39:55 PM PDT 24
Peak memory 220520 kb
Host smart-244ed060-d45e-4242-808f-1acd8d89aa97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588863174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2588863174
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1118741841
Short name T906
Test name
Test status
Simulation time 23897775 ps
CPU time 1.39 seconds
Started Apr 28 12:39:45 PM PDT 24
Finished Apr 28 12:39:47 PM PDT 24
Peak memory 206208 kb
Host smart-041c2e1a-7ab3-4f4b-a73c-980410a328c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118741841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1118741841
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.127570956
Short name T964
Test name
Test status
Simulation time 1645559899 ps
CPU time 9.38 seconds
Started Apr 28 12:39:46 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 214180 kb
Host smart-4d0f26e9-9ae5-45ef-80a2-02e1a5c6f68c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127570956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
127570956
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.478314617
Short name T938
Test name
Test status
Simulation time 77652850 ps
CPU time 1.3 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 214236 kb
Host smart-fe81a6b0-148f-453e-a99a-1b956184afd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478314617 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.478314617
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3250601635
Short name T1058
Test name
Test status
Simulation time 54101212 ps
CPU time 1.21 seconds
Started Apr 28 12:40:00 PM PDT 24
Finished Apr 28 12:40:02 PM PDT 24
Peak memory 205828 kb
Host smart-3d53b037-f9ca-4b43-a222-9df0d4bbf792
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250601635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3250601635
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4222347657
Short name T984
Test name
Test status
Simulation time 15377616 ps
CPU time 0.77 seconds
Started Apr 28 12:40:20 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 205752 kb
Host smart-6edb5274-d047-4e6c-b82e-cef1b8ee2a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222347657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4222347657
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.960572270
Short name T152
Test name
Test status
Simulation time 23257126 ps
CPU time 1.72 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 206020 kb
Host smart-911208c4-5aff-4b04-9da5-9079f371b154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960572270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.960572270
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3374696847
Short name T975
Test name
Test status
Simulation time 596150146 ps
CPU time 12.25 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:40:07 PM PDT 24
Peak memory 214488 kb
Host smart-b36bd927-9ebe-4290-8206-504749482d3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374696847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3374696847
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.759076073
Short name T1004
Test name
Test status
Simulation time 377473883 ps
CPU time 8.81 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:09 PM PDT 24
Peak memory 214516 kb
Host smart-2496a80f-b3ed-43dd-8130-486b7fa1f937
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759076073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.759076073
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2700240349
Short name T1046
Test name
Test status
Simulation time 30361047 ps
CPU time 1.89 seconds
Started Apr 28 12:39:42 PM PDT 24
Finished Apr 28 12:39:45 PM PDT 24
Peak memory 214288 kb
Host smart-db676a72-77f6-481b-bf2b-5d9edb73fd97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700240349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2700240349
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2072003535
Short name T909
Test name
Test status
Simulation time 21460566 ps
CPU time 1.76 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 214348 kb
Host smart-4640a21e-82d0-4094-b45d-7db039f9e8b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072003535 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2072003535
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4189273892
Short name T995
Test name
Test status
Simulation time 28518196 ps
CPU time 1.62 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:53 PM PDT 24
Peak memory 205968 kb
Host smart-9ad0f913-d3f7-4f4f-af2f-5387a682884b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189273892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4189273892
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2743486037
Short name T1033
Test name
Test status
Simulation time 19578196 ps
CPU time 0.81 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 205712 kb
Host smart-bc8bbf4a-96e6-4acd-9785-b3abaa051c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743486037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2743486037
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4281976216
Short name T1020
Test name
Test status
Simulation time 85695721 ps
CPU time 1.71 seconds
Started Apr 28 12:40:00 PM PDT 24
Finished Apr 28 12:40:02 PM PDT 24
Peak memory 214232 kb
Host smart-a75502a9-2b82-4b1c-a6e6-02e8b8de6279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281976216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.4281976216
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4128831181
Short name T957
Test name
Test status
Simulation time 767968188 ps
CPU time 4 seconds
Started Apr 28 12:40:03 PM PDT 24
Finished Apr 28 12:40:09 PM PDT 24
Peak memory 214548 kb
Host smart-8f532bf4-692d-41c0-8dc5-ebeabe85f1d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128831181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4128831181
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1220611980
Short name T105
Test name
Test status
Simulation time 370031721 ps
CPU time 7.12 seconds
Started Apr 28 12:40:02 PM PDT 24
Finished Apr 28 12:40:11 PM PDT 24
Peak memory 214620 kb
Host smart-fd488cf8-3f80-408f-8703-23e001fb8a3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220611980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1220611980
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.79386903
Short name T208
Test name
Test status
Simulation time 811149792 ps
CPU time 2.78 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 215412 kb
Host smart-19ccf25a-62f4-4cac-9d0c-5b71e8cdc6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79386903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.79386903
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4210056467
Short name T172
Test name
Test status
Simulation time 242971649 ps
CPU time 6.36 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 209332 kb
Host smart-be81c6e1-73b8-4661-8a8d-0bb64b42dff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210056467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4210056467
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.384077720
Short name T998
Test name
Test status
Simulation time 91364790 ps
CPU time 1.8 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:21 PM PDT 24
Peak memory 205964 kb
Host smart-268d8c47-3159-4b73-b796-68f715643df8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384077720 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.384077720
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.997895679
Short name T961
Test name
Test status
Simulation time 36309807 ps
CPU time 1 seconds
Started Apr 28 12:40:06 PM PDT 24
Finished Apr 28 12:40:08 PM PDT 24
Peak memory 205684 kb
Host smart-bb60a2b4-83d6-44e1-94f6-e6d1a35cf837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997895679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.997895679
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1425238993
Short name T910
Test name
Test status
Simulation time 10790218 ps
CPU time 0.7 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:55 PM PDT 24
Peak memory 205736 kb
Host smart-9a5c84f7-8d35-45fa-991a-82a51359b220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425238993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1425238993
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.678117488
Short name T145
Test name
Test status
Simulation time 82269489 ps
CPU time 2.53 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 206028 kb
Host smart-e8a59788-9809-48e3-9179-3a9468733b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678117488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.678117488
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3417094823
Short name T1010
Test name
Test status
Simulation time 178098769 ps
CPU time 2.55 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 214544 kb
Host smart-3899c399-60b2-4cfc-ad21-8d882a64d14f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417094823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3417094823
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.43319671
Short name T1024
Test name
Test status
Simulation time 444518441 ps
CPU time 14.88 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:18 PM PDT 24
Peak memory 220552 kb
Host smart-05f9be73-52c7-41d6-ab74-53365b88ffb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43319671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.k
eymgr_shadow_reg_errors_with_csr_rw.43319671
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3080279545
Short name T970
Test name
Test status
Simulation time 150265461 ps
CPU time 2.95 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 217388 kb
Host smart-0fb341c4-3c70-4dfe-936d-ac444744cab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080279545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3080279545
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1530080434
Short name T972
Test name
Test status
Simulation time 88757175 ps
CPU time 1.11 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 206068 kb
Host smart-36f319a7-b70c-4151-83cf-962ad2c432b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530080434 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1530080434
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4230056011
Short name T1009
Test name
Test status
Simulation time 24165825 ps
CPU time 1.23 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 205904 kb
Host smart-1ce32d8c-35b0-44e7-a36f-493afa8b701f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230056011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4230056011
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2297767976
Short name T1035
Test name
Test status
Simulation time 14735697 ps
CPU time 0.73 seconds
Started Apr 28 12:39:57 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 205680 kb
Host smart-ab3b7c26-bc8a-4d2d-ba2e-03d1b5ac99af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297767976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2297767976
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2592238785
Short name T1021
Test name
Test status
Simulation time 149002195 ps
CPU time 2.77 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 206148 kb
Host smart-2b39c8a2-ece2-4812-8713-d0ef68a7e61a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592238785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2592238785
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.695379516
Short name T937
Test name
Test status
Simulation time 556204760 ps
CPU time 16.47 seconds
Started Apr 28 12:40:05 PM PDT 24
Finished Apr 28 12:40:23 PM PDT 24
Peak memory 215552 kb
Host smart-03d160c5-274f-4f57-8d6d-cc90a5a3e640
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695379516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.695379516
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.707878279
Short name T925
Test name
Test status
Simulation time 87956717 ps
CPU time 1.51 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 214200 kb
Host smart-eab40606-4b7f-42e1-9ce3-5de9f56f04a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707878279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.707878279
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.159034735
Short name T935
Test name
Test status
Simulation time 275886533 ps
CPU time 4.37 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:07 PM PDT 24
Peak memory 209168 kb
Host smart-7736099b-fe3a-4c72-80c9-1d8b28600c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159034735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.159034735
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2776582699
Short name T966
Test name
Test status
Simulation time 223190216 ps
CPU time 2.49 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 214248 kb
Host smart-dab2c6fe-57d6-4e21-b7c3-63c2d0476871
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776582699 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2776582699
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.488810274
Short name T1049
Test name
Test status
Simulation time 35673104 ps
CPU time 0.93 seconds
Started Apr 28 12:39:46 PM PDT 24
Finished Apr 28 12:39:47 PM PDT 24
Peak memory 205732 kb
Host smart-b8bbf061-5da2-4f76-a1cc-6ede36cb8828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488810274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.488810274
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3418100441
Short name T947
Test name
Test status
Simulation time 52462282 ps
CPU time 0.8 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205736 kb
Host smart-2a2d5b8d-3288-4304-bd48-757c92721c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418100441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3418100441
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.765389931
Short name T969
Test name
Test status
Simulation time 32024490 ps
CPU time 2.01 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 206056 kb
Host smart-47ff565a-cad4-4446-9c98-c86fa44ab446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765389931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.765389931
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2106180088
Short name T991
Test name
Test status
Simulation time 75249176 ps
CPU time 1.89 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 214600 kb
Host smart-70440428-e60f-4b11-99b8-170b81379b45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106180088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2106180088
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2083231861
Short name T943
Test name
Test status
Simulation time 77060492 ps
CPU time 3.92 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 214596 kb
Host smart-2600180b-a48b-49c4-bac9-27b357c93e82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083231861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2083231861
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2265915479
Short name T1059
Test name
Test status
Simulation time 543329939 ps
CPU time 5.15 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 217484 kb
Host smart-602358de-799f-4589-af57-598298460cf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265915479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2265915479
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.545465885
Short name T1029
Test name
Test status
Simulation time 27480174 ps
CPU time 1.49 seconds
Started Apr 28 12:40:02 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 214420 kb
Host smart-fb661ea8-e014-4407-b99a-1f7716266ad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545465885 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.545465885
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4156896003
Short name T917
Test name
Test status
Simulation time 11618579 ps
CPU time 0.99 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 205748 kb
Host smart-0aafd132-3864-4555-8b15-ca78e7728d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156896003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4156896003
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1952593349
Short name T1013
Test name
Test status
Simulation time 48188255 ps
CPU time 0.87 seconds
Started Apr 28 12:39:58 PM PDT 24
Finished Apr 28 12:40:00 PM PDT 24
Peak memory 205748 kb
Host smart-0653d5b8-4314-4150-9430-0056042b4660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952593349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1952593349
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1579811371
Short name T187
Test name
Test status
Simulation time 91473529 ps
CPU time 2.41 seconds
Started Apr 28 12:40:07 PM PDT 24
Finished Apr 28 12:40:11 PM PDT 24
Peak memory 205964 kb
Host smart-decb0bae-4198-4c11-aa41-61388411bc42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579811371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1579811371
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1673190496
Short name T113
Test name
Test status
Simulation time 112304374 ps
CPU time 3.01 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 214468 kb
Host smart-d5bf6276-fa25-4821-aa54-ea7994312165
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673190496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1673190496
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1136677022
Short name T946
Test name
Test status
Simulation time 170569452 ps
CPU time 7.48 seconds
Started Apr 28 12:39:44 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 220688 kb
Host smart-cc536461-f15c-4ec4-a244-462be593d56c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136677022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1136677022
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4267985633
Short name T1023
Test name
Test status
Simulation time 67368907 ps
CPU time 1.56 seconds
Started Apr 28 12:40:02 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 216276 kb
Host smart-ecd056b5-a531-4033-a69f-1c0a288d65e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267985633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4267985633
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1783165047
Short name T1040
Test name
Test status
Simulation time 181180664 ps
CPU time 4.69 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 209684 kb
Host smart-a3d711a1-0b82-4b4f-87fe-58be5d40ddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783165047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1783165047
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2160332370
Short name T1022
Test name
Test status
Simulation time 208601001 ps
CPU time 1.62 seconds
Started Apr 28 12:40:13 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 214352 kb
Host smart-4789a893-a23c-44ff-b806-660554db2e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160332370 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2160332370
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4147555623
Short name T151
Test name
Test status
Simulation time 20246139 ps
CPU time 1.28 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 206060 kb
Host smart-e892b410-2700-4dfb-9eef-9db1d4aded06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147555623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4147555623
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1512011676
Short name T994
Test name
Test status
Simulation time 25983349 ps
CPU time 1.04 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 205908 kb
Host smart-9630cb60-bca4-4bf4-ae42-22bad8b37489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512011676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1512011676
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1613629112
Short name T188
Test name
Test status
Simulation time 66018982 ps
CPU time 1.7 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 205932 kb
Host smart-9eaa79ef-68fc-46a1-ba81-1234e7ca2cf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613629112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1613629112
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2279974963
Short name T111
Test name
Test status
Simulation time 117855380 ps
CPU time 4.48 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:40:01 PM PDT 24
Peak memory 214480 kb
Host smart-61df114f-d83e-4dd8-86d2-35b88a8c1a66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279974963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2279974963
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3060533035
Short name T1045
Test name
Test status
Simulation time 327302398 ps
CPU time 6.63 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 214628 kb
Host smart-37c6ac1c-25c6-4d24-926d-ede56fd9d4ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060533035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3060533035
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3190472017
Short name T908
Test name
Test status
Simulation time 613543261 ps
CPU time 2.79 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 214224 kb
Host smart-0fa4798a-6d90-48a7-ab6b-ce865e5bf40f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190472017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3190472017
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3051383466
Short name T165
Test name
Test status
Simulation time 25461476025 ps
CPU time 135.72 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:42:10 PM PDT 24
Peak memory 224000 kb
Host smart-f0fe83bd-4ea4-4881-99b0-fba7ed4dc2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051383466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3051383466
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2725890643
Short name T1064
Test name
Test status
Simulation time 321635763 ps
CPU time 1.24 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 214304 kb
Host smart-487196da-fe90-4cd0-a93b-4d35859d8cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725890643 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2725890643
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1451240150
Short name T1012
Test name
Test status
Simulation time 14218026 ps
CPU time 1.07 seconds
Started Apr 28 12:40:02 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 205936 kb
Host smart-0e068cf0-544f-4044-b610-1c5b23070029
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451240150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1451240150
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1085531213
Short name T977
Test name
Test status
Simulation time 14267051 ps
CPU time 0.87 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 205848 kb
Host smart-e629c2c8-b580-486a-acb5-a91ec4ded0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085531213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1085531213
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.474294162
Short name T955
Test name
Test status
Simulation time 1058592380 ps
CPU time 1.9 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 206100 kb
Host smart-93bccf4c-5d29-4cce-8b37-383905b3e85a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474294162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.474294162
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1131549514
Short name T1061
Test name
Test status
Simulation time 987229565 ps
CPU time 5.84 seconds
Started Apr 28 12:40:02 PM PDT 24
Finished Apr 28 12:40:10 PM PDT 24
Peak memory 214544 kb
Host smart-b9b2515c-b6be-4cfc-80c9-7923d29c1f27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131549514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1131549514
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.517412064
Short name T963
Test name
Test status
Simulation time 280041181 ps
CPU time 7.71 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:11 PM PDT 24
Peak memory 222704 kb
Host smart-f5603785-37d7-4c8c-bc78-3df2f8ef4016
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517412064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.517412064
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2785185840
Short name T918
Test name
Test status
Simulation time 172873608 ps
CPU time 3.11 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 214216 kb
Host smart-fd3c8b1f-06cb-4548-b64d-ff4028883cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785185840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2785185840
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2146408825
Short name T180
Test name
Test status
Simulation time 1417214770 ps
CPU time 39.04 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:40:30 PM PDT 24
Peak memory 214196 kb
Host smart-e5e58145-77d8-4a5c-a63c-c5c351cb9808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146408825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2146408825
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2628208186
Short name T929
Test name
Test status
Simulation time 42731594 ps
CPU time 1.71 seconds
Started Apr 28 12:40:07 PM PDT 24
Finished Apr 28 12:40:09 PM PDT 24
Peak memory 219528 kb
Host smart-85586651-8fa2-4440-bca4-8ff5c270786d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628208186 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2628208186
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3955135928
Short name T1025
Test name
Test status
Simulation time 29291708 ps
CPU time 1.01 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:34 PM PDT 24
Peak memory 205800 kb
Host smart-81d1312c-8ff8-4192-9b8d-742975cc72c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955135928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3955135928
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1354494275
Short name T973
Test name
Test status
Simulation time 104918881 ps
CPU time 0.81 seconds
Started Apr 28 12:40:00 PM PDT 24
Finished Apr 28 12:40:03 PM PDT 24
Peak memory 205824 kb
Host smart-fbd35b58-6ef4-4632-a80f-906efc46f35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354494275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1354494275
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1773297363
Short name T150
Test name
Test status
Simulation time 35676962 ps
CPU time 2.47 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205936 kb
Host smart-b71b2ff3-6e39-402a-83c8-4a04d7bd005d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773297363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1773297363
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2974332589
Short name T939
Test name
Test status
Simulation time 64588472 ps
CPU time 1.71 seconds
Started Apr 28 12:40:00 PM PDT 24
Finished Apr 28 12:40:02 PM PDT 24
Peak memory 219116 kb
Host smart-b38be5a8-ea9d-40ec-a63f-f208f1a8f548
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974332589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2974332589
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1578084333
Short name T988
Test name
Test status
Simulation time 2465280043 ps
CPU time 9.29 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:40:08 PM PDT 24
Peak memory 213864 kb
Host smart-15d9730e-d5ba-474e-ab65-797155ba840e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578084333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1578084333
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2908090979
Short name T1011
Test name
Test status
Simulation time 96491299 ps
CPU time 1.5 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:18 PM PDT 24
Peak memory 214164 kb
Host smart-0c98dc88-6e36-4b5d-a275-5b385e817584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908090979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2908090979
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1606910395
Short name T411
Test name
Test status
Simulation time 24874251 ps
CPU time 1.57 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:54 PM PDT 24
Peak memory 214372 kb
Host smart-fb98f0d4-42ba-45d2-aa05-1d73a24a8784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606910395 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1606910395
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2860062494
Short name T1053
Test name
Test status
Simulation time 11065986 ps
CPU time 0.88 seconds
Started Apr 28 12:39:46 PM PDT 24
Finished Apr 28 12:39:48 PM PDT 24
Peak memory 205716 kb
Host smart-d79d7093-9622-47c3-85b7-b42b64b635d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860062494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2860062494
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3467431752
Short name T993
Test name
Test status
Simulation time 138434614 ps
CPU time 0.75 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 205568 kb
Host smart-99343b6f-8e18-4890-a584-8f811c88802d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467431752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3467431752
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.437337899
Short name T1001
Test name
Test status
Simulation time 21723698 ps
CPU time 1.35 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:24 PM PDT 24
Peak memory 206124 kb
Host smart-76a641af-b7aa-4391-9d34-2ef3d06c70ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437337899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.437337899
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2915662666
Short name T114
Test name
Test status
Simulation time 2103816574 ps
CPU time 3.68 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:15 PM PDT 24
Peak memory 222544 kb
Host smart-dfd667ff-ea18-4253-ba4e-062fbb9afb62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915662666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2915662666
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2508096245
Short name T1015
Test name
Test status
Simulation time 1386294970 ps
CPU time 9.48 seconds
Started Apr 28 12:40:05 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 214640 kb
Host smart-0c5114f9-2e27-4b99-a873-0680b42b2cd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508096245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2508096245
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2204017762
Short name T912
Test name
Test status
Simulation time 64721069 ps
CPU time 3.18 seconds
Started Apr 28 12:40:00 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 214300 kb
Host smart-ac363eb7-959f-4fb8-a80d-e5b4f9100db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204017762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2204017762
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3381863153
Short name T919
Test name
Test status
Simulation time 187124730 ps
CPU time 5.08 seconds
Started Apr 28 12:39:46 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 205964 kb
Host smart-37374829-fb6e-444c-bfd8-080ad17c8026
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381863153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
381863153
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.380575335
Short name T950
Test name
Test status
Simulation time 5353507634 ps
CPU time 17.78 seconds
Started Apr 28 12:39:45 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 206096 kb
Host smart-7785b323-b8c9-4dd1-a088-14c906af0d12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380575335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.380575335
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4032119025
Short name T189
Test name
Test status
Simulation time 120257420 ps
CPU time 1.22 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 205988 kb
Host smart-123cbf2f-5ad4-4adc-8879-05b59439bde6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032119025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
032119025
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.973125500
Short name T403
Test name
Test status
Simulation time 170230447 ps
CPU time 2.08 seconds
Started Apr 28 12:39:44 PM PDT 24
Finished Apr 28 12:39:47 PM PDT 24
Peak memory 214404 kb
Host smart-58aeaeb0-f394-4025-9b21-64ec3af27e1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973125500 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.973125500
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3810121159
Short name T980
Test name
Test status
Simulation time 15155999 ps
CPU time 1.25 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 206048 kb
Host smart-6f210787-8fde-4510-9859-a62b97903e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810121159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3810121159
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2568498658
Short name T1037
Test name
Test status
Simulation time 70541391 ps
CPU time 0.79 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:40:07 PM PDT 24
Peak memory 205780 kb
Host smart-8a030774-37d9-4bca-8ac2-44dd7fd00aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568498658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2568498658
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4281387668
Short name T978
Test name
Test status
Simulation time 99713140 ps
CPU time 1.74 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 206028 kb
Host smart-4c824939-9ab7-4928-9e98-a8d64e570868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281387668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.4281387668
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3071350570
Short name T1041
Test name
Test status
Simulation time 372730536 ps
CPU time 4.04 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 214516 kb
Host smart-492f6bed-4e22-44c6-a900-1c6b7e00c2be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071350570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3071350570
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3446465059
Short name T112
Test name
Test status
Simulation time 205267277 ps
CPU time 7.8 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 214524 kb
Host smart-71fbe768-911d-44d0-aa88-1f85789ac9a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446465059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3446465059
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.518449922
Short name T1034
Test name
Test status
Simulation time 249063935 ps
CPU time 2.72 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 216368 kb
Host smart-e105e7b6-80c3-4b7a-917d-15adc8c8aa4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518449922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.518449922
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.763526310
Short name T941
Test name
Test status
Simulation time 11298604 ps
CPU time 0.72 seconds
Started Apr 28 12:40:22 PM PDT 24
Finished Apr 28 12:40:24 PM PDT 24
Peak memory 205764 kb
Host smart-ef2ff9e0-2e00-4f72-8ed6-58598d82ef66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763526310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.763526310
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1970123794
Short name T942
Test name
Test status
Simulation time 13075824 ps
CPU time 0.73 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:18 PM PDT 24
Peak memory 205760 kb
Host smart-3f51b2d6-dfa1-4aba-a519-92b73c545a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970123794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1970123794
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1568274647
Short name T930
Test name
Test status
Simulation time 20481629 ps
CPU time 0.82 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205704 kb
Host smart-c12e436b-e557-4b72-9b16-31fedafb689a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568274647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1568274647
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.354922682
Short name T958
Test name
Test status
Simulation time 41454444 ps
CPU time 0.8 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 205692 kb
Host smart-e9529e1d-c294-4b9c-94dc-107972550a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354922682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.354922682
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2384054541
Short name T949
Test name
Test status
Simulation time 71906235 ps
CPU time 0.71 seconds
Started Apr 28 12:40:05 PM PDT 24
Finished Apr 28 12:40:07 PM PDT 24
Peak memory 205772 kb
Host smart-5ef02474-a153-4781-8b6f-7885cab5c37d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384054541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2384054541
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2975478048
Short name T960
Test name
Test status
Simulation time 11451345 ps
CPU time 0.84 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205772 kb
Host smart-b9a6f058-a5ef-426c-b480-2bda8a6c006e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975478048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2975478048
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1379708649
Short name T1056
Test name
Test status
Simulation time 85580002 ps
CPU time 0.85 seconds
Started Apr 28 12:40:18 PM PDT 24
Finished Apr 28 12:40:21 PM PDT 24
Peak memory 205852 kb
Host smart-fe9fe637-0950-48e7-b716-1a04b185b8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379708649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1379708649
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.654756283
Short name T1054
Test name
Test status
Simulation time 58994927 ps
CPU time 0.83 seconds
Started Apr 28 12:40:07 PM PDT 24
Finished Apr 28 12:40:10 PM PDT 24
Peak memory 205748 kb
Host smart-44e07c13-6405-48b8-ac48-540c9813c9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654756283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.654756283
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2189487852
Short name T921
Test name
Test status
Simulation time 13346885 ps
CPU time 0.72 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:55 PM PDT 24
Peak memory 205744 kb
Host smart-26557791-6f1b-4089-a644-750370b2e9af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189487852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2189487852
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.845317057
Short name T1017
Test name
Test status
Simulation time 14348997 ps
CPU time 0.79 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:40:59 PM PDT 24
Peak memory 205716 kb
Host smart-6e51ee8b-8847-4274-9a07-1d09580e0d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845317057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.845317057
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1322922942
Short name T996
Test name
Test status
Simulation time 70559904 ps
CPU time 4.95 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 205992 kb
Host smart-ba564966-2978-4b94-be92-2881436ee7a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322922942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
322922942
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3805995725
Short name T1048
Test name
Test status
Simulation time 3611790918 ps
CPU time 17.55 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 206108 kb
Host smart-6effcd43-4d54-400e-b6dd-2e20065c2b83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805995725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
805995725
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4096868319
Short name T1002
Test name
Test status
Simulation time 132792079 ps
CPU time 1.45 seconds
Started Apr 28 12:39:48 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 205948 kb
Host smart-2af89a80-30a0-4fe8-9f9f-a79b2e7452d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096868319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
096868319
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3128569328
Short name T162
Test name
Test status
Simulation time 29253126 ps
CPU time 1.16 seconds
Started Apr 28 12:39:42 PM PDT 24
Finished Apr 28 12:39:44 PM PDT 24
Peak memory 206012 kb
Host smart-fd4c2f96-2795-4370-b038-2486ec3dc1be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128569328 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3128569328
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3800655714
Short name T982
Test name
Test status
Simulation time 39223684 ps
CPU time 0.98 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 205816 kb
Host smart-8e9016aa-0e27-4805-b419-f46e21b663cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800655714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3800655714
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1769884356
Short name T936
Test name
Test status
Simulation time 24037220 ps
CPU time 0.77 seconds
Started Apr 28 12:39:43 PM PDT 24
Finished Apr 28 12:39:45 PM PDT 24
Peak memory 205672 kb
Host smart-920f33af-546d-4beb-9f2b-79c89fea5ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769884356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1769884356
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2088096778
Short name T974
Test name
Test status
Simulation time 756790854 ps
CPU time 2.65 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 206108 kb
Host smart-efeffd81-704e-4d0b-8f91-27707baedd41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088096778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2088096778
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2228853876
Short name T959
Test name
Test status
Simulation time 536544038 ps
CPU time 2.5 seconds
Started Apr 28 12:39:40 PM PDT 24
Finished Apr 28 12:39:43 PM PDT 24
Peak memory 219048 kb
Host smart-1c0c72c1-2bac-420b-a1c4-c7e6c5e29ef2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228853876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2228853876
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3664392292
Short name T940
Test name
Test status
Simulation time 347960818 ps
CPU time 3.99 seconds
Started Apr 28 12:39:42 PM PDT 24
Finished Apr 28 12:39:46 PM PDT 24
Peak memory 214076 kb
Host smart-f73caef1-a72b-4498-b74a-3ebb90c4e983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664392292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3664392292
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.748017824
Short name T976
Test name
Test status
Simulation time 158551284 ps
CPU time 3.06 seconds
Started Apr 28 12:39:41 PM PDT 24
Finished Apr 28 12:39:44 PM PDT 24
Peak memory 214260 kb
Host smart-53c08a8f-2435-4051-9e9b-eea1ff6bd961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748017824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.748017824
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3484204855
Short name T920
Test name
Test status
Simulation time 31607928 ps
CPU time 0.7 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:12 PM PDT 24
Peak memory 205692 kb
Host smart-c9033f67-7d22-43cb-be0c-f1e854cd878f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484204855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3484204855
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.19608997
Short name T1062
Test name
Test status
Simulation time 21283602 ps
CPU time 0.83 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205756 kb
Host smart-53172785-8eb5-4a06-99ec-e24f8f12a0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.19608997
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3378388069
Short name T907
Test name
Test status
Simulation time 9767863 ps
CPU time 0.83 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:12 PM PDT 24
Peak memory 205736 kb
Host smart-687333c1-a5e4-4cdb-94b7-2c35f7f3cd7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378388069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3378388069
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3235146333
Short name T926
Test name
Test status
Simulation time 22296204 ps
CPU time 0.74 seconds
Started Apr 28 12:40:20 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 205744 kb
Host smart-ada6a1cb-da2b-4756-8148-f4271b43cccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235146333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3235146333
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.693790520
Short name T931
Test name
Test status
Simulation time 15936623 ps
CPU time 0.78 seconds
Started Apr 28 12:39:57 PM PDT 24
Finished Apr 28 12:40:00 PM PDT 24
Peak memory 205668 kb
Host smart-8ba0a8bb-a9f7-43d9-b8e4-d03c34a99dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693790520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.693790520
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.535382048
Short name T951
Test name
Test status
Simulation time 10327593 ps
CPU time 0.84 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205736 kb
Host smart-61fa1acf-fd19-4547-96bb-ee7cb6123c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535382048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.535382048
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4229801037
Short name T1005
Test name
Test status
Simulation time 25595761 ps
CPU time 0.79 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 205668 kb
Host smart-bbb7299d-7499-4f77-b2c4-d032428a5434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229801037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4229801037
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2139212177
Short name T967
Test name
Test status
Simulation time 11063070 ps
CPU time 0.83 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 205696 kb
Host smart-adf82fb8-5e2f-4729-9046-2ea5ded1c946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139212177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2139212177
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3417315172
Short name T1060
Test name
Test status
Simulation time 9222450 ps
CPU time 0.7 seconds
Started Apr 28 12:40:07 PM PDT 24
Finished Apr 28 12:40:09 PM PDT 24
Peak memory 205656 kb
Host smart-38f31106-12c5-4cff-8a15-8f3b559c3355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417315172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3417315172
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.530538233
Short name T932
Test name
Test status
Simulation time 13031901 ps
CPU time 0.7 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 205728 kb
Host smart-507ef880-cc39-4fc2-a1eb-b019cacf4e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530538233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.530538233
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2314700487
Short name T1057
Test name
Test status
Simulation time 733786849 ps
CPU time 15.25 seconds
Started Apr 28 12:39:39 PM PDT 24
Finished Apr 28 12:39:54 PM PDT 24
Peak memory 205952 kb
Host smart-79b2a5b2-465c-4f61-a4f7-cad70651d1c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314700487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
314700487
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2670120873
Short name T997
Test name
Test status
Simulation time 2237779549 ps
CPU time 8.73 seconds
Started Apr 28 12:39:48 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 206120 kb
Host smart-0b91800d-abbb-4d30-8539-4b27b2bfa412
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670120873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
670120873
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3190696779
Short name T987
Test name
Test status
Simulation time 130566445 ps
CPU time 1.5 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:39:49 PM PDT 24
Peak memory 206076 kb
Host smart-842e1773-cfe1-4bbb-96d2-76078fd0dafe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190696779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
190696779
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4140800620
Short name T945
Test name
Test status
Simulation time 29730050 ps
CPU time 1.12 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 214376 kb
Host smart-2d100928-09f8-4e59-aa56-93fd33275f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140800620 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4140800620
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2538451456
Short name T956
Test name
Test status
Simulation time 43303339 ps
CPU time 1.16 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:01 PM PDT 24
Peak memory 205936 kb
Host smart-bd416f4a-eca8-4378-900d-d16d93cf042d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538451456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2538451456
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2151974927
Short name T1027
Test name
Test status
Simulation time 12330662 ps
CPU time 0.72 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:39:49 PM PDT 24
Peak memory 205720 kb
Host smart-1e6f4b96-6e73-4df4-8b7d-db64c6285fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151974927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2151974927
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3151380536
Short name T1000
Test name
Test status
Simulation time 689658238 ps
CPU time 3.92 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 206096 kb
Host smart-9dad5268-a68f-49dd-8af6-8802234fd67c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151380536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3151380536
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.416039024
Short name T954
Test name
Test status
Simulation time 936008531 ps
CPU time 14.95 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:40:08 PM PDT 24
Peak memory 214504 kb
Host smart-951e17aa-9dfa-429b-b2f1-84e5a34eddc2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416039024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.416039024
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.878900415
Short name T1065
Test name
Test status
Simulation time 308136408 ps
CPU time 5.62 seconds
Started Apr 28 12:39:31 PM PDT 24
Finished Apr 28 12:39:37 PM PDT 24
Peak memory 214520 kb
Host smart-1f6555b1-5767-45d6-8723-876a5e0fea70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878900415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.878900415
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2320558776
Short name T914
Test name
Test status
Simulation time 96431439 ps
CPU time 1.97 seconds
Started Apr 28 12:39:40 PM PDT 24
Finished Apr 28 12:39:42 PM PDT 24
Peak memory 214260 kb
Host smart-8cf52c4f-b816-4933-ac42-3b25994cf164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320558776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2320558776
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1124027398
Short name T185
Test name
Test status
Simulation time 242849927 ps
CPU time 3.71 seconds
Started Apr 28 12:39:51 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 214220 kb
Host smart-9744f68a-162b-4235-a0aa-c2fa511d574d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124027398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1124027398
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4270549738
Short name T965
Test name
Test status
Simulation time 13155034 ps
CPU time 0.7 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:54 PM PDT 24
Peak memory 205632 kb
Host smart-94f88aaa-62d8-4290-a272-4a729fc49a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270549738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4270549738
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2518993621
Short name T986
Test name
Test status
Simulation time 39967685 ps
CPU time 0.88 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:17 PM PDT 24
Peak memory 205772 kb
Host smart-57634ed5-66a9-4039-88d7-2ab94251e781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518993621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2518993621
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.330618826
Short name T928
Test name
Test status
Simulation time 173310110 ps
CPU time 0.72 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:14 PM PDT 24
Peak memory 205772 kb
Host smart-5b69c77d-d9c6-4365-894f-b69bb62da241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330618826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.330618826
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.628054987
Short name T915
Test name
Test status
Simulation time 15336400 ps
CPU time 0.72 seconds
Started Apr 28 12:40:11 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 205792 kb
Host smart-d1c251ec-7a2e-448d-87e4-ecbb6713910d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628054987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.628054987
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4120888322
Short name T1038
Test name
Test status
Simulation time 39836592 ps
CPU time 0.9 seconds
Started Apr 28 12:40:35 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 205744 kb
Host smart-9b1196e6-c336-4f71-98aa-d1ffeb2f5fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120888322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4120888322
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.959745800
Short name T1031
Test name
Test status
Simulation time 10008268 ps
CPU time 0.76 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 205744 kb
Host smart-9e6bf559-4065-46c9-9dec-a4969c5e87cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959745800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.959745800
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.879799665
Short name T927
Test name
Test status
Simulation time 20239147 ps
CPU time 0.7 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:26 PM PDT 24
Peak memory 205756 kb
Host smart-97eaa6c4-c381-41d9-8062-40d580f10e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879799665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.879799665
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1192225933
Short name T944
Test name
Test status
Simulation time 12385115 ps
CPU time 0.73 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 205740 kb
Host smart-d92a230b-5e86-4438-beb6-52c53cfd661c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192225933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1192225933
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2683959113
Short name T934
Test name
Test status
Simulation time 25656916 ps
CPU time 0.88 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 205696 kb
Host smart-97854aef-ac11-497b-b98e-284b460746ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683959113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2683959113
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3142373319
Short name T1042
Test name
Test status
Simulation time 49232088 ps
CPU time 0.74 seconds
Started Apr 28 12:40:20 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 205764 kb
Host smart-7af52a0d-4d7c-440b-9e69-30f7eee86a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142373319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3142373319
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1368340852
Short name T1039
Test name
Test status
Simulation time 53305826 ps
CPU time 1.45 seconds
Started Apr 28 12:39:47 PM PDT 24
Finished Apr 28 12:39:49 PM PDT 24
Peak memory 216776 kb
Host smart-eb519d90-4c8e-4c4b-a552-10a84926195f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368340852 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1368340852
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2230489820
Short name T948
Test name
Test status
Simulation time 27026161 ps
CPU time 1.09 seconds
Started Apr 28 12:39:58 PM PDT 24
Finished Apr 28 12:40:01 PM PDT 24
Peak memory 206120 kb
Host smart-234c4fe1-4cb0-48a5-ba4b-341f79223cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230489820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2230489820
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.634101053
Short name T992
Test name
Test status
Simulation time 11378575 ps
CPU time 0.88 seconds
Started Apr 28 12:39:48 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 205708 kb
Host smart-a3f095c2-7f33-452b-8f25-a529caec8cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634101053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.634101053
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4222147776
Short name T1055
Test name
Test status
Simulation time 202389652 ps
CPU time 3.92 seconds
Started Apr 28 12:39:45 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 206064 kb
Host smart-74a1782c-4d8c-4d69-8449-7f9aa8900cba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222147776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4222147776
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4256948467
Short name T115
Test name
Test status
Simulation time 524629567 ps
CPU time 5.46 seconds
Started Apr 28 12:39:46 PM PDT 24
Finished Apr 28 12:39:53 PM PDT 24
Peak memory 214472 kb
Host smart-f0fa449f-667a-4686-8f5c-f3d68841b2f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256948467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4256948467
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1858723951
Short name T1007
Test name
Test status
Simulation time 161188663 ps
CPU time 4.57 seconds
Started Apr 28 12:39:44 PM PDT 24
Finished Apr 28 12:39:50 PM PDT 24
Peak memory 214552 kb
Host smart-260878cf-a6b8-4db7-b3ee-4f2bb14701f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858723951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1858723951
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3516283443
Short name T1006
Test name
Test status
Simulation time 152599063 ps
CPU time 3.24 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 214160 kb
Host smart-d1adc557-201d-4fc9-b4e9-f932dab172e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516283443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3516283443
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1265772844
Short name T164
Test name
Test status
Simulation time 537608002 ps
CPU time 12.75 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:40:03 PM PDT 24
Peak memory 214268 kb
Host smart-fecf7bad-e747-41a9-8ff1-f03f96f2264d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265772844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1265772844
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.774963436
Short name T1008
Test name
Test status
Simulation time 24846738 ps
CPU time 1.37 seconds
Started Apr 28 12:39:45 PM PDT 24
Finished Apr 28 12:39:48 PM PDT 24
Peak memory 214236 kb
Host smart-595d0f84-9c7e-46a5-80f6-00ea8bd432c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774963436 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.774963436
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.899425416
Short name T981
Test name
Test status
Simulation time 15822227 ps
CPU time 1.07 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 206044 kb
Host smart-f82c0414-4bdf-404f-9b37-204cf99757c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899425416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.899425416
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4113461002
Short name T911
Test name
Test status
Simulation time 39358054 ps
CPU time 0.72 seconds
Started Apr 28 12:40:03 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 205652 kb
Host smart-60897393-2ba3-4403-944b-2066ee16b4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113461002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4113461002
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1626932733
Short name T1043
Test name
Test status
Simulation time 159311648 ps
CPU time 1.66 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:54 PM PDT 24
Peak memory 205976 kb
Host smart-50026008-9090-4493-9326-04e1357fc9d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626932733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1626932733
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3350017078
Short name T999
Test name
Test status
Simulation time 437751720 ps
CPU time 2 seconds
Started Apr 28 12:39:45 PM PDT 24
Finished Apr 28 12:39:47 PM PDT 24
Peak memory 214460 kb
Host smart-cadce374-0b8b-4d8d-b33f-9aea34d291f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350017078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3350017078
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1952045858
Short name T971
Test name
Test status
Simulation time 421385068 ps
CPU time 14.02 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:40:10 PM PDT 24
Peak memory 220700 kb
Host smart-76c2498a-eea7-4e8d-91db-21765eb7b19a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952045858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1952045858
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1721408140
Short name T1063
Test name
Test status
Simulation time 160638841 ps
CPU time 5.45 seconds
Started Apr 28 12:39:44 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 214232 kb
Host smart-3a3fe9dd-3cab-43c7-8518-774a1a686437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721408140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1721408140
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1038620236
Short name T183
Test name
Test status
Simulation time 300599956 ps
CPU time 5.85 seconds
Started Apr 28 12:39:58 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 220364 kb
Host smart-bb6d2b96-04fa-4665-aeda-bf16baecdbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038620236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1038620236
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.279938585
Short name T952
Test name
Test status
Simulation time 225713518 ps
CPU time 2.35 seconds
Started Apr 28 12:39:57 PM PDT 24
Finished Apr 28 12:40:01 PM PDT 24
Peak memory 214264 kb
Host smart-cfa61804-3aed-42c3-8afc-2312b308dbac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279938585 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.279938585
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3787794899
Short name T1044
Test name
Test status
Simulation time 23585077 ps
CPU time 1.06 seconds
Started Apr 28 12:39:38 PM PDT 24
Finished Apr 28 12:39:40 PM PDT 24
Peak memory 205972 kb
Host smart-07c18019-a743-40c1-9ff8-12dd45ecd20f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787794899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3787794899
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3205419389
Short name T983
Test name
Test status
Simulation time 11201892 ps
CPU time 0.66 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 205796 kb
Host smart-76a444b7-8b6f-428c-925a-911f2be7e87a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205419389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3205419389
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3210040958
Short name T1014
Test name
Test status
Simulation time 25269806 ps
CPU time 1.73 seconds
Started Apr 28 12:39:49 PM PDT 24
Finished Apr 28 12:39:52 PM PDT 24
Peak memory 206224 kb
Host smart-503c90be-e8de-4521-adf4-e301c7fe5621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210040958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3210040958
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2541113805
Short name T1003
Test name
Test status
Simulation time 659395931 ps
CPU time 4.92 seconds
Started Apr 28 12:39:51 PM PDT 24
Finished Apr 28 12:39:57 PM PDT 24
Peak memory 214576 kb
Host smart-57b1078e-8f98-464b-8f62-ef9aa554f688
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541113805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2541113805
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.86382809
Short name T1036
Test name
Test status
Simulation time 134197862 ps
CPU time 3.64 seconds
Started Apr 28 12:39:44 PM PDT 24
Finished Apr 28 12:39:48 PM PDT 24
Peak memory 214664 kb
Host smart-315cec67-c1b7-4f12-b510-5432593300cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86382809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_shadow_reg_errors_with_csr_rw.86382809
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.110863596
Short name T1052
Test name
Test status
Simulation time 134158594 ps
CPU time 3.47 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:06 PM PDT 24
Peak memory 214268 kb
Host smart-bbf22cd7-b478-4853-b81a-2433600133c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110863596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.110863596
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2324607579
Short name T916
Test name
Test status
Simulation time 103275220 ps
CPU time 1.64 seconds
Started Apr 28 12:39:53 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 218932 kb
Host smart-1e7d76f7-708f-4c87-8f81-081590425863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324607579 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2324607579
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2433384502
Short name T148
Test name
Test status
Simulation time 33773449 ps
CPU time 0.85 seconds
Started Apr 28 12:39:57 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 205772 kb
Host smart-0f42709c-f76c-414b-9fed-2316bb1ed87e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433384502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2433384502
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4004409121
Short name T1028
Test name
Test status
Simulation time 10783279 ps
CPU time 0.82 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:39:54 PM PDT 24
Peak memory 205744 kb
Host smart-5a0682e5-60fd-418c-8c01-b74464c1615b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004409121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4004409121
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3180350956
Short name T147
Test name
Test status
Simulation time 34677785 ps
CPU time 2.01 seconds
Started Apr 28 12:39:41 PM PDT 24
Finished Apr 28 12:39:43 PM PDT 24
Peak memory 206108 kb
Host smart-4687285b-2bf7-4e73-898c-d2eabad8cc8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180350956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3180350956
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3374446940
Short name T103
Test name
Test status
Simulation time 114405864 ps
CPU time 4.26 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:04 PM PDT 24
Peak memory 222700 kb
Host smart-892a8629-d7a5-4f3a-9328-5464dc6da9c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374446940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3374446940
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4220707389
Short name T953
Test name
Test status
Simulation time 331714719 ps
CPU time 4.89 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:40:03 PM PDT 24
Peak memory 214564 kb
Host smart-3c03e747-54f8-41f5-af21-6072ca7d8e37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220707389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4220707389
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.109078962
Short name T1050
Test name
Test status
Simulation time 155183339 ps
CPU time 4.88 seconds
Started Apr 28 12:39:50 PM PDT 24
Finished Apr 28 12:39:56 PM PDT 24
Peak memory 214208 kb
Host smart-2fa37564-f514-4e85-8bdf-b472b0264ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109078962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.109078962
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.97454156
Short name T158
Test name
Test status
Simulation time 189978264 ps
CPU time 3.84 seconds
Started Apr 28 12:39:56 PM PDT 24
Finished Apr 28 12:40:02 PM PDT 24
Peak memory 214284 kb
Host smart-5466f512-9bcc-4b75-b662-0e8b3232f3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97454156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.97454156
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2249428763
Short name T1030
Test name
Test status
Simulation time 28553401 ps
CPU time 1.1 seconds
Started Apr 28 12:39:51 PM PDT 24
Finished Apr 28 12:39:53 PM PDT 24
Peak memory 206108 kb
Host smart-3609e94b-af14-408a-9bdf-5eade2769d59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249428763 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2249428763
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1808395411
Short name T990
Test name
Test status
Simulation time 31926150 ps
CPU time 1.53 seconds
Started Apr 28 12:39:52 PM PDT 24
Finished Apr 28 12:40:00 PM PDT 24
Peak memory 205940 kb
Host smart-a3a64419-4f90-40c0-a8ec-1e7137f202b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808395411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1808395411
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2803460390
Short name T1018
Test name
Test status
Simulation time 14928665 ps
CPU time 0.77 seconds
Started Apr 28 12:40:02 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 205660 kb
Host smart-8c6625be-f7bc-4054-b00c-a1b7985a2f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803460390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2803460390
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.904581057
Short name T1051
Test name
Test status
Simulation time 205686522 ps
CPU time 2.91 seconds
Started Apr 28 12:39:48 PM PDT 24
Finished Apr 28 12:39:51 PM PDT 24
Peak memory 206096 kb
Host smart-cf1b012f-41c5-426c-aaa4-1362df59e18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904581057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.904581057
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1357912860
Short name T989
Test name
Test status
Simulation time 678773006 ps
CPU time 4.68 seconds
Started Apr 28 12:39:54 PM PDT 24
Finished Apr 28 12:40:00 PM PDT 24
Peak memory 220068 kb
Host smart-836e25a3-1322-474c-82bc-3b29b06b2c16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357912860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1357912860
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3535807630
Short name T1066
Test name
Test status
Simulation time 88180432 ps
CPU time 2.97 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 216356 kb
Host smart-e70b5234-2814-4a1b-b4ae-b002f94cec5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535807630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3535807630
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1467374198
Short name T435
Test name
Test status
Simulation time 137274485 ps
CPU time 2.6 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 213916 kb
Host smart-f72eb3a8-e0a6-4897-af08-be1b1f9efd01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467374198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1467374198
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2694250262
Short name T563
Test name
Test status
Simulation time 141806992 ps
CPU time 1.68 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 208284 kb
Host smart-b68e52bd-1084-4f75-b48b-4f80be7a56af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694250262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2694250262
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2563002256
Short name T274
Test name
Test status
Simulation time 16421189 ps
CPU time 1.42 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 207116 kb
Host smart-a5820dce-8cba-4ce5-8761-6807b454f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563002256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2563002256
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2927717118
Short name T301
Test name
Test status
Simulation time 371898610 ps
CPU time 4.54 seconds
Started Apr 28 12:41:47 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 211452 kb
Host smart-7e879cb4-5bc5-46e3-9f4d-0956df5a1a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927717118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2927717118
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.377696518
Short name T225
Test name
Test status
Simulation time 1339210072 ps
CPU time 15 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 220092 kb
Host smart-9e2a27dc-d7d2-4307-8cfc-ccd050d81898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377696518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.377696518
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3804731963
Short name T292
Test name
Test status
Simulation time 923275330 ps
CPU time 4.71 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:27 PM PDT 24
Peak memory 208896 kb
Host smart-85fb34a0-8282-4a48-8fb4-5d59dd02626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804731963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3804731963
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2879913269
Short name T40
Test name
Test status
Simulation time 1592653513 ps
CPU time 12.15 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 235024 kb
Host smart-f1ea07cf-fc30-4a83-9c8c-4a14d23f6ceb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879913269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2879913269
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.969082546
Short name T258
Test name
Test status
Simulation time 665116174 ps
CPU time 7.24 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 208128 kb
Host smart-913d0f90-d27b-431d-bb57-1f00f14503f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969082546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.969082546
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3543044287
Short name T468
Test name
Test status
Simulation time 121658805 ps
CPU time 3.79 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 207856 kb
Host smart-1ed41d96-6c01-446b-9a41-bad42d80e827
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543044287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3543044287
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1931187451
Short name T615
Test name
Test status
Simulation time 153660618 ps
CPU time 2.67 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 208280 kb
Host smart-bd212489-080f-40a5-a3ca-919f9209362c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931187451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1931187451
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1102177318
Short name T818
Test name
Test status
Simulation time 69399875 ps
CPU time 3.63 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:55 PM PDT 24
Peak memory 205944 kb
Host smart-3fc6697c-3b9a-4d1d-849e-74e2807647e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102177318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1102177318
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1282110107
Short name T717
Test name
Test status
Simulation time 172823316 ps
CPU time 4.09 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 207676 kb
Host smart-6704617b-a244-4cd4-bc39-52d4592a9723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282110107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1282110107
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.656132666
Short name T877
Test name
Test status
Simulation time 185287560 ps
CPU time 2.79 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 208100 kb
Host smart-2d9a919a-df56-4703-a4c0-22ed58a153d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656132666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.656132666
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3050054269
Short name T637
Test name
Test status
Simulation time 495170119 ps
CPU time 5.97 seconds
Started Apr 28 12:41:35 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 208028 kb
Host smart-9e1ec1ff-f443-4543-8823-ec14f29b5bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050054269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3050054269
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3993894701
Short name T625
Test name
Test status
Simulation time 48884840 ps
CPU time 2.96 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 209808 kb
Host smart-79cc55e0-0c1d-4959-b831-416f2f19a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993894701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3993894701
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3698577504
Short name T487
Test name
Test status
Simulation time 10403856 ps
CPU time 0.82 seconds
Started Apr 28 12:41:46 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 205568 kb
Host smart-466460ea-6c31-4ab6-9d36-17c64f772f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698577504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3698577504
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4114157157
Short name T440
Test name
Test status
Simulation time 1066716625 ps
CPU time 15.84 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 214000 kb
Host smart-6459f801-0d91-4472-ae34-85c7e4e723e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114157157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4114157157
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1773638070
Short name T9
Test name
Test status
Simulation time 493826642 ps
CPU time 4.21 seconds
Started Apr 28 12:41:50 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 209748 kb
Host smart-182eb37a-afaf-4860-a993-cc32b5798601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773638070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1773638070
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.6774773
Short name T297
Test name
Test status
Simulation time 254111964 ps
CPU time 2.17 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:44 PM PDT 24
Peak memory 206744 kb
Host smart-fa11d99a-b540-4e10-9565-d9d591845154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6774773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.6774773
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.430618788
Short name T612
Test name
Test status
Simulation time 58411005 ps
CPU time 3 seconds
Started Apr 28 12:41:36 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 208528 kb
Host smart-6da78231-0b86-4db5-a37f-fdb81cf65c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430618788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.430618788
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3058477660
Short name T713
Test name
Test status
Simulation time 97553662 ps
CPU time 2.15 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 208176 kb
Host smart-2a217ee7-8bcc-4cbb-b39b-646a4abb063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058477660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3058477660
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1825321165
Short name T309
Test name
Test status
Simulation time 39523939 ps
CPU time 2.84 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 208540 kb
Host smart-d643f018-5317-42fe-8a38-a64dde846419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825321165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1825321165
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4087882437
Short name T11
Test name
Test status
Simulation time 4610799930 ps
CPU time 18.95 seconds
Started Apr 28 12:41:28 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 239632 kb
Host smart-f595081e-cb71-4523-a82a-8ff4f66f9ab9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087882437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4087882437
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3218505942
Short name T365
Test name
Test status
Simulation time 583016928 ps
CPU time 3.93 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 208252 kb
Host smart-5d3cf05b-08d4-4244-bd98-04df9445f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218505942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3218505942
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1551776379
Short name T489
Test name
Test status
Simulation time 117831247 ps
CPU time 3.01 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 207540 kb
Host smart-a8e92af7-7fe6-4135-9644-0eab2fa4db28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551776379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1551776379
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2628590455
Short name T417
Test name
Test status
Simulation time 83741723 ps
CPU time 2.93 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 208636 kb
Host smart-68bab332-e9aa-4a1b-a0b5-034548d9cf20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628590455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2628590455
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.731688414
Short name T511
Test name
Test status
Simulation time 87466498 ps
CPU time 1.9 seconds
Started Apr 28 12:41:35 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 206376 kb
Host smart-2acd989e-b703-4937-b4a7-d56a1aa4ed54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731688414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.731688414
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2044581343
Short name T266
Test name
Test status
Simulation time 238001513 ps
CPU time 4.75 seconds
Started Apr 28 12:41:31 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 207444 kb
Host smart-1d8640fa-adf4-466a-9a21-442553ba3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044581343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2044581343
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.320871839
Short name T647
Test name
Test status
Simulation time 150944172 ps
CPU time 2.24 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 206324 kb
Host smart-de479bc1-04b7-44a7-8353-6b478ee938a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320871839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.320871839
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1983494352
Short name T42
Test name
Test status
Simulation time 643786671 ps
CPU time 11.96 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 216072 kb
Host smart-5c6f8237-4355-4975-b359-7dfaf262bbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983494352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1983494352
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4176450088
Short name T497
Test name
Test status
Simulation time 201650363 ps
CPU time 5.8 seconds
Started Apr 28 12:41:27 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 218148 kb
Host smart-5beb71fb-566f-4113-b768-ac80306e46b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176450088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4176450088
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.766142672
Short name T106
Test name
Test status
Simulation time 50855817 ps
CPU time 2.22 seconds
Started Apr 28 12:41:36 PM PDT 24
Finished Apr 28 12:41:40 PM PDT 24
Peak memory 209776 kb
Host smart-88e34256-dba5-4936-9147-ed03ef2a0831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766142672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.766142672
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3325711205
Short name T633
Test name
Test status
Simulation time 61725947 ps
CPU time 0.97 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 205748 kb
Host smart-5996e466-cab5-4536-80ff-2aa6044438a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325711205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3325711205
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2006684819
Short name T310
Test name
Test status
Simulation time 152709067 ps
CPU time 2.83 seconds
Started Apr 28 12:42:01 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 217832 kb
Host smart-629e4182-3525-4b04-9858-05e6e2380c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006684819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2006684819
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3166616484
Short name T667
Test name
Test status
Simulation time 52787294 ps
CPU time 1.31 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 207060 kb
Host smart-f036280a-d6bf-4008-b461-dac094fcbd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166616484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3166616484
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2034615876
Short name T678
Test name
Test status
Simulation time 60695561 ps
CPU time 3.31 seconds
Started Apr 28 12:42:03 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 207180 kb
Host smart-9e672515-cc4e-440c-b8d7-fbb46e0b7c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034615876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2034615876
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1211569345
Short name T636
Test name
Test status
Simulation time 64875236 ps
CPU time 3.38 seconds
Started Apr 28 12:42:04 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 208012 kb
Host smart-4c3b5554-3f4d-4dcf-b06a-83c1f504f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211569345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1211569345
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.69464733
Short name T806
Test name
Test status
Simulation time 67634510 ps
CPU time 2.42 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 206688 kb
Host smart-3c70f18d-65b4-4b7a-a405-b9eb4c2c3168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69464733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.69464733
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1009096151
Short name T751
Test name
Test status
Simulation time 515067629 ps
CPU time 6.64 seconds
Started Apr 28 12:42:12 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 207604 kb
Host smart-66a193b7-7909-4efa-8d9a-ac163a2aea00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009096151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1009096151
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.990986128
Short name T882
Test name
Test status
Simulation time 797581264 ps
CPU time 10.51 seconds
Started Apr 28 12:42:00 PM PDT 24
Finished Apr 28 12:42:12 PM PDT 24
Peak memory 207228 kb
Host smart-6fbcca1b-173d-43dd-b3c5-a10de0655931
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990986128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.990986128
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3938491272
Short name T871
Test name
Test status
Simulation time 568021592 ps
CPU time 15 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:15 PM PDT 24
Peak memory 207580 kb
Host smart-46354462-01a3-4eec-af4d-8a7af62d5537
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938491272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3938491272
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.485112095
Short name T388
Test name
Test status
Simulation time 116568577 ps
CPU time 2.77 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:18 PM PDT 24
Peak memory 206916 kb
Host smart-47a9f253-8a3c-4134-8fcd-2931ada4448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485112095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.485112095
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3225955976
Short name T125
Test name
Test status
Simulation time 594155771 ps
CPU time 7.17 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:10 PM PDT 24
Peak memory 207412 kb
Host smart-29f8a5c1-e237-43c1-a39d-74ef92d55cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225955976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3225955976
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2347635001
Short name T247
Test name
Test status
Simulation time 157194202 ps
CPU time 4.93 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 214128 kb
Host smart-8e027d37-54bc-43cd-843d-1dcf68f4431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347635001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2347635001
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.326112847
Short name T60
Test name
Test status
Simulation time 108067077 ps
CPU time 2.43 seconds
Started Apr 28 12:42:03 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 209676 kb
Host smart-55c40e3e-11d7-4f8e-b17e-56a61d1f9052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326112847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.326112847
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1641286817
Short name T797
Test name
Test status
Simulation time 92819518 ps
CPU time 0.88 seconds
Started Apr 28 12:42:12 PM PDT 24
Finished Apr 28 12:42:14 PM PDT 24
Peak memory 205704 kb
Host smart-2b68d428-94e9-4ee3-89eb-07f93feff2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641286817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1641286817
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.149979541
Short name T885
Test name
Test status
Simulation time 617863656 ps
CPU time 5.06 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 209336 kb
Host smart-791016d6-6114-434e-92e5-d6da2398a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149979541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.149979541
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2507658809
Short name T362
Test name
Test status
Simulation time 425473841 ps
CPU time 3.39 seconds
Started Apr 28 12:42:04 PM PDT 24
Finished Apr 28 12:42:09 PM PDT 24
Peak memory 222100 kb
Host smart-1c1558f2-8a33-4897-88c1-c341957d3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507658809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2507658809
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1643732223
Short name T193
Test name
Test status
Simulation time 467215561 ps
CPU time 3.82 seconds
Started Apr 28 12:42:01 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 219528 kb
Host smart-1b9ea53d-a335-411f-ba29-064cb4bfc936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643732223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1643732223
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1147383851
Short name T564
Test name
Test status
Simulation time 79069428 ps
CPU time 3.17 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 209324 kb
Host smart-0a65ed44-c7ff-47fb-accb-cf5c5d14ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147383851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1147383851
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.320762412
Short name T493
Test name
Test status
Simulation time 214068124 ps
CPU time 5.32 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 207524 kb
Host smart-416650df-80f9-4931-88a4-8e20c8027ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320762412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.320762412
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3391918002
Short name T630
Test name
Test status
Simulation time 98626531 ps
CPU time 4.18 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 208256 kb
Host smart-d547cf26-1275-4d0d-b52e-f7bd2e46cf19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391918002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3391918002
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1795325061
Short name T136
Test name
Test status
Simulation time 1180429411 ps
CPU time 28.67 seconds
Started Apr 28 12:42:20 PM PDT 24
Finished Apr 28 12:42:49 PM PDT 24
Peak memory 207964 kb
Host smart-1cbaddf9-427d-46db-a369-05b28619d6b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795325061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1795325061
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3368074563
Short name T558
Test name
Test status
Simulation time 127557539 ps
CPU time 2.32 seconds
Started Apr 28 12:42:10 PM PDT 24
Finished Apr 28 12:42:13 PM PDT 24
Peak memory 206356 kb
Host smart-64edcb4e-d146-4ebd-b8c0-27f85a7bd8fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368074563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3368074563
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.447142970
Short name T798
Test name
Test status
Simulation time 427052905 ps
CPU time 3.38 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 214720 kb
Host smart-b63a83ea-2a13-4c5a-8c28-23a1aef4611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447142970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.447142970
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3184581116
Short name T16
Test name
Test status
Simulation time 199768910 ps
CPU time 6.52 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 207420 kb
Host smart-db3b9e3e-2d6f-4831-b2dd-9ce4f324f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184581116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3184581116
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.600098777
Short name T623
Test name
Test status
Simulation time 659290995 ps
CPU time 8.68 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:41 PM PDT 24
Peak memory 208540 kb
Host smart-1ba9d08e-8ec8-46d8-a398-948baf679bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600098777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.600098777
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3432297805
Short name T161
Test name
Test status
Simulation time 62654679 ps
CPU time 2.53 seconds
Started Apr 28 12:42:10 PM PDT 24
Finished Apr 28 12:42:14 PM PDT 24
Peak memory 209556 kb
Host smart-cd4d673f-9fcc-42aa-8b47-8e943ae4acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432297805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3432297805
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3343979616
Short name T443
Test name
Test status
Simulation time 20026748 ps
CPU time 0.97 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:17 PM PDT 24
Peak memory 205756 kb
Host smart-2e767d26-5f4c-413f-958d-90f0f8e5977b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343979616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3343979616
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.694424391
Short name T238
Test name
Test status
Simulation time 38665588 ps
CPU time 2.76 seconds
Started Apr 28 12:42:04 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 209052 kb
Host smart-ef5327e7-ab43-438b-b4ec-4ae2160d77a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694424391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.694424391
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3727537958
Short name T394
Test name
Test status
Simulation time 110742126 ps
CPU time 4.13 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 209468 kb
Host smart-94d1ce48-87e0-4c0a-aabe-600a59b48b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727537958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3727537958
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3538645676
Short name T892
Test name
Test status
Simulation time 88860735 ps
CPU time 3.87 seconds
Started Apr 28 12:42:38 PM PDT 24
Finished Apr 28 12:42:47 PM PDT 24
Peak memory 214124 kb
Host smart-c353043b-9651-4411-9ea0-a2b05485a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538645676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3538645676
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2871425041
Short name T590
Test name
Test status
Simulation time 59011766 ps
CPU time 2.05 seconds
Started Apr 28 12:42:04 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 214012 kb
Host smart-f0cc9340-ac8e-467c-acae-fcef51d2cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871425041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2871425041
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1480569931
Short name T503
Test name
Test status
Simulation time 230170097 ps
CPU time 4 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:22 PM PDT 24
Peak memory 206848 kb
Host smart-f4ac1cd9-9e74-4bd3-b027-944812892143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480569931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1480569931
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2156520927
Short name T839
Test name
Test status
Simulation time 53851476 ps
CPU time 2.96 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 206768 kb
Host smart-f2296c30-ad5e-4498-b39c-aa8061f6cc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156520927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2156520927
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.176708630
Short name T464
Test name
Test status
Simulation time 207794620 ps
CPU time 7.85 seconds
Started Apr 28 12:42:15 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 208232 kb
Host smart-ce3d0884-a066-4aba-b5e0-5ffd07159604
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176708630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.176708630
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3696853201
Short name T894
Test name
Test status
Simulation time 19859346 ps
CPU time 1.71 seconds
Started Apr 28 12:42:06 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 206512 kb
Host smart-c2c481bc-ed2c-4db6-b13c-847a18c3c6cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696853201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3696853201
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3361570339
Short name T841
Test name
Test status
Simulation time 765906121 ps
CPU time 3.29 seconds
Started Apr 28 12:42:05 PM PDT 24
Finished Apr 28 12:42:09 PM PDT 24
Peak memory 214048 kb
Host smart-d4643580-4b4f-41b5-a42e-cc5fbe36fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361570339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3361570339
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1549129509
Short name T533
Test name
Test status
Simulation time 208059608 ps
CPU time 3.5 seconds
Started Apr 28 12:42:07 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 206344 kb
Host smart-6811fd31-576e-45d5-bac3-9db7ce81aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549129509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1549129509
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3258050642
Short name T120
Test name
Test status
Simulation time 1769796728 ps
CPU time 18.06 seconds
Started Apr 28 12:42:01 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 222320 kb
Host smart-ea6ba3eb-72e9-42e5-b8e8-cac7d12265fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258050642 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3258050642
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1926505564
Short name T268
Test name
Test status
Simulation time 160430120 ps
CPU time 4.03 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 214040 kb
Host smart-fb2f33b2-4ed1-442c-9692-d54abcd654f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926505564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1926505564
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.594912266
Short name T52
Test name
Test status
Simulation time 401983164 ps
CPU time 3.55 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 209944 kb
Host smart-63cbe0bf-dd71-4dae-aee9-ee275339e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594912266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.594912266
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.683167971
Short name T853
Test name
Test status
Simulation time 12972423 ps
CPU time 0.89 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:15 PM PDT 24
Peak memory 205544 kb
Host smart-cecdd2cc-2e4b-4ebf-beba-135ecef45cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683167971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.683167971
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2193309587
Short name T824
Test name
Test status
Simulation time 43769495 ps
CPU time 3.52 seconds
Started Apr 28 12:42:20 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 214016 kb
Host smart-12785ea4-d193-4deb-b6b3-18560a01e754
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193309587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2193309587
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3840677825
Short name T434
Test name
Test status
Simulation time 121433264 ps
CPU time 2.8 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:17 PM PDT 24
Peak memory 214116 kb
Host smart-96b5650d-c778-43da-81e7-8d8deaa7d6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840677825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3840677825
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2801682623
Short name T3
Test name
Test status
Simulation time 139003088 ps
CPU time 3.56 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 218960 kb
Host smart-69e65be4-2cec-462f-acca-154b3b49a385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801682623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2801682623
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3574251001
Short name T214
Test name
Test status
Simulation time 1201413203 ps
CPU time 9.58 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 214024 kb
Host smart-7a79669a-4f96-49ee-91db-9b502489e4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574251001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3574251001
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3397019596
Short name T381
Test name
Test status
Simulation time 463591579 ps
CPU time 4.43 seconds
Started Apr 28 12:42:07 PM PDT 24
Finished Apr 28 12:42:12 PM PDT 24
Peak memory 220400 kb
Host smart-d3516ad8-33bf-46a0-9145-80bcbb4ffcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397019596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3397019596
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3348082358
Short name T692
Test name
Test status
Simulation time 1050877259 ps
CPU time 3.62 seconds
Started Apr 28 12:42:15 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 208356 kb
Host smart-1136f59b-3f10-49a7-9429-d407388dc181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348082358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3348082358
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.681398016
Short name T517
Test name
Test status
Simulation time 262543596 ps
CPU time 3.46 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 206860 kb
Host smart-89beb045-5e93-459d-b21d-e7b1ae2bb808
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681398016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.681398016
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1001945783
Short name T811
Test name
Test status
Simulation time 709818143 ps
CPU time 3.84 seconds
Started Apr 28 12:42:03 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 208132 kb
Host smart-269f2d84-012b-40a6-a581-264b6a95131b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001945783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1001945783
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.722173596
Short name T510
Test name
Test status
Simulation time 241842313 ps
CPU time 3.29 seconds
Started Apr 28 12:42:07 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 208240 kb
Host smart-6879b139-94cd-45f5-8932-6246c34550c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722173596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.722173596
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2643754005
Short name T735
Test name
Test status
Simulation time 95552948 ps
CPU time 3.01 seconds
Started Apr 28 12:42:12 PM PDT 24
Finished Apr 28 12:42:16 PM PDT 24
Peak memory 214040 kb
Host smart-bf76be6a-f633-474e-b50d-70a0581ba91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643754005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2643754005
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1226237329
Short name T888
Test name
Test status
Simulation time 66235540 ps
CPU time 2.41 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 206224 kb
Host smart-7393d6c7-24a3-44ef-b89f-99f3025232be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226237329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1226237329
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2238558146
Short name T339
Test name
Test status
Simulation time 1477523468 ps
CPU time 24.73 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 222116 kb
Host smart-7d9c443a-77fe-4c47-948c-fd49d1d288da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238558146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2238558146
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4284953709
Short name T789
Test name
Test status
Simulation time 84976973 ps
CPU time 4.49 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:25 PM PDT 24
Peak memory 214164 kb
Host smart-d0978b21-e9a6-4786-91ac-6d850a22daaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284953709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4284953709
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3649564306
Short name T101
Test name
Test status
Simulation time 747285421 ps
CPU time 2.72 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 209320 kb
Host smart-d7911660-1d60-4aa8-8385-c4fcc6073d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649564306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3649564306
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.158310609
Short name T872
Test name
Test status
Simulation time 13800711 ps
CPU time 0.73 seconds
Started Apr 28 12:42:11 PM PDT 24
Finished Apr 28 12:42:13 PM PDT 24
Peak memory 205604 kb
Host smart-42583466-3a18-4321-a503-67bc2db7308b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158310609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.158310609
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3368841350
Short name T245
Test name
Test status
Simulation time 58345007 ps
CPU time 4.12 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 213960 kb
Host smart-a9a26df2-7837-4883-a84c-92c06aab8881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368841350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3368841350
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1573219943
Short name T734
Test name
Test status
Simulation time 6150100529 ps
CPU time 13.21 seconds
Started Apr 28 12:42:11 PM PDT 24
Finished Apr 28 12:42:25 PM PDT 24
Peak memory 208204 kb
Host smart-e9d94746-a029-4f73-9b02-93196a7281ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573219943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1573219943
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1991415591
Short name T364
Test name
Test status
Simulation time 104528512 ps
CPU time 3.11 seconds
Started Apr 28 12:42:15 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 207968 kb
Host smart-d3d4b5e4-2fb1-4334-bf1d-5858c5ad9625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991415591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1991415591
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3011349682
Short name T122
Test name
Test status
Simulation time 148146986 ps
CPU time 5.67 seconds
Started Apr 28 12:42:41 PM PDT 24
Finished Apr 28 12:42:47 PM PDT 24
Peak memory 213896 kb
Host smart-7db4882e-0dc9-4441-80ab-18ac625a8c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011349682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3011349682
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2069572253
Short name T605
Test name
Test status
Simulation time 87266436 ps
CPU time 2.62 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:17 PM PDT 24
Peak memory 208032 kb
Host smart-80db9394-e65a-414f-9da8-3d93809a4b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069572253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2069572253
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.988456015
Short name T704
Test name
Test status
Simulation time 51187544 ps
CPU time 2.29 seconds
Started Apr 28 12:42:12 PM PDT 24
Finished Apr 28 12:42:16 PM PDT 24
Peak memory 206376 kb
Host smart-01c0bc90-87f0-4530-a3d5-e7305dbb1957
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988456015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.988456015
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1477965693
Short name T838
Test name
Test status
Simulation time 1362045492 ps
CPU time 33.52 seconds
Started Apr 28 12:42:32 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 208192 kb
Host smart-9ded7be3-9a50-44f1-8aed-84ef1e5c87af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477965693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1477965693
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1211772714
Short name T304
Test name
Test status
Simulation time 224536093 ps
CPU time 7.35 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 208380 kb
Host smart-28207bdc-0800-443d-8730-73dbdd3df766
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211772714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1211772714
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.503520410
Short name T801
Test name
Test status
Simulation time 559765558 ps
CPU time 5.28 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 207640 kb
Host smart-86091de9-3a51-45b4-b566-cd221d8f357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503520410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.503520410
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.375095879
Short name T442
Test name
Test status
Simulation time 316099598 ps
CPU time 3.34 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 206452 kb
Host smart-cb1be946-a2fb-45d9-a37e-eb5fe742e8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375095879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.375095879
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3043817649
Short name T143
Test name
Test status
Simulation time 921473323 ps
CPU time 7.78 seconds
Started Apr 28 12:42:12 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 214664 kb
Host smart-6f6564df-7d34-43f6-b0c1-6d2f476337ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043817649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3043817649
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.407696598
Short name T596
Test name
Test status
Simulation time 1539633163 ps
CPU time 8.2 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 214012 kb
Host smart-370449dd-7a86-4e2a-93ab-30af0d182069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407696598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.407696598
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2207307165
Short name T512
Test name
Test status
Simulation time 75660831 ps
CPU time 2.04 seconds
Started Apr 28 12:42:07 PM PDT 24
Finished Apr 28 12:42:10 PM PDT 24
Peak memory 209740 kb
Host smart-a3c05d78-7e59-495d-a461-180ca11e93f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207307165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2207307165
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1067660054
Short name T802
Test name
Test status
Simulation time 12869056 ps
CPU time 0.74 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 205512 kb
Host smart-8b2089df-e15d-4130-9dba-65b06d176f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067660054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1067660054
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2627088558
Short name T426
Test name
Test status
Simulation time 69336851 ps
CPU time 4.54 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 215044 kb
Host smart-8bf02a25-0339-472f-acb0-84b895a91020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627088558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2627088558
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.292630183
Short name T597
Test name
Test status
Simulation time 734675198 ps
CPU time 3.61 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 217948 kb
Host smart-bd3d8eb0-b242-47db-872b-28df33b30117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292630183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.292630183
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1136685842
Short name T65
Test name
Test status
Simulation time 82121523 ps
CPU time 1.82 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:17 PM PDT 24
Peak memory 208080 kb
Host smart-18706b24-b126-4381-959f-98b012d4cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136685842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1136685842
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1892090091
Short name T413
Test name
Test status
Simulation time 129101385 ps
CPU time 5.42 seconds
Started Apr 28 12:42:46 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 222140 kb
Host smart-8e06abed-998b-4a84-8014-52af406da721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892090091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1892090091
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1004324802
Short name T843
Test name
Test status
Simulation time 68221938 ps
CPU time 3.3 seconds
Started Apr 28 12:42:20 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 209264 kb
Host smart-9aec213b-2870-476f-9cde-3c510ba81a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004324802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1004324802
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1970389500
Short name T565
Test name
Test status
Simulation time 481965475 ps
CPU time 6.09 seconds
Started Apr 28 12:42:07 PM PDT 24
Finished Apr 28 12:42:14 PM PDT 24
Peak memory 207624 kb
Host smart-ae37c578-3a44-4a47-a522-59836151519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970389500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1970389500
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.498130241
Short name T861
Test name
Test status
Simulation time 362092935 ps
CPU time 3.8 seconds
Started Apr 28 12:42:09 PM PDT 24
Finished Apr 28 12:42:14 PM PDT 24
Peak memory 208200 kb
Host smart-d6a947e2-229f-4374-afd9-c19df9562652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498130241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.498130241
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.651315064
Short name T450
Test name
Test status
Simulation time 198170235 ps
CPU time 2.9 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 206484 kb
Host smart-96d6c276-dced-4d65-a365-01a9ac3eacf1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651315064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.651315064
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.739792426
Short name T706
Test name
Test status
Simulation time 60073670 ps
CPU time 3.25 seconds
Started Apr 28 12:42:15 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 208416 kb
Host smart-5a28a9b5-5a15-44b9-80e7-46ee9acc650e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739792426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.739792426
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1710941165
Short name T776
Test name
Test status
Simulation time 74143771 ps
CPU time 3.22 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:18 PM PDT 24
Peak memory 206408 kb
Host smart-4596a23d-71b1-4356-bdfc-10f40a6fe055
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710941165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1710941165
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3635705360
Short name T812
Test name
Test status
Simulation time 5907116124 ps
CPU time 14.05 seconds
Started Apr 28 12:42:07 PM PDT 24
Finished Apr 28 12:42:22 PM PDT 24
Peak memory 207688 kb
Host smart-f56dad1d-3311-4aac-8ef6-fdcc8ad40b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635705360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3635705360
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3879252187
Short name T356
Test name
Test status
Simulation time 5307140759 ps
CPU time 52.24 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 215396 kb
Host smart-b4755904-95cc-4f2e-846f-dd26dc45fc7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879252187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3879252187
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.373741894
Short name T852
Test name
Test status
Simulation time 1480536989 ps
CPU time 14.98 seconds
Started Apr 28 12:42:21 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 222312 kb
Host smart-a789528f-6f85-400d-bf84-c37861f62b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373741894 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.373741894
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1347811245
Short name T665
Test name
Test status
Simulation time 633973781 ps
CPU time 7.02 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 206504 kb
Host smart-1a21d83c-0744-4653-bf4e-eebc0992d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347811245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1347811245
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4186189837
Short name T854
Test name
Test status
Simulation time 67569913 ps
CPU time 1.64 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:42:32 PM PDT 24
Peak memory 209660 kb
Host smart-8350b801-549a-4901-b840-e5477c792590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186189837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4186189837
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3554710502
Short name T441
Test name
Test status
Simulation time 27093527 ps
CPU time 0.79 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 205560 kb
Host smart-9ce33d9e-3866-4083-9b13-46e5268c9b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554710502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3554710502
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1054246937
Short name T723
Test name
Test status
Simulation time 155795547 ps
CPU time 5.17 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 208580 kb
Host smart-a51610e8-fd32-41e7-ab42-ad715d94db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054246937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1054246937
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.204600079
Short name T626
Test name
Test status
Simulation time 68547518 ps
CPU time 1.8 seconds
Started Apr 28 12:42:30 PM PDT 24
Finished Apr 28 12:42:33 PM PDT 24
Peak memory 214072 kb
Host smart-a4c07751-0804-45bf-8896-1a5f4853c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204600079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.204600079
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2013121124
Short name T568
Test name
Test status
Simulation time 4157594320 ps
CPU time 39.65 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 220704 kb
Host smart-761571ef-4a11-43a6-bd68-ba605970871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013121124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2013121124
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.694234653
Short name T360
Test name
Test status
Simulation time 254984702 ps
CPU time 5.35 seconds
Started Apr 28 12:42:30 PM PDT 24
Finished Apr 28 12:42:41 PM PDT 24
Peak memory 214060 kb
Host smart-233b697f-aa1a-4e78-8779-aa904fa2d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694234653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.694234653
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3175277468
Short name T196
Test name
Test status
Simulation time 581062439 ps
CPU time 3.8 seconds
Started Apr 28 12:42:21 PM PDT 24
Finished Apr 28 12:42:25 PM PDT 24
Peak memory 209076 kb
Host smart-9e27f403-220e-416e-b637-6d06d3aaea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175277468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3175277468
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3741247894
Short name T873
Test name
Test status
Simulation time 300867987 ps
CPU time 3.98 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:18 PM PDT 24
Peak memory 208472 kb
Host smart-43138526-9033-4713-a9ae-afcadd1299cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741247894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3741247894
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1702816336
Short name T756
Test name
Test status
Simulation time 381691173 ps
CPU time 6.08 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 208420 kb
Host smart-4298225e-537e-479c-900d-a43d9cd39e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702816336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1702816336
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1248101226
Short name T221
Test name
Test status
Simulation time 987801734 ps
CPU time 10.35 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:31 PM PDT 24
Peak memory 208020 kb
Host smart-3932b1c9-ed16-417c-9d81-a994f769a476
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248101226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1248101226
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1686858891
Short name T710
Test name
Test status
Simulation time 486796088 ps
CPU time 4.29 seconds
Started Apr 28 12:42:11 PM PDT 24
Finished Apr 28 12:42:17 PM PDT 24
Peak memory 206496 kb
Host smart-9b6958ed-a06f-44a1-a78a-c39b1764d01c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686858891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1686858891
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.852061122
Short name T477
Test name
Test status
Simulation time 149085459 ps
CPU time 4.73 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 207504 kb
Host smart-676849c7-3729-4293-84fb-be4310c369f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852061122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.852061122
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2827140244
Short name T815
Test name
Test status
Simulation time 197869764 ps
CPU time 2.68 seconds
Started Apr 28 12:42:16 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 217708 kb
Host smart-e40d7552-0b48-4dd7-aa80-fc05b1920d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827140244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2827140244
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3928484151
Short name T660
Test name
Test status
Simulation time 173298472 ps
CPU time 4.95 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:42:35 PM PDT 24
Peak memory 207344 kb
Host smart-4b623440-1e16-46bb-8cf6-a3055645fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928484151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3928484151
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2345501509
Short name T121
Test name
Test status
Simulation time 312753343 ps
CPU time 12.63 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 222348 kb
Host smart-18f764e6-9dd3-414f-88a4-29ad9958afa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345501509 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2345501509
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1586838793
Short name T538
Test name
Test status
Simulation time 463108484 ps
CPU time 8.8 seconds
Started Apr 28 12:42:15 PM PDT 24
Finished Apr 28 12:42:25 PM PDT 24
Peak memory 208636 kb
Host smart-a811191a-1c44-4599-add1-acb2af75ffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586838793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1586838793
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2616309945
Short name T727
Test name
Test status
Simulation time 124149864 ps
CPU time 2.05 seconds
Started Apr 28 12:42:16 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 209620 kb
Host smart-b760f727-7b5f-49d2-aaeb-877d2fdebdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616309945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2616309945
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3161110226
Short name T642
Test name
Test status
Simulation time 14668234 ps
CPU time 0.93 seconds
Started Apr 28 12:42:24 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 205736 kb
Host smart-35d83e1d-4de4-47f4-ada1-f25e8cee587a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161110226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3161110226
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2508604465
Short name T56
Test name
Test status
Simulation time 1142762989 ps
CPU time 12.97 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:47 PM PDT 24
Peak memory 209204 kb
Host smart-ddf55ee5-65c1-4677-8635-be8cea403a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508604465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2508604465
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1587777090
Short name T653
Test name
Test status
Simulation time 149154041 ps
CPU time 2.24 seconds
Started Apr 28 12:42:28 PM PDT 24
Finished Apr 28 12:42:31 PM PDT 24
Peak memory 208444 kb
Host smart-200df8d8-f2e4-45d2-ac49-898c88dc1799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587777090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1587777090
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1603795603
Short name T821
Test name
Test status
Simulation time 781325314 ps
CPU time 5.69 seconds
Started Apr 28 12:42:16 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 222156 kb
Host smart-9d21ab10-7d93-4e3d-97c5-f5705436327c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603795603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1603795603
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2198653597
Short name T326
Test name
Test status
Simulation time 311293331 ps
CPU time 4.05 seconds
Started Apr 28 12:42:14 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 207876 kb
Host smart-dde07b9b-dd69-4faf-aaf4-843d986b1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198653597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2198653597
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.978864447
Short name T536
Test name
Test status
Simulation time 1268255575 ps
CPU time 40.36 seconds
Started Apr 28 12:42:15 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 208168 kb
Host smart-53b8cef5-2551-4d96-96b6-f2a9ee01fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978864447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.978864447
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3320875544
Short name T287
Test name
Test status
Simulation time 270334240 ps
CPU time 4.32 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 206516 kb
Host smart-11dcc84a-8b59-4609-917f-87d2eccf7722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320875544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3320875544
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1807926302
Short name T559
Test name
Test status
Simulation time 73438078 ps
CPU time 3.65 seconds
Started Apr 28 12:42:26 PM PDT 24
Finished Apr 28 12:42:30 PM PDT 24
Peak memory 206480 kb
Host smart-1a6ba9c2-0dcb-4bda-ba09-57a6c0317769
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807926302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1807926302
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.850406617
Short name T884
Test name
Test status
Simulation time 56231754 ps
CPU time 2.75 seconds
Started Apr 28 12:42:25 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 208368 kb
Host smart-a4307054-126a-4f68-9301-75cf6d7eb0be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850406617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.850406617
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2041543284
Short name T902
Test name
Test status
Simulation time 270895772 ps
CPU time 7.32 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:41 PM PDT 24
Peak memory 208312 kb
Host smart-5a3d4db9-a62e-46f7-a60b-60ebc549ece4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041543284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2041543284
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3007082852
Short name T479
Test name
Test status
Simulation time 162249292 ps
CPU time 2.16 seconds
Started Apr 28 12:42:24 PM PDT 24
Finished Apr 28 12:42:27 PM PDT 24
Peak memory 207180 kb
Host smart-04208e9e-7c72-443e-8c5d-197a462c72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007082852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3007082852
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4006557103
Short name T716
Test name
Test status
Simulation time 259945107 ps
CPU time 3.28 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:42:33 PM PDT 24
Peak memory 208316 kb
Host smart-8bf9836b-bc65-4fce-bf56-d66445f0b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006557103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4006557103
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1904216800
Short name T574
Test name
Test status
Simulation time 93029558 ps
CPU time 4.01 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:36 PM PDT 24
Peak memory 208740 kb
Host smart-3cda0f7d-8c2e-4467-b494-d9b79695fb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904216800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1904216800
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2814824180
Short name T540
Test name
Test status
Simulation time 33951127 ps
CPU time 1.45 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:33 PM PDT 24
Peak memory 208124 kb
Host smart-adc70362-d9c0-4a79-b0fb-c6a971cffee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814824180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2814824180
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2950068471
Short name T621
Test name
Test status
Simulation time 12690838 ps
CPU time 0.89 seconds
Started Apr 28 12:42:24 PM PDT 24
Finished Apr 28 12:42:26 PM PDT 24
Peak memory 205540 kb
Host smart-af14a01d-5588-431e-8177-5544c94301bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950068471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2950068471
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3376328093
Short name T93
Test name
Test status
Simulation time 50900215 ps
CPU time 2.7 seconds
Started Apr 28 12:42:28 PM PDT 24
Finished Apr 28 12:42:31 PM PDT 24
Peak memory 214032 kb
Host smart-2d41766d-7cc0-4e82-b5f5-b07a6124689f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376328093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3376328093
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4265893387
Short name T728
Test name
Test status
Simulation time 2907154746 ps
CPU time 7.54 seconds
Started Apr 28 12:42:26 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 208980 kb
Host smart-f853ab6b-a3da-4c2f-94c5-8bb0a5292e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265893387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4265893387
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4116310681
Short name T785
Test name
Test status
Simulation time 52429588 ps
CPU time 1.97 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 207752 kb
Host smart-0b9ab8b3-ed02-4024-93da-78543c312d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116310681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4116310681
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3853018306
Short name T742
Test name
Test status
Simulation time 286761847 ps
CPU time 4 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 208448 kb
Host smart-4d21f206-238c-45e0-9751-6c9527c43905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853018306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3853018306
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3795103397
Short name T614
Test name
Test status
Simulation time 763709372 ps
CPU time 3.34 seconds
Started Apr 28 12:42:25 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 217608 kb
Host smart-41f94508-c053-4019-8e88-4100d8eaefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795103397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3795103397
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.786562065
Short name T800
Test name
Test status
Simulation time 359889396 ps
CPU time 4.83 seconds
Started Apr 28 12:42:37 PM PDT 24
Finished Apr 28 12:42:42 PM PDT 24
Peak memory 208412 kb
Host smart-30aefe76-bc6a-4c3e-ba41-4b4188faf727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786562065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.786562065
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.664325945
Short name T272
Test name
Test status
Simulation time 1019956568 ps
CPU time 4.36 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:24 PM PDT 24
Peak memory 208432 kb
Host smart-478403b6-8c79-4bc2-9f52-a90a91d5f1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664325945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.664325945
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3507799991
Short name T124
Test name
Test status
Simulation time 11531422613 ps
CPU time 74.31 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 208704 kb
Host smart-88ffc6eb-e1a0-4eb3-9d83-f51ccb943210
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507799991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3507799991
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4146332367
Short name T263
Test name
Test status
Simulation time 60462131 ps
CPU time 3.04 seconds
Started Apr 28 12:42:27 PM PDT 24
Finished Apr 28 12:42:31 PM PDT 24
Peak memory 206632 kb
Host smart-413a5b7e-641f-4f9a-9f73-a78f33921c23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146332367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4146332367
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3576788047
Short name T566
Test name
Test status
Simulation time 1253117775 ps
CPU time 42.65 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:43:35 PM PDT 24
Peak memory 208056 kb
Host smart-9ac522b8-8720-43c4-b236-dc828ee0413b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576788047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3576788047
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.494058266
Short name T585
Test name
Test status
Simulation time 28095548 ps
CPU time 1.76 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:35 PM PDT 24
Peak memory 208964 kb
Host smart-6a91e69c-d5a0-494a-9f40-d8bca39162e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494058266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.494058266
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.198591002
Short name T651
Test name
Test status
Simulation time 239542237 ps
CPU time 3.79 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 206268 kb
Host smart-1e7e5c58-b8ee-4ba1-a236-c9cdaa55d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198591002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.198591002
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3908186605
Short name T865
Test name
Test status
Simulation time 530453647 ps
CPU time 11.15 seconds
Started Apr 28 12:42:17 PM PDT 24
Finished Apr 28 12:42:29 PM PDT 24
Peak memory 222368 kb
Host smart-86389b5f-f711-458b-b05f-1dc033a1b1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908186605 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3908186605
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1498729014
Short name T722
Test name
Test status
Simulation time 100936401 ps
CPU time 4.06 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 209640 kb
Host smart-64e07844-7b3a-4640-8bbe-49a3594a5cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498729014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1498729014
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2564127050
Short name T168
Test name
Test status
Simulation time 113235582 ps
CPU time 1.89 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 209812 kb
Host smart-7867578b-f3a5-4d38-a07e-04bc0faed447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564127050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2564127050
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.187849846
Short name T87
Test name
Test status
Simulation time 33041735 ps
CPU time 1.26 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 205784 kb
Host smart-b4cd0d42-d087-488a-9cab-fa8845202b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187849846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.187849846
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3674690399
Short name T427
Test name
Test status
Simulation time 394190541 ps
CPU time 5.98 seconds
Started Apr 28 12:42:38 PM PDT 24
Finished Apr 28 12:42:45 PM PDT 24
Peak memory 214068 kb
Host smart-c04adbc5-1fbd-4218-a9c0-dc06fc80cd49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674690399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3674690399
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1004918256
Short name T867
Test name
Test status
Simulation time 64050217 ps
CPU time 2.74 seconds
Started Apr 28 12:42:37 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 208684 kb
Host smart-4ded0733-376d-4d85-a484-7e9187fc2a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004918256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1004918256
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3255206178
Short name T567
Test name
Test status
Simulation time 87415297 ps
CPU time 2.98 seconds
Started Apr 28 12:42:36 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 218144 kb
Host smart-d16d1e95-3da7-4ab7-912c-2391f5b897dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255206178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3255206178
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2520709169
Short name T576
Test name
Test status
Simulation time 1194347056 ps
CPU time 6.3 seconds
Started Apr 28 12:42:16 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 221904 kb
Host smart-7234f3e3-78d5-4937-bf6f-41d6df4d4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520709169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2520709169
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2951688972
Short name T890
Test name
Test status
Simulation time 74721442 ps
CPU time 4.11 seconds
Started Apr 28 12:42:30 PM PDT 24
Finished Apr 28 12:42:35 PM PDT 24
Peak memory 220840 kb
Host smart-d360256c-8b02-422d-8a73-6c96b236b5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951688972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2951688972
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3297237113
Short name T744
Test name
Test status
Simulation time 88872442 ps
CPU time 2.49 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 209408 kb
Host smart-e6f71e54-529b-4723-9b46-e45515b9b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297237113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3297237113
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.553015760
Short name T2
Test name
Test status
Simulation time 187083004 ps
CPU time 4.24 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 207672 kb
Host smart-df058b29-2528-47a9-bc73-bfac8d35b9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553015760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.553015760
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2332838799
Short name T768
Test name
Test status
Simulation time 380588844 ps
CPU time 3.53 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 206252 kb
Host smart-9f89086e-38e2-49f3-a935-2d162c08cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332838799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2332838799
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3221091577
Short name T842
Test name
Test status
Simulation time 776667189 ps
CPU time 21.29 seconds
Started Apr 28 12:42:38 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 207988 kb
Host smart-b22f823d-e7eb-42e6-b6a1-e83310223d8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221091577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3221091577
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2741234947
Short name T736
Test name
Test status
Simulation time 86556580 ps
CPU time 2.65 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 206732 kb
Host smart-28cc9f44-25ea-4c75-bd2a-57e1295feb07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741234947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2741234947
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3018451357
Short name T814
Test name
Test status
Simulation time 135268430 ps
CPU time 4.98 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 207428 kb
Host smart-f7c418db-7acf-4341-b977-6b68482197c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018451357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3018451357
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1597233849
Short name T844
Test name
Test status
Simulation time 76965719 ps
CPU time 3.33 seconds
Started Apr 28 12:42:37 PM PDT 24
Finished Apr 28 12:42:41 PM PDT 24
Peak memory 208900 kb
Host smart-d92e24d0-e13f-4216-ba4b-6be9620b0a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597233849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1597233849
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1290027286
Short name T628
Test name
Test status
Simulation time 33758341 ps
CPU time 2.27 seconds
Started Apr 28 12:42:25 PM PDT 24
Finished Apr 28 12:42:28 PM PDT 24
Peak memory 206472 kb
Host smart-67b8960b-c84b-4614-b583-39f8fa98a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290027286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1290027286
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.874547881
Short name T315
Test name
Test status
Simulation time 539989219 ps
CPU time 19.64 seconds
Started Apr 28 12:42:22 PM PDT 24
Finished Apr 28 12:42:42 PM PDT 24
Peak memory 215864 kb
Host smart-637fce25-5de7-4af7-9fdf-174efe5b81f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874547881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.874547881
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2616969745
Short name T311
Test name
Test status
Simulation time 389503703 ps
CPU time 7.36 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 222376 kb
Host smart-1d528e81-e9b7-43ef-8bc3-10db6417f9d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616969745 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2616969745
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1161588807
Short name T895
Test name
Test status
Simulation time 237755742 ps
CPU time 6.74 seconds
Started Apr 28 12:42:32 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 207692 kb
Host smart-434da6ce-d54f-4bc0-89ba-30c8d28faf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161588807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1161588807
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.95675687
Short name T712
Test name
Test status
Simulation time 542116718 ps
CPU time 3.84 seconds
Started Apr 28 12:42:18 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 209864 kb
Host smart-cbbb2ac7-7f5a-4cf4-aabf-805973d7e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95675687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.95675687
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3455535298
Short name T128
Test name
Test status
Simulation time 14938634 ps
CPU time 0.95 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 205668 kb
Host smart-b257ac47-fe4c-477a-bcf0-9f7aa45e5efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455535298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3455535298
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3785346696
Short name T372
Test name
Test status
Simulation time 3976658952 ps
CPU time 12.59 seconds
Started Apr 28 12:41:37 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 214052 kb
Host smart-4e324e21-6720-4800-8056-a36708be24c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785346696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3785346696
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4164565450
Short name T745
Test name
Test status
Simulation time 701126803 ps
CPU time 5.18 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 217156 kb
Host smart-f1fcc39b-5328-48c5-af6a-7bb28549359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164565450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4164565450
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2302720366
Short name T831
Test name
Test status
Simulation time 154648034 ps
CPU time 4.43 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 207732 kb
Host smart-ec90af94-4f11-45fe-990a-b322ed1dd447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302720366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2302720366
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3083003194
Short name T314
Test name
Test status
Simulation time 11721546661 ps
CPU time 27.5 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 214152 kb
Host smart-2ee7067a-ba84-4b2c-ad10-7262edaf81e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083003194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3083003194
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4141144294
Short name T275
Test name
Test status
Simulation time 63915144 ps
CPU time 2.56 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:44 PM PDT 24
Peak memory 213988 kb
Host smart-8b609a7e-375b-4762-8e7c-7edd67125c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141144294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4141144294
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3022964341
Short name T758
Test name
Test status
Simulation time 120788777 ps
CPU time 3.67 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 214092 kb
Host smart-61bd5a2d-36d1-40aa-956d-8dd1747aa0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022964341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3022964341
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.982099356
Short name T627
Test name
Test status
Simulation time 113749985 ps
CPU time 4.51 seconds
Started Apr 28 12:41:38 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 208416 kb
Host smart-2529ff94-035c-4c61-8558-a798e39af502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982099356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.982099356
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3820886163
Short name T379
Test name
Test status
Simulation time 482960497 ps
CPU time 6.86 seconds
Started Apr 28 12:41:39 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 207912 kb
Host smart-1d98a7a0-e0fe-44b2-ba7c-0ca9035067a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820886163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3820886163
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3473265461
Short name T685
Test name
Test status
Simulation time 265480004 ps
CPU time 3.41 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 208328 kb
Host smart-e5b9e345-f023-406b-bd0d-a8da7343ee2a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473265461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3473265461
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1912356046
Short name T369
Test name
Test status
Simulation time 350851675 ps
CPU time 2.85 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 206848 kb
Host smart-1d7c1c92-4a51-4a47-953d-e04ce5e0d82c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912356046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1912356046
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.656624688
Short name T900
Test name
Test status
Simulation time 33823773 ps
CPU time 1.81 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 206388 kb
Host smart-6a3037f6-aa02-4ecb-90bf-6ae75db9a91d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656624688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.656624688
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3336876044
Short name T419
Test name
Test status
Simulation time 371059819 ps
CPU time 4.92 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 208212 kb
Host smart-ad866b1d-3978-4d9e-837a-a763ec642ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336876044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3336876044
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3514274900
Short name T448
Test name
Test status
Simulation time 75532240 ps
CPU time 2.49 seconds
Started Apr 28 12:41:36 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 207928 kb
Host smart-1083dddb-2cf2-4106-ac56-f76fae514ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514274900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3514274900
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1086501334
Short name T298
Test name
Test status
Simulation time 3648197955 ps
CPU time 48.94 seconds
Started Apr 28 12:41:46 PM PDT 24
Finished Apr 28 12:42:36 PM PDT 24
Peak memory 220444 kb
Host smart-46b408d3-8696-4a50-b82c-e9d0519761b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086501334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1086501334
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1981792310
Short name T18
Test name
Test status
Simulation time 6931797465 ps
CPU time 73.56 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 209772 kb
Host smart-62747771-94fb-4e2c-85b9-4591faa07ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981792310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1981792310
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.803071222
Short name T139
Test name
Test status
Simulation time 55721476 ps
CPU time 2.39 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 209684 kb
Host smart-515a25fc-850a-4c0b-85d8-5e6b51f7c82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803071222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.803071222
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3902140527
Short name T720
Test name
Test status
Simulation time 21971989 ps
CPU time 0.75 seconds
Started Apr 28 12:42:44 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 205608 kb
Host smart-f37d8437-4dda-4dff-bf02-4ae2ccdf9887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902140527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3902140527
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1704748731
Short name T126
Test name
Test status
Simulation time 414250060 ps
CPU time 4.71 seconds
Started Apr 28 12:42:32 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 215096 kb
Host smart-c5f886b8-42b9-43ed-8c5c-7f7130bcdd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704748731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1704748731
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1702519330
Short name T31
Test name
Test status
Simulation time 131899920 ps
CPU time 3.11 seconds
Started Apr 28 12:42:48 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 214464 kb
Host smart-a7ce6e69-944b-4f03-a8f3-570dbb4a3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702519330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1702519330
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2973590761
Short name T67
Test name
Test status
Simulation time 49646487 ps
CPU time 2.46 seconds
Started Apr 28 12:42:30 PM PDT 24
Finished Apr 28 12:42:34 PM PDT 24
Peak memory 207076 kb
Host smart-a24ccd2c-0d67-4dc1-a41d-b4a198a0862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973590761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2973590761
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2075201527
Short name T259
Test name
Test status
Simulation time 49301917 ps
CPU time 2.93 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 208344 kb
Host smart-d82a5d7c-b432-414b-b36d-b2d8024138d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075201527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2075201527
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3455237082
Short name T313
Test name
Test status
Simulation time 730518186 ps
CPU time 7.84 seconds
Started Apr 28 12:42:41 PM PDT 24
Finished Apr 28 12:42:49 PM PDT 24
Peak memory 214124 kb
Host smart-de59796b-c3dd-4222-bf2a-c932a1733672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455237082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3455237082
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4087984019
Short name T54
Test name
Test status
Simulation time 53445316 ps
CPU time 3.45 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:42:50 PM PDT 24
Peak memory 209088 kb
Host smart-970c6f45-15c7-4aa0-a9ca-cc2f207aa942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087984019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4087984019
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1083358330
Short name T471
Test name
Test status
Simulation time 124702366 ps
CPU time 3.61 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 208984 kb
Host smart-a8845dcf-cf57-4669-9ec3-65081020679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083358330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1083358330
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1698103846
Short name T285
Test name
Test status
Simulation time 115649565 ps
CPU time 3.94 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 208068 kb
Host smart-937b313b-029a-477b-9298-a479a403cc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698103846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1698103846
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2064832446
Short name T422
Test name
Test status
Simulation time 163234504 ps
CPU time 3.84 seconds
Started Apr 28 12:42:36 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 206492 kb
Host smart-74da4e88-cae4-4c50-b1ba-7c90b5be44c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064832446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2064832446
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3053607282
Short name T92
Test name
Test status
Simulation time 1442534006 ps
CPU time 16.36 seconds
Started Apr 28 12:42:30 PM PDT 24
Finished Apr 28 12:42:47 PM PDT 24
Peak memory 207992 kb
Host smart-ef3b0aaf-1c0a-46d5-aece-ac045faf69bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053607282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3053607282
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.467196634
Short name T787
Test name
Test status
Simulation time 508898127 ps
CPU time 6.43 seconds
Started Apr 28 12:42:36 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 207332 kb
Host smart-535f04d2-5c91-4eab-aa46-8fa25e464b30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467196634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.467196634
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.906789084
Short name T347
Test name
Test status
Simulation time 44782575 ps
CPU time 2.29 seconds
Started Apr 28 12:42:23 PM PDT 24
Finished Apr 28 12:42:27 PM PDT 24
Peak memory 208340 kb
Host smart-0d1523ca-9cd0-47d4-9d7d-5b86205874fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906789084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.906789084
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.964955162
Short name T817
Test name
Test status
Simulation time 94644213 ps
CPU time 2.76 seconds
Started Apr 28 12:42:24 PM PDT 24
Finished Apr 28 12:42:28 PM PDT 24
Peak memory 206276 kb
Host smart-3d6e2a11-b563-45b1-9400-9c1d52bc6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964955162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.964955162
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1939989090
Short name T467
Test name
Test status
Simulation time 535587641 ps
CPU time 16.95 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:42:53 PM PDT 24
Peak memory 216300 kb
Host smart-856eb6e5-a9b1-451c-b9fa-ad7f794f4cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939989090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1939989090
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1143229686
Short name T306
Test name
Test status
Simulation time 2348170037 ps
CPU time 54.67 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:43:41 PM PDT 24
Peak memory 210260 kb
Host smart-24d02f1c-1889-4aee-8f02-37bd9b648d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143229686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1143229686
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.311171175
Short name T514
Test name
Test status
Simulation time 51278106 ps
CPU time 2.58 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:42 PM PDT 24
Peak memory 209636 kb
Host smart-110b149e-f328-4cbb-ad89-ab10acb957af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311171175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.311171175
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.460347453
Short name T889
Test name
Test status
Simulation time 38049183 ps
CPU time 0.74 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:34 PM PDT 24
Peak memory 205604 kb
Host smart-bc766ef6-da0d-4ee3-932c-436636667843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460347453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.460347453
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1123123791
Short name T410
Test name
Test status
Simulation time 639637058 ps
CPU time 4.37 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 214948 kb
Host smart-8f63d3dd-8ff3-4c4e-ab79-5352f2f0e3f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123123791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1123123791
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3332977036
Short name T724
Test name
Test status
Simulation time 290818150 ps
CPU time 7.92 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:43 PM PDT 24
Peak memory 210116 kb
Host smart-2a41a06e-ea0f-4ece-9cc7-f8343f24d380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332977036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3332977036
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2674352763
Short name T53
Test name
Test status
Simulation time 119736219 ps
CPU time 3.59 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 209064 kb
Host smart-cb1d30c5-054f-4ba2-bac1-3734524d5f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674352763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2674352763
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3162413358
Short name T505
Test name
Test status
Simulation time 326945835 ps
CPU time 4.54 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:45 PM PDT 24
Peak memory 220336 kb
Host smart-533b4fb1-3278-4697-b848-08b24e2ac67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162413358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3162413358
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.859552599
Short name T816
Test name
Test status
Simulation time 99827267 ps
CPU time 2.35 seconds
Started Apr 28 12:42:41 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 210400 kb
Host smart-5cec5f49-9820-49fd-b51b-d164e07a2eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859552599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.859552599
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.263404517
Short name T580
Test name
Test status
Simulation time 432164418 ps
CPU time 3.36 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 219328 kb
Host smart-2b8a0766-1e9c-44ca-9d29-41ed965a5bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263404517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.263404517
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1284327177
Short name T609
Test name
Test status
Simulation time 5739329842 ps
CPU time 45.84 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 214072 kb
Host smart-858a503c-dc1e-4ffe-8341-3cc29eecc0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284327177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1284327177
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3192018872
Short name T248
Test name
Test status
Simulation time 201828361 ps
CPU time 5.36 seconds
Started Apr 28 12:42:38 PM PDT 24
Finished Apr 28 12:42:44 PM PDT 24
Peak memory 206328 kb
Host smart-0d47df01-5f33-4d86-a33a-7910d7a423df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192018872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3192018872
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.918765791
Short name T833
Test name
Test status
Simulation time 220787472 ps
CPU time 2.4 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:36 PM PDT 24
Peak memory 206560 kb
Host smart-05a5c8fe-7d6f-4948-84fd-0e1a948e89f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918765791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.918765791
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3903633080
Short name T518
Test name
Test status
Simulation time 520456265 ps
CPU time 4.75 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 207636 kb
Host smart-cc50188b-c869-4785-8a87-1d2a7dcfd8a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903633080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3903633080
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3383717955
Short name T766
Test name
Test status
Simulation time 276700827 ps
CPU time 4.44 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:42:48 PM PDT 24
Peak memory 206476 kb
Host smart-37444094-ccdf-4e51-be0e-65cced539128
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383717955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3383717955
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.380180891
Short name T380
Test name
Test status
Simulation time 276893327 ps
CPU time 2.61 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:35 PM PDT 24
Peak memory 208564 kb
Host smart-bc8e32e0-f7b5-417f-9483-55634873e500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380180891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.380180891
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2835447714
Short name T500
Test name
Test status
Simulation time 227283319 ps
CPU time 3.02 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 208164 kb
Host smart-95b7ecdf-47f9-43a1-ab82-e9937af22286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835447714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2835447714
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2939960922
Short name T743
Test name
Test status
Simulation time 363356652 ps
CPU time 5.51 seconds
Started Apr 28 12:42:37 PM PDT 24
Finished Apr 28 12:42:43 PM PDT 24
Peak memory 222180 kb
Host smart-34bef64f-40ac-490c-97da-5037dceb3306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939960922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2939960922
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2024865168
Short name T116
Test name
Test status
Simulation time 223848981 ps
CPU time 2.71 seconds
Started Apr 28 12:42:29 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 209468 kb
Host smart-7689728c-63cb-4b37-99be-87d53d1c5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024865168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2024865168
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.872243997
Short name T901
Test name
Test status
Simulation time 16193768 ps
CPU time 0.78 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 205608 kb
Host smart-192d65f0-3413-4d72-a666-1a3db862aefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872243997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.872243997
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4220177889
Short name T429
Test name
Test status
Simulation time 301058328 ps
CPU time 14.39 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:54 PM PDT 24
Peak memory 213872 kb
Host smart-c8a7a307-d6cd-4611-9808-4057e5f7804a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220177889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4220177889
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2007353509
Short name T231
Test name
Test status
Simulation time 59418787 ps
CPU time 3.82 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:45 PM PDT 24
Peak memory 209508 kb
Host smart-e5d04cf1-c728-4523-aeac-8e653be7e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007353509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2007353509
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.4262246023
Short name T864
Test name
Test status
Simulation time 257256502 ps
CPU time 1.84 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:42:43 PM PDT 24
Peak memory 207484 kb
Host smart-e45a7c41-99bf-4083-b8df-1f740da49be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262246023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.4262246023
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3937760679
Short name T317
Test name
Test status
Simulation time 525235602 ps
CPU time 9.18 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:42:53 PM PDT 24
Peak memory 213944 kb
Host smart-9d4efe3c-f0d4-45c4-ae33-7e34826fc319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937760679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3937760679
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.506269775
Short name T251
Test name
Test status
Simulation time 393781027 ps
CPU time 10.94 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 222236 kb
Host smart-28876a09-bb93-497e-82f5-5c0b0496febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506269775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.506269775
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.795384993
Short name T891
Test name
Test status
Simulation time 179805398 ps
CPU time 4.15 seconds
Started Apr 28 12:42:42 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 217684 kb
Host smart-6381f680-81ae-4e0e-810f-4b7c895db29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795384993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.795384993
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1359650300
Short name T370
Test name
Test status
Simulation time 211625399 ps
CPU time 3.86 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 217984 kb
Host smart-83496ad3-3d8f-4c25-84d1-06ed63839af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359650300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1359650300
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3527946639
Short name T551
Test name
Test status
Simulation time 1870739173 ps
CPU time 33.49 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 208424 kb
Host smart-14b27a09-3a67-4cb4-abaf-077c4cb55eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527946639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3527946639
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1704684855
Short name T664
Test name
Test status
Simulation time 41022659 ps
CPU time 2.32 seconds
Started Apr 28 12:42:32 PM PDT 24
Finished Apr 28 12:42:35 PM PDT 24
Peak memory 207564 kb
Host smart-f70c328c-dc4c-4244-81cb-c76d73961e91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704684855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1704684855
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2844360193
Short name T632
Test name
Test status
Simulation time 880322488 ps
CPU time 9.02 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:42:45 PM PDT 24
Peak memory 207780 kb
Host smart-a2246955-8df9-446b-aac4-483f9031b16a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844360193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2844360193
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4118852041
Short name T857
Test name
Test status
Simulation time 118374341 ps
CPU time 2.59 seconds
Started Apr 28 12:42:36 PM PDT 24
Finished Apr 28 12:42:40 PM PDT 24
Peak memory 206836 kb
Host smart-40036202-8f11-404e-991d-5edf9ab22c8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118852041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4118852041
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3812865493
Short name T711
Test name
Test status
Simulation time 268525484 ps
CPU time 3.13 seconds
Started Apr 28 12:42:24 PM PDT 24
Finished Apr 28 12:42:28 PM PDT 24
Peak memory 208720 kb
Host smart-c31b1aa7-00b9-4a66-905f-d3bed0b1f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812865493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3812865493
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2164978505
Short name T486
Test name
Test status
Simulation time 48527696 ps
CPU time 1.97 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:35 PM PDT 24
Peak memory 207964 kb
Host smart-ccf50f8f-4e30-482a-8348-449e473e94d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164978505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2164978505
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1723419363
Short name T670
Test name
Test status
Simulation time 1514713676 ps
CPU time 9.25 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:51 PM PDT 24
Peak memory 208736 kb
Host smart-e7593dd2-c5c1-406a-ab4f-5073f279208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723419363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1723419363
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.49645651
Short name T401
Test name
Test status
Simulation time 63405736 ps
CPU time 2.59 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 209500 kb
Host smart-eb484960-9553-400e-885f-8ff8d209b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49645651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.49645651
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.150778351
Short name T790
Test name
Test status
Simulation time 11835464 ps
CPU time 0.83 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:42 PM PDT 24
Peak memory 205508 kb
Host smart-54b0d30e-3d73-4a4f-8400-f4ec7cc06498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150778351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.150778351
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.403242442
Short name T820
Test name
Test status
Simulation time 185625626 ps
CPU time 2.4 seconds
Started Apr 28 12:42:44 PM PDT 24
Finished Apr 28 12:42:47 PM PDT 24
Peak memory 210032 kb
Host smart-b9fc164b-aaa0-4162-abd6-f51e3a4151e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403242442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.403242442
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.319095456
Short name T377
Test name
Test status
Simulation time 586011228 ps
CPU time 2.31 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:43 PM PDT 24
Peak memory 206852 kb
Host smart-189b5c4c-aa85-4308-8585-e231c113f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319095456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.319095456
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1175345197
Short name T84
Test name
Test status
Simulation time 504611286 ps
CPU time 10.01 seconds
Started Apr 28 12:42:42 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 220296 kb
Host smart-5156eb01-f79a-42be-be85-ffd49da17a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175345197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1175345197
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2550992138
Short name T819
Test name
Test status
Simulation time 2080259274 ps
CPU time 57.33 seconds
Started Apr 28 12:42:28 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 222336 kb
Host smart-0897d5c2-506f-4fc0-bb1c-9cb966ebb656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550992138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2550992138
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3168624820
Short name T904
Test name
Test status
Simulation time 142736379 ps
CPU time 1.16 seconds
Started Apr 28 12:42:41 PM PDT 24
Finished Apr 28 12:42:43 PM PDT 24
Peak memory 205816 kb
Host smart-68aa66a2-5fb7-4931-9488-969ae897ad91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168624820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3168624820
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.911471840
Short name T786
Test name
Test status
Simulation time 245356052 ps
CPU time 4.48 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 207036 kb
Host smart-6baf57c5-6c5e-4c03-989d-65960170a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911471840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.911471840
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.969480933
Short name T291
Test name
Test status
Simulation time 303257755 ps
CPU time 5.56 seconds
Started Apr 28 12:42:42 PM PDT 24
Finished Apr 28 12:42:48 PM PDT 24
Peak memory 206812 kb
Host smart-8ec084de-9f36-4893-9d1e-c33b2a55a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969480933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.969480933
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1202313726
Short name T520
Test name
Test status
Simulation time 226409315 ps
CPU time 6.13 seconds
Started Apr 28 12:42:44 PM PDT 24
Finished Apr 28 12:42:51 PM PDT 24
Peak memory 206548 kb
Host smart-6288ca8d-d4a8-434e-adf3-0dccbeffc4a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202313726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1202313726
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1113646786
Short name T611
Test name
Test status
Simulation time 585326037 ps
CPU time 4.92 seconds
Started Apr 28 12:42:31 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 208044 kb
Host smart-abd68d84-cee1-4f6e-ab70-8838921e69c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113646786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1113646786
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.927137885
Short name T827
Test name
Test status
Simulation time 174764745 ps
CPU time 3.51 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:38 PM PDT 24
Peak memory 208272 kb
Host smart-386b0f0c-0e65-476b-9ddc-6a49b29e6f91
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927137885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.927137885
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_smoke.551003578
Short name T537
Test name
Test status
Simulation time 736625540 ps
CPU time 4.98 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 206456 kb
Host smart-4789ea0c-9ffd-42bd-9e7d-6856c217017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551003578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.551003578
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1624901134
Short name T280
Test name
Test status
Simulation time 1422459135 ps
CPU time 12.2 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 216496 kb
Host smart-46fa6737-d878-45af-839f-8bcd333deee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624901134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1624901134
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.805463656
Short name T376
Test name
Test status
Simulation time 492479317 ps
CPU time 5.67 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 214064 kb
Host smart-abc66c2f-ce66-4a6a-a88e-822658a6d85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805463656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.805463656
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1910855987
Short name T97
Test name
Test status
Simulation time 596718998 ps
CPU time 12.47 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:48 PM PDT 24
Peak memory 221132 kb
Host smart-e25a49d3-a0f7-4317-8af7-c20a0f52ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910855987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1910855987
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4119527598
Short name T732
Test name
Test status
Simulation time 15698741 ps
CPU time 0.78 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:42:54 PM PDT 24
Peak memory 205220 kb
Host smart-f4998e6a-495f-4ada-a1de-05e72d113e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119527598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4119527598
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.140851659
Short name T584
Test name
Test status
Simulation time 124165954 ps
CPU time 1.69 seconds
Started Apr 28 12:42:40 PM PDT 24
Finished Apr 28 12:42:43 PM PDT 24
Peak memory 207136 kb
Host smart-ad7231cf-e4dc-4a1b-b138-6f180213a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140851659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.140851659
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2812509932
Short name T81
Test name
Test status
Simulation time 155826906 ps
CPU time 3.88 seconds
Started Apr 28 12:42:34 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 214188 kb
Host smart-0e7ae614-62f2-4138-8159-86a7fdf2f193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812509932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2812509932
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1540723160
Short name T224
Test name
Test status
Simulation time 747381758 ps
CPU time 3.55 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:42:50 PM PDT 24
Peak memory 207872 kb
Host smart-279e9303-abea-4b3f-bf12-f9eaef38fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540723160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1540723160
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2313348240
Short name T294
Test name
Test status
Simulation time 173786347 ps
CPU time 5.65 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 208736 kb
Host smart-9e44e979-a6a4-4593-bb16-24de6812c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313348240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2313348240
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2038009797
Short name T837
Test name
Test status
Simulation time 138985484 ps
CPU time 4.92 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:42:48 PM PDT 24
Peak memory 206340 kb
Host smart-02d58fa4-df0d-48a8-8e19-e695c42eb8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038009797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2038009797
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1417881251
Short name T747
Test name
Test status
Simulation time 37332791 ps
CPU time 1.72 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:42:54 PM PDT 24
Peak memory 206588 kb
Host smart-96db5088-bc5b-4635-856f-692139ca1be0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417881251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1417881251
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.616526279
Short name T483
Test name
Test status
Simulation time 35235818 ps
CPU time 2.62 seconds
Started Apr 28 12:42:35 PM PDT 24
Finished Apr 28 12:42:39 PM PDT 24
Peak memory 206632 kb
Host smart-b80f1307-e7e0-4c42-9c88-cce4a38f9075
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616526279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.616526279
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.149771619
Short name T601
Test name
Test status
Simulation time 159840925 ps
CPU time 4.09 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:42:50 PM PDT 24
Peak memory 208396 kb
Host smart-074b6337-18b7-4f66-b660-b6615cac0895
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149771619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.149771619
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4119377932
Short name T288
Test name
Test status
Simulation time 200717874 ps
CPU time 3.11 seconds
Started Apr 28 12:42:33 PM PDT 24
Finished Apr 28 12:42:37 PM PDT 24
Peak memory 209300 kb
Host smart-fff8acd4-20af-447f-afe5-866fee85cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119377932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4119377932
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2526812709
Short name T457
Test name
Test status
Simulation time 628483462 ps
CPU time 2.82 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 208076 kb
Host smart-18d0f5b5-d8db-4ac6-88da-21f4adb48b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526812709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2526812709
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4187543804
Short name T586
Test name
Test status
Simulation time 380508667 ps
CPU time 10.74 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 216256 kb
Host smart-40f7d21e-c938-4d60-997f-247525d8df60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187543804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4187543804
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.406177592
Short name T129
Test name
Test status
Simulation time 163204153 ps
CPU time 6.56 seconds
Started Apr 28 12:42:54 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 208804 kb
Host smart-2f93dc0a-1679-41c8-8c30-1ae8f205cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406177592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.406177592
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3079056232
Short name T544
Test name
Test status
Simulation time 70291245 ps
CPU time 2.14 seconds
Started Apr 28 12:42:47 PM PDT 24
Finished Apr 28 12:42:50 PM PDT 24
Peak memory 209768 kb
Host smart-0a14b1c7-9361-4bd1-abd7-77cccf8292fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079056232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3079056232
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2588023691
Short name T866
Test name
Test status
Simulation time 21939338 ps
CPU time 0.73 seconds
Started Apr 28 12:42:57 PM PDT 24
Finished Apr 28 12:42:59 PM PDT 24
Peak memory 205708 kb
Host smart-96965c07-9204-41a5-a0fd-1bc43d0e7cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588023691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2588023691
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2666862922
Short name T336
Test name
Test status
Simulation time 27660155 ps
CPU time 2.31 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 213960 kb
Host smart-c4df757c-cf0c-4fb0-b6c6-8923e62ac09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666862922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2666862922
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.94322922
Short name T30
Test name
Test status
Simulation time 322814567 ps
CPU time 3.25 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 221736 kb
Host smart-e06eb933-8360-4a47-ab45-62a202a2711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94322922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.94322922
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3841023699
Short name T588
Test name
Test status
Simulation time 66232684 ps
CPU time 1.7 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 207604 kb
Host smart-30a224b0-eed0-4390-9473-da64f6ed790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841023699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3841023699
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2208775524
Short name T220
Test name
Test status
Simulation time 55061770 ps
CPU time 3.66 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 214116 kb
Host smart-3a40d5fc-95da-43fb-a1dd-8a1243d2da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208775524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2208775524
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.770840124
Short name T227
Test name
Test status
Simulation time 297404024 ps
CPU time 4.88 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 222208 kb
Host smart-42582e4e-a416-4b0f-b440-5b68374a417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770840124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.770840124
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3837875716
Short name T673
Test name
Test status
Simulation time 72908574 ps
CPU time 3.85 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:05 PM PDT 24
Peak memory 214068 kb
Host smart-798189cf-7994-4f9a-b27a-37e656fa10cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837875716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3837875716
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.222651733
Short name T858
Test name
Test status
Simulation time 506229394 ps
CPU time 8.14 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 208280 kb
Host smart-1ba76666-c36a-4d59-9f9b-b28d28754f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222651733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.222651733
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3518539098
Short name T480
Test name
Test status
Simulation time 131320253 ps
CPU time 2.93 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 206652 kb
Host smart-b1addc7f-39a5-4ca5-a426-1589d0676f0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518539098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3518539098
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3552961010
Short name T135
Test name
Test status
Simulation time 154105284 ps
CPU time 3.97 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 206388 kb
Host smart-ccbd25ec-8c35-4493-ada8-cecbb4a8a4ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552961010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3552961010
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2303797262
Short name T803
Test name
Test status
Simulation time 440379237 ps
CPU time 14.85 seconds
Started Apr 28 12:42:39 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 208672 kb
Host smart-093528d0-00c0-4922-bd13-b49f4ba3a52e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303797262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2303797262
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3308771169
Short name T654
Test name
Test status
Simulation time 57306621 ps
CPU time 2.89 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 208284 kb
Host smart-3e0ec384-e8af-4bc2-9b7e-0c1e4c1fb003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308771169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3308771169
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2665948290
Short name T445
Test name
Test status
Simulation time 611652325 ps
CPU time 4.62 seconds
Started Apr 28 12:42:53 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 206188 kb
Host smart-f7e65400-beaa-41b3-bfce-7b8baab75e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665948290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2665948290
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.709907616
Short name T207
Test name
Test status
Simulation time 519492083 ps
CPU time 6.96 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 207876 kb
Host smart-f81f4539-67da-4b88-830a-a87210ebed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709907616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.709907616
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2942035410
Short name T752
Test name
Test status
Simulation time 76301070 ps
CPU time 2.93 seconds
Started Apr 28 12:42:58 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 209724 kb
Host smart-9a3c11d9-673f-4b8e-bc37-e20ad64177d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942035410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2942035410
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.267686349
Short name T13
Test name
Test status
Simulation time 66565513 ps
CPU time 0.9 seconds
Started Apr 28 12:42:45 PM PDT 24
Finished Apr 28 12:42:47 PM PDT 24
Peak memory 205760 kb
Host smart-d6c1744a-d9de-4fe7-80d8-b35f124829ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267686349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.267686349
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3990451055
Short name T425
Test name
Test status
Simulation time 206077400 ps
CPU time 10.21 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 214044 kb
Host smart-78a3df35-e466-45f6-909a-46a3fc0aa613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990451055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3990451055
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4236339393
Short name T674
Test name
Test status
Simulation time 2263751421 ps
CPU time 18.94 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 222468 kb
Host smart-632fa48c-c66c-4449-91d7-985c97653b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236339393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4236339393
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1439630021
Short name T555
Test name
Test status
Simulation time 102297324 ps
CPU time 2 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 218212 kb
Host smart-2e0c1351-becc-4a77-91ed-ad2695b330da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439630021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1439630021
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2596019770
Short name T754
Test name
Test status
Simulation time 110855865 ps
CPU time 4.29 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:14 PM PDT 24
Peak memory 214252 kb
Host smart-d6242936-124d-4985-8232-2ef1ae598a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596019770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2596019770
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_random.2837008599
Short name T509
Test name
Test status
Simulation time 277355295 ps
CPU time 5.84 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 209548 kb
Host smart-ce0427c8-d187-4937-89d3-a13b6a163894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837008599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2837008599
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2909297884
Short name T622
Test name
Test status
Simulation time 1177709893 ps
CPU time 13.08 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 207492 kb
Host smart-f4d69c24-9796-4165-b9ac-dbe9541beb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909297884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2909297884
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3671147633
Short name T474
Test name
Test status
Simulation time 133526605 ps
CPU time 3.4 seconds
Started Apr 28 12:42:46 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 207892 kb
Host smart-7a7504e3-3bc3-49e0-a77a-41ef8665bbb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671147633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3671147633
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1203607799
Short name T577
Test name
Test status
Simulation time 850974632 ps
CPU time 3.67 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 206272 kb
Host smart-e6d5b0f4-f569-4f57-ae13-c95109ea7626
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203607799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1203607799
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.273987178
Short name T459
Test name
Test status
Simulation time 67846695 ps
CPU time 3.33 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:14 PM PDT 24
Peak memory 208112 kb
Host smart-f9ec4269-b2b1-4d6d-951b-40f26b1c6c78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273987178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.273987178
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.767954403
Short name T729
Test name
Test status
Simulation time 162650166 ps
CPU time 2.36 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 209320 kb
Host smart-1a6ba9a1-156e-4f36-9d92-3af5aa57e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767954403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.767954403
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1803221748
Short name T452
Test name
Test status
Simulation time 64007746 ps
CPU time 2.25 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 206376 kb
Host smart-1e23e2d6-0bc8-49de-9850-2034b6a127f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803221748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1803221748
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.799677304
Short name T348
Test name
Test status
Simulation time 50460962481 ps
CPU time 481.41 seconds
Started Apr 28 12:42:43 PM PDT 24
Finished Apr 28 12:50:46 PM PDT 24
Peak memory 219564 kb
Host smart-eaefee29-b939-4c68-ad1b-c47550f98235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799677304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.799677304
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2820948272
Short name T130
Test name
Test status
Simulation time 1073339349 ps
CPU time 21.78 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 222428 kb
Host smart-1dcba39e-9634-44bf-ac88-19efb88f8f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820948272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2820948272
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3939405216
Short name T375
Test name
Test status
Simulation time 110857496 ps
CPU time 3.85 seconds
Started Apr 28 12:42:44 PM PDT 24
Finished Apr 28 12:42:49 PM PDT 24
Peak memory 207876 kb
Host smart-2ca77853-772e-43a9-a99c-ca7f0f64b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939405216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3939405216
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2881066838
Short name T181
Test name
Test status
Simulation time 51781187 ps
CPU time 2.28 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:05 PM PDT 24
Peak memory 209612 kb
Host smart-f55174a2-28b2-47d3-bd20-483c31d540b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881066838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2881066838
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1232359032
Short name T550
Test name
Test status
Simulation time 71022997 ps
CPU time 0.83 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 205540 kb
Host smart-460b5254-a1f5-43f5-a262-5296f041d127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232359032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1232359032
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3155500150
Short name T332
Test name
Test status
Simulation time 67484170 ps
CPU time 2.75 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:42:58 PM PDT 24
Peak memory 213964 kb
Host smart-31fd1015-609b-4634-a330-1b751bf33f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155500150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3155500150
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1118634663
Short name T195
Test name
Test status
Simulation time 123714259 ps
CPU time 5.67 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 208488 kb
Host smart-625aeb2b-4c1e-4d46-8ebb-0c19ab0cd42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118634663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1118634663
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3729604502
Short name T795
Test name
Test status
Simulation time 47910623 ps
CPU time 2.33 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 213984 kb
Host smart-92fcefde-ddc5-4500-b070-86495f2edd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729604502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3729604502
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2352289503
Short name T338
Test name
Test status
Simulation time 153637528 ps
CPU time 5.81 seconds
Started Apr 28 12:42:48 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 222192 kb
Host smart-24f63a14-c542-421d-869c-cec360ae33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352289503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2352289503
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3174038825
Short name T523
Test name
Test status
Simulation time 149364771 ps
CPU time 3.92 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 213888 kb
Host smart-6bfbc6e1-787f-4165-8f09-ce7c753784d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174038825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3174038825
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.846047781
Short name T604
Test name
Test status
Simulation time 53630497 ps
CPU time 3.43 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 214088 kb
Host smart-563816ea-310c-4d65-99c5-a88bc1149130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846047781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.846047781
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.377298402
Short name T391
Test name
Test status
Simulation time 421633381 ps
CPU time 3.57 seconds
Started Apr 28 12:42:48 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 206420 kb
Host smart-c1715bb2-1ff9-4029-b891-466e11639d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377298402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.377298402
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.532477402
Short name T859
Test name
Test status
Simulation time 925582264 ps
CPU time 6.79 seconds
Started Apr 28 12:42:54 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 207516 kb
Host smart-25184939-6a0a-4baa-9ce8-3b45a64e7517
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532477402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.532477402
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3212354279
Short name T810
Test name
Test status
Simulation time 100506367 ps
CPU time 3.52 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 206344 kb
Host smart-b7262ead-6cee-4762-b2b8-a8a4d16d0ecb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212354279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3212354279
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2945095856
Short name T341
Test name
Test status
Simulation time 31133837 ps
CPU time 2.27 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 208252 kb
Host smart-a8f99ff9-e370-4e9c-9693-40a2e5cfeb46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945095856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2945095856
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3660927120
Short name T698
Test name
Test status
Simulation time 70648996 ps
CPU time 2.93 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 214864 kb
Host smart-e2bd4cff-e6c4-4754-a08e-12c4ff90642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660927120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3660927120
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3387133029
Short name T470
Test name
Test status
Simulation time 33237323 ps
CPU time 2.28 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 206456 kb
Host smart-3095a324-71fc-43ea-90d8-e507855d6fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387133029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3387133029
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3052410151
Short name T236
Test name
Test status
Simulation time 7650903746 ps
CPU time 78.11 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:44:16 PM PDT 24
Peak memory 222232 kb
Host smart-d0f3515e-fad3-4dfe-8597-c733e68bd999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052410151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3052410151
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4069528689
Short name T398
Test name
Test status
Simulation time 248882045 ps
CPU time 3.63 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 206416 kb
Host smart-66301a04-852e-45fb-8a50-85a11a859585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069528689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4069528689
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2900756443
Short name T562
Test name
Test status
Simulation time 168335726 ps
CPU time 2.8 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 209420 kb
Host smart-4a32f90a-4a3e-46c9-aa67-8d6ec2229d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900756443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2900756443
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.700439886
Short name T708
Test name
Test status
Simulation time 40801361 ps
CPU time 0.81 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 205692 kb
Host smart-a796b0f3-aa9c-46b7-aa9c-8c3cf4cc99c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700439886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.700439886
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.919921590
Short name T109
Test name
Test status
Simulation time 160217570 ps
CPU time 8.75 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 222184 kb
Host smart-887c1b29-bccc-4acf-a56d-57a81f4053f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919921590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.919921590
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3357157225
Short name T55
Test name
Test status
Simulation time 1622231131 ps
CPU time 21.14 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 214220 kb
Host smart-7245499c-521c-44b1-bfbf-0f520d2f508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357157225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3357157225
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.126093077
Short name T508
Test name
Test status
Simulation time 93830081 ps
CPU time 1.57 seconds
Started Apr 28 12:42:48 PM PDT 24
Finished Apr 28 12:42:51 PM PDT 24
Peak memory 206924 kb
Host smart-b47aacd2-b4ef-4d45-bf86-231bb5ab95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126093077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.126093077
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2765179141
Short name T26
Test name
Test status
Simulation time 118327235 ps
CPU time 5.4 seconds
Started Apr 28 12:42:58 PM PDT 24
Finished Apr 28 12:43:05 PM PDT 24
Peak memory 220488 kb
Host smart-7d897c73-8029-42a3-b0e1-656c58ef2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765179141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2765179141
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2414737768
Short name T851
Test name
Test status
Simulation time 77078542 ps
CPU time 4.1 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 210804 kb
Host smart-e60a9149-59ac-4629-a251-d38bf9377879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414737768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2414737768
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2963745847
Short name T475
Test name
Test status
Simulation time 104848882 ps
CPU time 4.2 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 218912 kb
Host smart-fd4845fd-5927-431d-a6d0-5ae6e18b252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963745847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2963745847
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2139108679
Short name T271
Test name
Test status
Simulation time 109568845 ps
CPU time 3.93 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 207584 kb
Host smart-efdc5879-8785-4591-94ad-97b7b101a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139108679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2139108679
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3706787676
Short name T352
Test name
Test status
Simulation time 197123471 ps
CPU time 5.93 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 206316 kb
Host smart-db0a32d0-b0df-4f30-9fab-00b4dbab011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706787676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3706787676
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3900986316
Short name T14
Test name
Test status
Simulation time 77401692 ps
CPU time 2.37 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 206320 kb
Host smart-6d075a41-5fc3-4f6f-b434-e896a20a5fd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900986316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3900986316
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2662659553
Short name T218
Test name
Test status
Simulation time 122675190 ps
CPU time 1.85 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:42:59 PM PDT 24
Peak memory 206504 kb
Host smart-73be477f-fee5-468d-af77-6d451e890c0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662659553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2662659553
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3751083985
Short name T547
Test name
Test status
Simulation time 2270976330 ps
CPU time 29.19 seconds
Started Apr 28 12:42:48 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 207768 kb
Host smart-78ac33b1-9ebf-4dfa-86a5-b516df96a9c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751083985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3751083985
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2525933746
Short name T516
Test name
Test status
Simulation time 62447377 ps
CPU time 2.61 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 209640 kb
Host smart-7b2ca088-d1fb-4daa-bbc5-c5103558d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525933746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2525933746
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2050108134
Short name T578
Test name
Test status
Simulation time 306107342 ps
CPU time 6.01 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 206508 kb
Host smart-84f173f4-f07d-4e14-95f6-629d664e9132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050108134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2050108134
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1589302857
Short name T141
Test name
Test status
Simulation time 1986192880 ps
CPU time 11.72 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 214604 kb
Host smart-b0ef6259-ce4b-497c-9692-5496dcf23768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589302857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1589302857
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.869808376
Short name T896
Test name
Test status
Simulation time 3413792717 ps
CPU time 75.24 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 208688 kb
Host smart-fde7d47f-2cb0-4d7a-901e-879dddf9a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869808376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.869808376
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2663971773
Short name T469
Test name
Test status
Simulation time 80732787 ps
CPU time 0.84 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 205652 kb
Host smart-a8a1ca9d-a915-47bf-ad10-27bb0a419391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663971773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2663971773
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1432904025
Short name T405
Test name
Test status
Simulation time 66702706 ps
CPU time 2.55 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 214012 kb
Host smart-b6ba2f2f-052c-481a-a587-b63bad752895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432904025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1432904025
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4073260705
Short name T20
Test name
Test status
Simulation time 82944545 ps
CPU time 3.03 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 214328 kb
Host smart-05e6256a-6ca5-4ed6-a1c4-3032c6375246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073260705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4073260705
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2950624977
Short name T132
Test name
Test status
Simulation time 366655401 ps
CPU time 3.01 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 209676 kb
Host smart-945e5482-6ebe-4317-a0a7-e9909d86c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950624977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2950624977
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1033087354
Short name T49
Test name
Test status
Simulation time 2907548833 ps
CPU time 23.15 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:43:21 PM PDT 24
Peak memory 222372 kb
Host smart-b56d2876-a75f-4e4e-a2e6-5a5f35a2cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033087354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1033087354
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3117713689
Short name T482
Test name
Test status
Simulation time 120456040 ps
CPU time 5.23 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 209344 kb
Host smart-f8b68a75-e89f-4476-b46d-9899be91dbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117713689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3117713689
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4207078023
Short name T594
Test name
Test status
Simulation time 313707108 ps
CPU time 6.6 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 208764 kb
Host smart-ac438074-3d47-44b3-b810-46a4a441b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207078023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4207078023
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.929876048
Short name T527
Test name
Test status
Simulation time 67066409 ps
CPU time 2.9 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 208484 kb
Host smart-6bf44eb3-0cae-477d-9d00-0253106dc248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929876048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.929876048
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3983310916
Short name T494
Test name
Test status
Simulation time 134387496 ps
CPU time 3.69 seconds
Started Apr 28 12:42:51 PM PDT 24
Finished Apr 28 12:42:58 PM PDT 24
Peak memory 208060 kb
Host smart-5bc1e341-dbc8-473b-aa1f-d7bd149af240
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983310916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3983310916
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1198897094
Short name T606
Test name
Test status
Simulation time 438329690 ps
CPU time 3.7 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 208372 kb
Host smart-23805350-b21a-4d74-98cc-9f43e10d7194
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198897094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1198897094
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4061951049
Short name T373
Test name
Test status
Simulation time 863142260 ps
CPU time 9.44 seconds
Started Apr 28 12:42:52 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 207440 kb
Host smart-a7f44bbc-d126-4aa7-8583-0bb080034b41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061951049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4061951049
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.587853078
Short name T529
Test name
Test status
Simulation time 60153053 ps
CPU time 1.75 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 209276 kb
Host smart-a61733c5-1211-466d-ae82-484aaef7d8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587853078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.587853078
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2227941922
Short name T780
Test name
Test status
Simulation time 257768378 ps
CPU time 5.48 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 206564 kb
Host smart-8c48669c-cd1a-4cb1-8a09-52e290fdfdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227941922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2227941922
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1529103085
Short name T95
Test name
Test status
Simulation time 185241420 ps
CPU time 5.32 seconds
Started Apr 28 12:42:57 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 209536 kb
Host smart-76ee33ec-578f-40d4-a3c8-0778b20f16f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529103085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1529103085
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3175543733
Short name T515
Test name
Test status
Simulation time 2699762254 ps
CPU time 6.45 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 210580 kb
Host smart-bbc85e8b-283c-4441-beb4-c5d3303040aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175543733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3175543733
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2648708373
Short name T446
Test name
Test status
Simulation time 34938300 ps
CPU time 0.85 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 205520 kb
Host smart-78af53d0-277e-4232-a16f-1cb16c113d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648708373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2648708373
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1799719633
Short name T675
Test name
Test status
Simulation time 88525552 ps
CPU time 3.54 seconds
Started Apr 28 12:41:47 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 210676 kb
Host smart-1954d3ba-3fdb-4668-ab64-80dd72350e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799719633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1799719633
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2406775729
Short name T775
Test name
Test status
Simulation time 1314743471 ps
CPU time 24.43 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:22 PM PDT 24
Peak memory 208448 kb
Host smart-3b7ad552-4a5f-4ef5-8f1b-ef5db070eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406775729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2406775729
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1092175825
Short name T643
Test name
Test status
Simulation time 411625018 ps
CPU time 7.16 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 214172 kb
Host smart-d1866914-c87c-4933-a8bd-de7a80a5331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092175825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1092175825
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.302961290
Short name T48
Test name
Test status
Simulation time 114999744 ps
CPU time 3.03 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 209608 kb
Host smart-b466f694-b768-4627-83e5-f09971a4adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302961290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.302961290
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4178435476
Short name T462
Test name
Test status
Simulation time 432269670 ps
CPU time 3.78 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:44 PM PDT 24
Peak memory 207204 kb
Host smart-969c21d7-c777-4e92-8322-66be0845dbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178435476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4178435476
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1468569790
Short name T89
Test name
Test status
Simulation time 1158756972 ps
CPU time 15.86 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:15 PM PDT 24
Peak memory 236024 kb
Host smart-ff1f5b08-e5a5-40a4-b526-8d0c0b1c5610
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468569790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1468569790
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4074899415
Short name T213
Test name
Test status
Simulation time 285716344 ps
CPU time 3.4 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 206376 kb
Host smart-97416a27-9418-4706-b831-cd81f6a852ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074899415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4074899415
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3683053984
Short name T357
Test name
Test status
Simulation time 1189714713 ps
CPU time 4.82 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 206568 kb
Host smart-a239d700-7217-41f4-9a8e-38f5bd8561b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683053984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3683053984
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2435085575
Short name T334
Test name
Test status
Simulation time 227743734 ps
CPU time 8.06 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 208312 kb
Host smart-f709fea1-6a95-4f64-aa68-70cf28f4019e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435085575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2435085575
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.832878538
Short name T886
Test name
Test status
Simulation time 106713120 ps
CPU time 2.67 seconds
Started Apr 28 12:41:37 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 206588 kb
Host smart-275c330e-7a2a-488c-8fa3-a2d5f30cbd88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832878538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.832878538
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.667577927
Short name T592
Test name
Test status
Simulation time 508458832 ps
CPU time 5.16 seconds
Started Apr 28 12:41:45 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 207756 kb
Host smart-997d7f9d-ecda-44fd-92fb-36853fd2ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667577927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.667577927
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1990325673
Short name T624
Test name
Test status
Simulation time 186221898 ps
CPU time 5.29 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 206152 kb
Host smart-f2d51dce-4c51-4dc2-8b6e-803bb02af66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990325673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1990325673
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1000391799
Short name T875
Test name
Test status
Simulation time 5289516999 ps
CPU time 66.95 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:42:52 PM PDT 24
Peak memory 214140 kb
Host smart-9df22946-24cc-4de7-ba3d-b17213ee8df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000391799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1000391799
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.370798341
Short name T893
Test name
Test status
Simulation time 99643093 ps
CPU time 1.93 seconds
Started Apr 28 12:41:45 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 209344 kb
Host smart-02f36f2d-4e70-43b9-ac3c-d76c062d2cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370798341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.370798341
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3999035181
Short name T91
Test name
Test status
Simulation time 11848006 ps
CPU time 0.75 seconds
Started Apr 28 12:42:58 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 205608 kb
Host smart-e9d862ec-3174-4e32-a274-5c295e9b7c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999035181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3999035181
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.484381699
Short name T610
Test name
Test status
Simulation time 81917690 ps
CPU time 3.58 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 208300 kb
Host smart-b71e8811-c8ce-448e-9372-ae26795faad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484381699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.484381699
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4046012682
Short name T880
Test name
Test status
Simulation time 48611661 ps
CPU time 2.44 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 209412 kb
Host smart-f26d9e3d-14f6-485b-840a-e73c8b190d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046012682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4046012682
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2232801602
Short name T83
Test name
Test status
Simulation time 1493160693 ps
CPU time 5.64 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 222264 kb
Host smart-0f1e04cd-e016-4198-92fa-5f2dfceb7e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232801602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2232801602
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2707621407
Short name T278
Test name
Test status
Simulation time 207033766 ps
CPU time 3.56 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 222136 kb
Host smart-8c64dc31-dcc1-492b-9cb0-6ab6549c3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707621407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2707621407
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.202485011
Short name T134
Test name
Test status
Simulation time 918230019 ps
CPU time 5.27 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 214024 kb
Host smart-137bfd85-5b61-4a03-8f76-e15df0821315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202485011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.202485011
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1082842836
Short name T836
Test name
Test status
Simulation time 1377248959 ps
CPU time 9.55 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 206376 kb
Host smart-dc9f8232-c073-46b7-8f6e-0dd365e6da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082842836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1082842836
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2586557429
Short name T389
Test name
Test status
Simulation time 106698008 ps
CPU time 2.93 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 208156 kb
Host smart-6b3f6f3a-1b14-4b13-b41a-c57a81a56333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586557429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2586557429
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2765694965
Short name T573
Test name
Test status
Simulation time 385058334 ps
CPU time 3.3 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 206552 kb
Host smart-db471fca-51b1-4213-ba00-c2a71fea357d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765694965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2765694965
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1667097667
Short name T194
Test name
Test status
Simulation time 132140600 ps
CPU time 2.86 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 206544 kb
Host smart-9e8c1f4a-9774-457b-a928-91792de432ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667097667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1667097667
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2576655160
Short name T903
Test name
Test status
Simulation time 125199828 ps
CPU time 3.32 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 208096 kb
Host smart-05e17fde-7f37-4f58-a759-6cc9fa90cadc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576655160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2576655160
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.66673222
Short name T719
Test name
Test status
Simulation time 160093722 ps
CPU time 4.52 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 208352 kb
Host smart-dc9e7a9c-b906-4010-8474-115acd0e78cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66673222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.66673222
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1007277180
Short name T210
Test name
Test status
Simulation time 122198784 ps
CPU time 3.47 seconds
Started Apr 28 12:42:58 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 208040 kb
Host smart-c878eda6-527e-4132-ae47-ba710a62193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007277180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1007277180
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1788146694
Short name T663
Test name
Test status
Simulation time 211054464 ps
CPU time 3.73 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:05 PM PDT 24
Peak memory 214080 kb
Host smart-4f313b36-307f-4966-973b-19eea7d96ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788146694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1788146694
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4155835689
Short name T715
Test name
Test status
Simulation time 44444311 ps
CPU time 0.71 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 205708 kb
Host smart-d0c48d26-ff92-439b-9089-c8e754fda13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155835689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4155835689
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1572939229
Short name T579
Test name
Test status
Simulation time 583770610 ps
CPU time 4.33 seconds
Started Apr 28 12:42:53 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 208736 kb
Host smart-bd3039d0-cfda-4418-bb3e-2da1072187f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572939229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1572939229
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.908491493
Short name T561
Test name
Test status
Simulation time 874206212 ps
CPU time 2.86 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 209232 kb
Host smart-4e85cc3a-2136-4be8-ae41-62ca17a53621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908491493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.908491493
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.940987966
Short name T862
Test name
Test status
Simulation time 262548542 ps
CPU time 3.27 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 208804 kb
Host smart-c7d0ef0f-280a-4774-a1f1-4f8794faf9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940987966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.940987966
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2165454209
Short name T342
Test name
Test status
Simulation time 400239624 ps
CPU time 3.72 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:55 PM PDT 24
Peak memory 220420 kb
Host smart-45f8fee9-b498-4ff6-a01e-066787ec0e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165454209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2165454209
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.179236177
Short name T705
Test name
Test status
Simulation time 1345184126 ps
CPU time 5.69 seconds
Started Apr 28 12:43:18 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 210036 kb
Host smart-d3dc1dcd-d5cf-4522-b098-f2a6329cb379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179236177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.179236177
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2984340323
Short name T599
Test name
Test status
Simulation time 22016974 ps
CPU time 1.88 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 206772 kb
Host smart-2de39e40-21ca-4383-8498-f0510a2f9323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984340323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2984340323
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.156700934
Short name T721
Test name
Test status
Simulation time 42679331 ps
CPU time 2.32 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 207508 kb
Host smart-8e91d1e7-e63a-4f91-9b68-96cc1c236526
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156700934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.156700934
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.953454023
Short name T572
Test name
Test status
Simulation time 200485736 ps
CPU time 7.05 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 207756 kb
Host smart-50955102-451b-414e-8696-a7ffb0721a13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953454023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.953454023
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3425120173
Short name T524
Test name
Test status
Simulation time 559656437 ps
CPU time 6.18 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 207788 kb
Host smart-31efb6e8-49aa-4dfd-8314-353f79269524
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425120173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3425120173
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2177876019
Short name T463
Test name
Test status
Simulation time 2759806556 ps
CPU time 13.37 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 218048 kb
Host smart-5b492479-962b-4755-aa46-2d358f7ef876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177876019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2177876019
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3126979840
Short name T456
Test name
Test status
Simulation time 2324366708 ps
CPU time 58.5 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 218308 kb
Host smart-a8c1c0be-0d0a-43a2-b803-14c44775e48d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126979840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3126979840
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.221123917
Short name T770
Test name
Test status
Simulation time 188530903 ps
CPU time 3.02 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 206584 kb
Host smart-d25f38ec-ba89-49a5-83a6-d156d7b72333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221123917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.221123917
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1300033146
Short name T689
Test name
Test status
Simulation time 132815159 ps
CPU time 3.25 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 210020 kb
Host smart-9929e641-6acd-40aa-968a-b746b4fea32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300033146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1300033146
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.550721846
Short name T454
Test name
Test status
Simulation time 14220134 ps
CPU time 0.9 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 205848 kb
Host smart-e9682ee2-e5de-4999-b7df-968c264f1fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550721846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.550721846
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2818803327
Short name T393
Test name
Test status
Simulation time 116483145 ps
CPU time 4.27 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 215224 kb
Host smart-b76fd86f-fdb1-4a90-b359-2cbd685ce3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818803327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2818803327
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1190583706
Short name T726
Test name
Test status
Simulation time 132770406 ps
CPU time 4.1 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 214028 kb
Host smart-5f6d1e1e-0358-4219-a401-1617f5589e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190583706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1190583706
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1173079276
Short name T382
Test name
Test status
Simulation time 92958053 ps
CPU time 3.11 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 208320 kb
Host smart-15568581-5cce-44bc-b01b-f5bd4ae5324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173079276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1173079276
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3155047463
Short name T250
Test name
Test status
Simulation time 76563387 ps
CPU time 4.59 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 214672 kb
Host smart-50159f51-80aa-4405-a6c6-a09f131901b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155047463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3155047463
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.232630855
Short name T235
Test name
Test status
Simulation time 137985956 ps
CPU time 4.07 seconds
Started Apr 28 12:42:57 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 209252 kb
Host smart-c8845844-428d-4279-abe4-d3cc97c715f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232630855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.232630855
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.748970012
Short name T262
Test name
Test status
Simulation time 663383657 ps
CPU time 4.52 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 218376 kb
Host smart-dfb91389-c5c5-450b-a2f8-fcaf413affed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748970012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.748970012
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3618842573
Short name T905
Test name
Test status
Simulation time 31992433 ps
CPU time 2.26 seconds
Started Apr 28 12:43:15 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 206264 kb
Host smart-c9beb78f-a1e7-476e-9f0e-5eb3cb47f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618842573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3618842573
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1756624989
Short name T834
Test name
Test status
Simulation time 46898461 ps
CPU time 1.98 seconds
Started Apr 28 12:42:55 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 208324 kb
Host smart-0b492403-efd9-4ceb-90c9-f66ce743b1af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756624989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1756624989
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1307912762
Short name T714
Test name
Test status
Simulation time 394664776 ps
CPU time 3.08 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 207968 kb
Host smart-102fa9df-3217-4d4a-a365-fd709f416c54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307912762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1307912762
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2741562742
Short name T549
Test name
Test status
Simulation time 378628811 ps
CPU time 4.91 seconds
Started Apr 28 12:42:49 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 206608 kb
Host smart-9a468949-0c4c-4516-82e4-5c695e2a746b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741562742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2741562742
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.122921855
Short name T793
Test name
Test status
Simulation time 149769805 ps
CPU time 3.87 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 208244 kb
Host smart-9f77a40d-0954-4c1b-8097-53a309703e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122921855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.122921855
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2729948546
Short name T94
Test name
Test status
Simulation time 48418651 ps
CPU time 2.51 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 206856 kb
Host smart-b5a2d7a3-24bf-4802-b26d-ac4651be8911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729948546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2729948546
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1873759623
Short name T575
Test name
Test status
Simulation time 123130618 ps
CPU time 3.72 seconds
Started Apr 28 12:42:56 PM PDT 24
Finished Apr 28 12:43:02 PM PDT 24
Peak memory 222288 kb
Host smart-cd90de45-6ea5-4fef-a51e-8819f0fd68aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873759623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1873759623
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2933866983
Short name T70
Test name
Test status
Simulation time 1149729353 ps
CPU time 8.19 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 208776 kb
Host smart-db032f63-371e-441c-8451-a3f42aecd65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933866983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2933866983
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4207677299
Short name T176
Test name
Test status
Simulation time 243705743 ps
CPU time 3.34 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 210564 kb
Host smart-9b90a749-402b-4b9e-a5b1-44d2341c1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207677299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4207677299
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3648701189
Short name T86
Test name
Test status
Simulation time 7662121 ps
CPU time 0.8 seconds
Started Apr 28 12:43:17 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 205672 kb
Host smart-ae019bf3-f738-4897-a9eb-4f6fb4ae8cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648701189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3648701189
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3985448854
Short name T260
Test name
Test status
Simulation time 566522815 ps
CPU time 8.84 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 215408 kb
Host smart-550af0b6-fc5b-498b-8ef1-1f65a8646b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985448854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3985448854
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2069222126
Short name T809
Test name
Test status
Simulation time 112484747 ps
CPU time 4.69 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 209584 kb
Host smart-032a048a-19b5-482a-bea6-ca829d4bb7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069222126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2069222126
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3287269779
Short name T703
Test name
Test status
Simulation time 476280373 ps
CPU time 3.9 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 208520 kb
Host smart-6f338577-38e3-439d-bcd7-91d5e84e0986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287269779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3287269779
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3021377736
Short name T82
Test name
Test status
Simulation time 2510670593 ps
CPU time 10.84 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 209292 kb
Host smart-365be69a-379f-44bc-8f8a-8b12450a6036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021377736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3021377736
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4108468057
Short name T883
Test name
Test status
Simulation time 2774522390 ps
CPU time 5.94 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 222156 kb
Host smart-a24a1cb6-069c-4800-b809-f0521fd09e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108468057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4108468057
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.431304546
Short name T695
Test name
Test status
Simulation time 325926752 ps
CPU time 2.81 seconds
Started Apr 28 12:42:53 PM PDT 24
Finished Apr 28 12:42:58 PM PDT 24
Peak memory 215632 kb
Host smart-1b81ba56-7132-4875-9018-ed2e698f0b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431304546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.431304546
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2526493218
Short name T659
Test name
Test status
Simulation time 1728170948 ps
CPU time 4.42 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 207812 kb
Host smart-3a555d5a-0d86-4819-9c22-a446485a3074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526493218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2526493218
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3635930352
Short name T423
Test name
Test status
Simulation time 156051420 ps
CPU time 4.03 seconds
Started Apr 28 12:42:59 PM PDT 24
Finished Apr 28 12:43:04 PM PDT 24
Peak memory 207608 kb
Host smart-ed0d26c5-352a-4ce2-8cc9-1e01048b0f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635930352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3635930352
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.708928099
Short name T598
Test name
Test status
Simulation time 217274029 ps
CPU time 7.6 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 206284 kb
Host smart-43c05776-fe62-4588-81d8-7533236dede4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708928099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.708928099
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2554108297
Short name T501
Test name
Test status
Simulation time 469664166 ps
CPU time 9.24 seconds
Started Apr 28 12:43:00 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 208360 kb
Host smart-a5d3f5c5-82b1-4cba-8f37-fb0060fd1872
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554108297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2554108297
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.502230107
Short name T813
Test name
Test status
Simulation time 58445543 ps
CPU time 2.22 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 206384 kb
Host smart-e489c9be-62ec-42cd-92e0-a9f96c488bf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502230107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.502230107
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2566836205
Short name T385
Test name
Test status
Simulation time 4009888314 ps
CPU time 38.15 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:48 PM PDT 24
Peak memory 220776 kb
Host smart-114885ca-dced-496a-94ee-b5eed365065d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566836205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2566836205
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1719594671
Short name T507
Test name
Test status
Simulation time 737657980 ps
CPU time 7.62 seconds
Started Apr 28 12:42:53 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 206372 kb
Host smart-59a29195-6e11-49c0-85da-258402de874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719594671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1719594671
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2936703288
Short name T869
Test name
Test status
Simulation time 633714001 ps
CPU time 21.71 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:27 PM PDT 24
Peak memory 220456 kb
Host smart-28201e77-074b-4a79-86f3-df97184c2510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936703288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2936703288
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1480717498
Short name T684
Test name
Test status
Simulation time 406754328 ps
CPU time 2.98 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 209680 kb
Host smart-2243964d-5a55-4e61-9b5b-1ace4b0b5c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480717498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1480717498
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3533319825
Short name T476
Test name
Test status
Simulation time 16258883 ps
CPU time 0.83 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 205608 kb
Host smart-4a22e5ec-8e04-4c76-a807-f0a935e99e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533319825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3533319825
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.132770442
Short name T436
Test name
Test status
Simulation time 62721297 ps
CPU time 4.27 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 215200 kb
Host smart-fce8b3b2-a74f-4005-ac93-e8592df91b1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132770442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.132770442
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2627896156
Short name T127
Test name
Test status
Simulation time 162395362 ps
CPU time 4.01 seconds
Started Apr 28 12:43:13 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 214100 kb
Host smart-ec14c801-6f17-488e-8530-29786232d0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627896156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2627896156
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3075429412
Short name T616
Test name
Test status
Simulation time 230560627 ps
CPU time 3.25 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:06 PM PDT 24
Peak memory 208964 kb
Host smart-e7a1d2a1-d441-4d35-b63b-7112cfb1c9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075429412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3075429412
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2912675890
Short name T319
Test name
Test status
Simulation time 142957437 ps
CPU time 3.02 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 220324 kb
Host smart-0a25045a-644f-43bb-992f-24f064ef1c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912675890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2912675890
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.228833296
Short name T746
Test name
Test status
Simulation time 372351677 ps
CPU time 4.18 seconds
Started Apr 28 12:43:02 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 207496 kb
Host smart-076c1228-5b74-49e7-b467-98aba16f6e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228833296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.228833296
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3348184326
Short name T355
Test name
Test status
Simulation time 823541073 ps
CPU time 7.19 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 207532 kb
Host smart-6165b5cb-4048-4142-9c49-256725300b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348184326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3348184326
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3737807707
Short name T371
Test name
Test status
Simulation time 799412548 ps
CPU time 21.12 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:30 PM PDT 24
Peak memory 207464 kb
Host smart-0be7ac79-fb71-4975-beca-0d0d105fc27c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737807707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3737807707
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2089143023
Short name T681
Test name
Test status
Simulation time 2759456640 ps
CPU time 6.14 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 208768 kb
Host smart-8b4c4420-c222-48d4-8b67-5be058d77751
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089143023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2089143023
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1390474632
Short name T846
Test name
Test status
Simulation time 20708439 ps
CPU time 1.9 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 206356 kb
Host smart-08babd64-56bd-4738-a2d8-4aeea2658bf0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390474632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1390474632
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1196892046
Short name T75
Test name
Test status
Simulation time 338025354 ps
CPU time 4.39 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 209280 kb
Host smart-14a2de43-e58b-4762-8ad7-88d4db0152e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196892046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1196892046
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1671701948
Short name T71
Test name
Test status
Simulation time 195989190 ps
CPU time 6.71 seconds
Started Apr 28 12:42:50 PM PDT 24
Finished Apr 28 12:43:00 PM PDT 24
Peak memory 207948 kb
Host smart-2dc7e3f2-b367-4eac-a882-e4be14d2f2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671701948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1671701948
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1032260667
Short name T687
Test name
Test status
Simulation time 152580584 ps
CPU time 7.98 seconds
Started Apr 28 12:43:18 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 215904 kb
Host smart-6b6cc4ea-fddc-468d-b095-d6b42dc31377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032260667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1032260667
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2767429321
Short name T367
Test name
Test status
Simulation time 1170701380 ps
CPU time 8.31 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 209120 kb
Host smart-cdf1c59f-8a61-4b98-ba20-c364de759005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767429321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2767429321
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4116949234
Short name T593
Test name
Test status
Simulation time 177963721 ps
CPU time 2.86 seconds
Started Apr 28 12:43:04 PM PDT 24
Finished Apr 28 12:43:09 PM PDT 24
Peak memory 210164 kb
Host smart-ddde8bf2-d2a8-421e-b605-ae6e16f402b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116949234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4116949234
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2796230128
Short name T600
Test name
Test status
Simulation time 22931890 ps
CPU time 0.77 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 205640 kb
Host smart-81477fc9-31e1-4fb6-88f3-36e3bef7e2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796230128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2796230128
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3215486070
Short name T269
Test name
Test status
Simulation time 78546498 ps
CPU time 4.22 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 214020 kb
Host smart-5cf238f7-5641-4d1c-a2d7-4cb7202beaf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215486070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3215486070
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1100514494
Short name T10
Test name
Test status
Simulation time 93938210 ps
CPU time 4.21 seconds
Started Apr 28 12:43:01 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 218896 kb
Host smart-8d259e79-b4cb-4c48-805f-6bd5f230da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100514494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1100514494
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1756878710
Short name T581
Test name
Test status
Simulation time 136544471 ps
CPU time 3.61 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 207104 kb
Host smart-066032bd-3da7-417a-864f-199616e0bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756878710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1756878710
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1007125129
Short name T848
Test name
Test status
Simulation time 106822467 ps
CPU time 4.02 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 208348 kb
Host smart-fb29a664-2f07-423e-a230-b4e18764fbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007125129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1007125129
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2992138595
Short name T397
Test name
Test status
Simulation time 6637941408 ps
CPU time 11.28 seconds
Started Apr 28 12:43:17 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 209808 kb
Host smart-39e44dfe-4d1c-40c3-8104-6c82b9d6899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992138595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2992138595
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3683405112
Short name T433
Test name
Test status
Simulation time 373590560 ps
CPU time 3.83 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 219684 kb
Host smart-daff7409-b97e-46be-9352-d1ee29d37d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683405112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3683405112
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2924414791
Short name T556
Test name
Test status
Simulation time 1695508745 ps
CPU time 31.85 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:42 PM PDT 24
Peak memory 208344 kb
Host smart-261fdab5-a2b0-4561-a2d6-252e37b238f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924414791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2924414791
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3417646930
Short name T669
Test name
Test status
Simulation time 155191006 ps
CPU time 4.97 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 208448 kb
Host smart-47dd339b-bf22-4315-bdc3-dac9994cc7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417646930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3417646930
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2828540444
Short name T748
Test name
Test status
Simulation time 235731823 ps
CPU time 2.92 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 208184 kb
Host smart-75417374-fb0b-40f3-baab-f4cd2e6d4cd5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828540444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2828540444
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1445447250
Short name T492
Test name
Test status
Simulation time 270488546 ps
CPU time 3.88 seconds
Started Apr 28 12:43:18 PM PDT 24
Finished Apr 28 12:43:23 PM PDT 24
Peak memory 207760 kb
Host smart-49320baa-5e8b-4d87-8b17-8ca946665e50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445447250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1445447250
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1708782757
Short name T219
Test name
Test status
Simulation time 145692395 ps
CPU time 3.5 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:27 PM PDT 24
Peak memory 208496 kb
Host smart-492d00fb-e700-42f1-8198-ec7a8a27c054
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708782757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1708782757
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2207774295
Short name T835
Test name
Test status
Simulation time 228051407 ps
CPU time 2.54 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 214112 kb
Host smart-2477f00a-b48c-4bdd-aef9-dd2a2bb10290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207774295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2207774295
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1182912497
Short name T461
Test name
Test status
Simulation time 3434297850 ps
CPU time 34.45 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 208256 kb
Host smart-eaaae01a-9e26-4abc-a1a3-69733b92342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182912497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1182912497
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1886896715
Short name T186
Test name
Test status
Simulation time 1927421359 ps
CPU time 21.17 seconds
Started Apr 28 12:43:19 PM PDT 24
Finished Apr 28 12:43:41 PM PDT 24
Peak memory 222448 kb
Host smart-0e4dfe3c-ab8f-44b1-9663-b5a48e55379a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886896715 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1886896715
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2992101731
Short name T343
Test name
Test status
Simulation time 171496684 ps
CPU time 2.83 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:10 PM PDT 24
Peak memory 214012 kb
Host smart-638feae1-bdb8-4bc9-ae22-4abe624325fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992101731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2992101731
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.848148661
Short name T466
Test name
Test status
Simulation time 397959722 ps
CPU time 2.6 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 209640 kb
Host smart-8eaaeef6-5c16-4ef9-92ef-420a11f08378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848148661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.848148661
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2937558548
Short name T557
Test name
Test status
Simulation time 21866972 ps
CPU time 0.73 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 205536 kb
Host smart-c404e263-2d10-4418-87d8-52beda9697ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937558548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2937558548
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3749591822
Short name T349
Test name
Test status
Simulation time 172264178 ps
CPU time 9.64 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:23 PM PDT 24
Peak memory 214840 kb
Host smart-123934bd-b102-431e-9756-4573a4bb072a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3749591822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3749591822
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.646043109
Short name T191
Test name
Test status
Simulation time 165960333 ps
CPU time 2.86 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 214000 kb
Host smart-cfae802f-3714-4534-b8d4-31fcd4582e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646043109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.646043109
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1870700717
Short name T68
Test name
Test status
Simulation time 276691544 ps
CPU time 2.04 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 206340 kb
Host smart-73f430a1-3d79-4a25-8a09-e9fdc861cdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870700717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1870700717
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1558792634
Short name T607
Test name
Test status
Simulation time 536462207 ps
CPU time 5.78 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 219380 kb
Host smart-5ff20b5a-50b9-41ff-8a88-e575f3e9f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558792634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1558792634
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.977016060
Short name T513
Test name
Test status
Simulation time 383776812 ps
CPU time 3.34 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 214048 kb
Host smart-72e6f190-deb1-4a26-a976-c09c9479f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977016060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.977016060
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1808218756
Short name T535
Test name
Test status
Simulation time 471077081 ps
CPU time 5.36 seconds
Started Apr 28 12:43:06 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 207192 kb
Host smart-3bdefd26-e3b6-4751-9d97-012ebfd5c28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808218756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1808218756
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.998106470
Short name T791
Test name
Test status
Simulation time 121705332 ps
CPU time 4.05 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 206436 kb
Host smart-7f133750-9c21-44db-ae7e-36b2ca0d108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998106470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.998106470
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3419529178
Short name T522
Test name
Test status
Simulation time 528397006 ps
CPU time 5.92 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 208256 kb
Host smart-b5a493bd-ba7e-48d9-83f1-17907ec8a4ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419529178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3419529178
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4001828421
Short name T424
Test name
Test status
Simulation time 878704183 ps
CPU time 6.72 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:21 PM PDT 24
Peak memory 208052 kb
Host smart-2ffc8437-3760-4156-87b4-781dec646e8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001828421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4001828421
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4110796832
Short name T223
Test name
Test status
Simulation time 126665988 ps
CPU time 5.38 seconds
Started Apr 28 12:43:20 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 206568 kb
Host smart-0fc8b11d-1cdb-45a7-8813-5b65ae25b1f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110796832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4110796832
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.77354847
Short name T499
Test name
Test status
Simulation time 226190672 ps
CPU time 2.99 seconds
Started Apr 28 12:43:05 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 208976 kb
Host smart-929da1e4-1755-4c63-8a38-8a9f15ab240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77354847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.77354847
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.22440091
Short name T519
Test name
Test status
Simulation time 29648763 ps
CPU time 2.13 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:14 PM PDT 24
Peak memory 205816 kb
Host smart-4a73f704-8e99-439b-896d-e60408f4570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22440091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.22440091
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.239032241
Short name T200
Test name
Test status
Simulation time 2356513677 ps
CPU time 3.11 seconds
Started Apr 28 12:43:03 PM PDT 24
Finished Apr 28 12:43:08 PM PDT 24
Peak memory 206380 kb
Host smart-0b59f3d6-541e-4b98-ba03-8ecd13618c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239032241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.239032241
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3191591694
Short name T350
Test name
Test status
Simulation time 186420343 ps
CPU time 3.14 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 213956 kb
Host smart-4265c742-aa48-4752-b55f-1cb8255f0450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191591694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3191591694
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.969391838
Short name T570
Test name
Test status
Simulation time 1746910561 ps
CPU time 10.08 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:21 PM PDT 24
Peak memory 210500 kb
Host smart-f8de4742-f5d9-4ff5-855b-e0ac1d14b8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969391838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.969391838
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.413258322
Short name T449
Test name
Test status
Simulation time 90191637 ps
CPU time 0.86 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:12 PM PDT 24
Peak memory 205700 kb
Host smart-f60e296d-0b65-49e7-a210-ac3ad1885cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413258322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.413258322
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3671875568
Short name T142
Test name
Test status
Simulation time 56983197 ps
CPU time 3.95 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 214764 kb
Host smart-5f8d247e-69ca-48cb-b862-81b6cdf7f6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671875568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3671875568
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3697625894
Short name T37
Test name
Test status
Simulation time 448356118 ps
CPU time 3.34 seconds
Started Apr 28 12:43:15 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 209448 kb
Host smart-62022249-ae30-477f-813a-45186a462670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697625894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3697625894
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3342434189
Short name T707
Test name
Test status
Simulation time 208402110 ps
CPU time 6.17 seconds
Started Apr 28 12:43:14 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 213980 kb
Host smart-ff0e83a7-58ad-4083-a725-69123b6f1e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342434189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3342434189
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.80850605
Short name T80
Test name
Test status
Simulation time 241852820 ps
CPU time 4.29 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 208448 kb
Host smart-59fb398b-c781-4096-b395-19644cc47379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80850605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.80850605
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.781066872
Short name T4
Test name
Test status
Simulation time 1906430444 ps
CPU time 38.24 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:50 PM PDT 24
Peak memory 222240 kb
Host smart-0668630a-6c99-4de1-b5cd-a15e9e221abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781066872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.781066872
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1890574668
Short name T671
Test name
Test status
Simulation time 90566921 ps
CPU time 3.99 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 222360 kb
Host smart-a646ba11-edf6-4a46-9bee-937486f49586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890574668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1890574668
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.921242330
Short name T354
Test name
Test status
Simulation time 122017661 ps
CPU time 3.4 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 207548 kb
Host smart-9032ca6b-dfaf-4139-8a89-4dd28e00aad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921242330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.921242330
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.633475940
Short name T290
Test name
Test status
Simulation time 867388095 ps
CPU time 7.02 seconds
Started Apr 28 12:43:13 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 208336 kb
Host smart-cb31807e-01fc-43b8-9330-7709118e8495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633475940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.633475940
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3298469082
Short name T383
Test name
Test status
Simulation time 71177768 ps
CPU time 3.23 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 208108 kb
Host smart-0e71d531-4afc-4c65-abce-cf5d133d1c77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298469082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3298469082
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.87173265
Short name T138
Test name
Test status
Simulation time 20604195631 ps
CPU time 93.36 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 207960 kb
Host smart-a0546a6a-6458-4598-998f-5c8cd933865d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87173265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.87173265
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.582571069
Short name T760
Test name
Test status
Simulation time 1554540301 ps
CPU time 10.5 seconds
Started Apr 28 12:43:14 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 208116 kb
Host smart-f8e38383-6d07-460a-aba9-93e3caf7c641
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582571069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.582571069
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1216943691
Short name T652
Test name
Test status
Simulation time 84654355 ps
CPU time 3.48 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 209060 kb
Host smart-4d6daeae-3639-46eb-8b85-24f6ce217313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216943691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1216943691
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.408091643
Short name T525
Test name
Test status
Simulation time 19807887 ps
CPU time 1.74 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:23 PM PDT 24
Peak memory 206248 kb
Host smart-e5b8ca8e-cd6c-4d49-be00-4237c148480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408091643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.408091643
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2013389081
Short name T66
Test name
Test status
Simulation time 2486906871 ps
CPU time 47.57 seconds
Started Apr 28 12:43:13 PM PDT 24
Finished Apr 28 12:44:03 PM PDT 24
Peak memory 214992 kb
Host smart-9163c4ae-e9c0-43e5-b27a-86eef9f94e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013389081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2013389081
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.506484119
Short name T119
Test name
Test status
Simulation time 467291441 ps
CPU time 26.93 seconds
Started Apr 28 12:43:31 PM PDT 24
Finished Apr 28 12:43:58 PM PDT 24
Peak memory 222404 kb
Host smart-c6be66e4-95c0-420c-b660-facff73d4413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506484119 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.506484119
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4128092066
Short name T682
Test name
Test status
Simulation time 223027111 ps
CPU time 2.75 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 207504 kb
Host smart-a24d61dc-c569-4870-b034-05d0c1124ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128092066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4128092066
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1815802382
Short name T169
Test name
Test status
Simulation time 214030207 ps
CPU time 2.48 seconds
Started Apr 28 12:43:16 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 209856 kb
Host smart-8a7028c0-d720-4812-9b18-de304ee13e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815802382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1815802382
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1335232094
Short name T635
Test name
Test status
Simulation time 9141900 ps
CPU time 0.71 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 205596 kb
Host smart-ebc90c1a-1107-4d0f-bd8a-03ca1f58e642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335232094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1335232094
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3447108728
Short name T144
Test name
Test status
Simulation time 191806959 ps
CPU time 3.66 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 213992 kb
Host smart-c8cfd0c1-6e7f-469d-b5f1-bf1bb1e4b839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447108728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3447108728
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2259436578
Short name T702
Test name
Test status
Simulation time 836091762 ps
CPU time 7.38 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 213880 kb
Host smart-192fe603-e85f-4cf0-981b-93a033e93259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259436578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2259436578
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3007808112
Short name T582
Test name
Test status
Simulation time 22199636 ps
CPU time 1.29 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:31 PM PDT 24
Peak memory 206476 kb
Host smart-f46dccf7-e1cc-4b39-9858-94d3e1213f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007808112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3007808112
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3964067295
Short name T847
Test name
Test status
Simulation time 329408967 ps
CPU time 8.38 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:23 PM PDT 24
Peak memory 222160 kb
Host smart-1fa0d70c-f46a-425e-8d40-09d372ff1790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964067295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3964067295
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1513316779
Short name T796
Test name
Test status
Simulation time 59522747 ps
CPU time 3.82 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 214124 kb
Host smart-83472c4b-e305-44cf-b077-a3d468d3f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513316779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1513316779
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.55131637
Short name T617
Test name
Test status
Simulation time 54223966 ps
CPU time 2.52 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:13 PM PDT 24
Peak memory 219532 kb
Host smart-b0c40e07-0245-4013-8185-e96adee61684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55131637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.55131637
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1547286199
Short name T264
Test name
Test status
Simulation time 183993148 ps
CPU time 5.58 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 207212 kb
Host smart-08ccc09a-a908-4e8f-a028-b1795faa85f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547286199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1547286199
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2774856851
Short name T569
Test name
Test status
Simulation time 282364561 ps
CPU time 3.19 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 206440 kb
Host smart-39981d6b-8e2c-41e0-bd31-7ad2c030e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774856851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2774856851
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3641186919
Short name T273
Test name
Test status
Simulation time 3196293908 ps
CPU time 21.23 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 207484 kb
Host smart-88415b50-fe27-400a-9b59-61dd9f91ae76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641186919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3641186919
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1379145768
Short name T730
Test name
Test status
Simulation time 48700040 ps
CPU time 2.84 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 208152 kb
Host smart-b74f402a-9d79-4a37-9fb9-8d1e259d4620
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379145768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1379145768
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3873224144
Short name T881
Test name
Test status
Simulation time 267480275 ps
CPU time 4.15 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 215844 kb
Host smart-99d7cd7c-5cf4-46ac-9649-1ae6042fccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873224144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3873224144
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1686987144
Short name T490
Test name
Test status
Simulation time 870929075 ps
CPU time 4.88 seconds
Started Apr 28 12:43:22 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 206208 kb
Host smart-7a9c2bfa-cc1c-47e2-aa64-88971d269de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686987144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1686987144
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2865754760
Short name T807
Test name
Test status
Simulation time 134578278 ps
CPU time 3.89 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 214108 kb
Host smart-4cabe22c-8030-4298-a590-2c354592f5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865754760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2865754760
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2930499194
Short name T418
Test name
Test status
Simulation time 4005767887 ps
CPU time 47.24 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 208208 kb
Host smart-6b09066a-8b2a-4283-9865-ad5c0c44c2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930499194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2930499194
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4252318673
Short name T170
Test name
Test status
Simulation time 152175539 ps
CPU time 3.36 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 209956 kb
Host smart-8139b0fd-09b3-4b43-b195-52a3502f6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252318673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4252318673
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4051126708
Short name T668
Test name
Test status
Simulation time 16844967 ps
CPU time 0.84 seconds
Started Apr 28 12:43:14 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 205640 kb
Host smart-1c949458-7550-4b17-892c-a1cb9cb814bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051126708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4051126708
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3939412374
Short name T428
Test name
Test status
Simulation time 49144743 ps
CPU time 3.21 seconds
Started Apr 28 12:43:07 PM PDT 24
Finished Apr 28 12:43:14 PM PDT 24
Peak memory 215196 kb
Host smart-e8b00698-eca6-4a4f-a99b-b9515f595009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939412374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3939412374
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3697589664
Short name T133
Test name
Test status
Simulation time 58823937 ps
CPU time 2.13 seconds
Started Apr 28 12:43:18 PM PDT 24
Finished Apr 28 12:43:21 PM PDT 24
Peak memory 207624 kb
Host smart-cffb2483-4aa9-41fc-b6ef-49d7a58d7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697589664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3697589664
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1590197723
Short name T737
Test name
Test status
Simulation time 457287949 ps
CPU time 5.82 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 207864 kb
Host smart-5f9a884b-92c6-4c50-8847-fa9a6c6f8ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590197723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1590197723
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.865664391
Short name T845
Test name
Test status
Simulation time 1239168599 ps
CPU time 12.72 seconds
Started Apr 28 12:43:19 PM PDT 24
Finished Apr 28 12:43:32 PM PDT 24
Peak memory 220896 kb
Host smart-cf5e5569-0c65-4164-9874-99d1f25f0ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865664391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.865664391
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1652842107
Short name T465
Test name
Test status
Simulation time 172851104 ps
CPU time 3.87 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 215728 kb
Host smart-623994ac-5cf3-4156-a747-61f40f7bff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652842107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1652842107
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.4266576254
Short name T697
Test name
Test status
Simulation time 1213288699 ps
CPU time 17.83 seconds
Started Apr 28 12:43:13 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 208596 kb
Host smart-1eaf4bc1-9576-4638-9959-26da24b96e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266576254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4266576254
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2733996328
Short name T696
Test name
Test status
Simulation time 1382589259 ps
CPU time 3.55 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 206292 kb
Host smart-6801e775-d2f0-496a-a3ce-899bff3340e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733996328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2733996328
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4234592533
Short name T613
Test name
Test status
Simulation time 22940556 ps
CPU time 1.89 seconds
Started Apr 28 12:43:08 PM PDT 24
Finished Apr 28 12:43:15 PM PDT 24
Peak memory 206896 kb
Host smart-b2380983-37db-4e7a-b79e-13071e29c128
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234592533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4234592533
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2947518063
Short name T72
Test name
Test status
Simulation time 116280083 ps
CPU time 4.59 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 208244 kb
Host smart-6bbbfa77-ebe5-4d8f-8118-44eaeaa66da7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947518063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2947518063
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3496447784
Short name T526
Test name
Test status
Simulation time 82531312 ps
CPU time 3.41 seconds
Started Apr 28 12:43:22 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 207096 kb
Host smart-8a0f38e7-40df-47a7-85b8-e2cf4deebec6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496447784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3496447784
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3695676812
Short name T545
Test name
Test status
Simulation time 46245983 ps
CPU time 1.96 seconds
Started Apr 28 12:43:19 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 208012 kb
Host smart-2a349916-2e13-4393-89db-c1ebf191b593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695676812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3695676812
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2091273750
Short name T1
Test name
Test status
Simulation time 64566628 ps
CPU time 2.43 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 208128 kb
Host smart-9836ef61-1f01-421e-84e8-e6f116d181a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091273750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2091273750
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1478709682
Short name T202
Test name
Test status
Simulation time 4338574455 ps
CPU time 96.91 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 217008 kb
Host smart-2aad16b6-f692-4742-bfeb-f699b6e822de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478709682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1478709682
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3798243476
Short name T645
Test name
Test status
Simulation time 125097550 ps
CPU time 3.61 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:17 PM PDT 24
Peak memory 206612 kb
Host smart-94bf7fab-42f5-4833-aa87-bf456b2178c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798243476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3798243476
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1678992009
Short name T762
Test name
Test status
Simulation time 4220412648 ps
CPU time 10.09 seconds
Started Apr 28 12:43:14 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 210320 kb
Host smart-693c08a8-b2fb-4912-98e5-9e8c56fb0aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678992009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1678992009
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.537590913
Short name T782
Test name
Test status
Simulation time 9845693 ps
CPU time 0.77 seconds
Started Apr 28 12:41:51 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 205576 kb
Host smart-a3ca4c6b-0796-4369-aa7e-69e3e6069ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537590913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.537590913
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.701975919
Short name T333
Test name
Test status
Simulation time 67386269 ps
CPU time 4.38 seconds
Started Apr 28 12:41:37 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 213952 kb
Host smart-b2751068-4ecf-4561-b249-ea2db9b733d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701975919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.701975919
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.955425088
Short name T420
Test name
Test status
Simulation time 64936180 ps
CPU time 1.49 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 214048 kb
Host smart-8aeddc2b-b448-43cf-b819-3b1f0a456a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955425088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.955425088
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2847974625
Short name T23
Test name
Test status
Simulation time 1710979942 ps
CPU time 53.2 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:42:49 PM PDT 24
Peak memory 213912 kb
Host smart-2fc0bc04-5ef8-451b-85dc-fddc793ec0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847974625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2847974625
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1813788634
Short name T256
Test name
Test status
Simulation time 3659333937 ps
CPU time 24.94 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:42:10 PM PDT 24
Peak memory 214064 kb
Host smart-a008c0b3-7312-4324-a8e1-c19d202de330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813788634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1813788634
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2866956281
Short name T620
Test name
Test status
Simulation time 349529547 ps
CPU time 5.53 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 220040 kb
Host smart-6b944bd8-4f04-4555-91ff-9c70ce8fbaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866956281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2866956281
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4027496595
Short name T778
Test name
Test status
Simulation time 686620669 ps
CPU time 4.65 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:41:55 PM PDT 24
Peak memory 208700 kb
Host smart-98840abd-43b5-4ed0-89fa-28771bf84fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027496595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4027496595
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.4058221025
Short name T12
Test name
Test status
Simulation time 6617408687 ps
CPU time 131.04 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 262624 kb
Host smart-b477aa30-b044-4881-9176-6e14f486a7c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058221025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4058221025
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3269173501
Short name T447
Test name
Test status
Simulation time 317163264 ps
CPU time 3.52 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 206444 kb
Host smart-218e6139-4851-4114-8a43-e58af5620347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269173501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3269173501
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4094175646
Short name T327
Test name
Test status
Simulation time 36926318 ps
CPU time 2.6 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 208048 kb
Host smart-ab1e2b44-8e46-4725-948e-6a288b18cc56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094175646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4094175646
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.639886875
Short name T472
Test name
Test status
Simulation time 412846358 ps
CPU time 5.01 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 207108 kb
Host smart-d88631c9-9310-4455-9cee-c7c07ebd3429
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639886875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.639886875
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.329209268
Short name T805
Test name
Test status
Simulation time 335919778 ps
CPU time 6.98 seconds
Started Apr 28 12:41:39 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 207816 kb
Host smart-c6fb25f9-b2f1-4be3-9ab1-e1f421dfdef7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329209268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.329209268
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2119414122
Short name T693
Test name
Test status
Simulation time 446738032 ps
CPU time 1.78 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 208708 kb
Host smart-f8677f91-9a28-41d0-bc55-24f9a70b7f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119414122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2119414122
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.960143114
Short name T504
Test name
Test status
Simulation time 95903093 ps
CPU time 2.29 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 206828 kb
Host smart-bedcc906-96b1-45c7-a3ab-3a96d772d6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960143114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.960143114
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.531661580
Short name T90
Test name
Test status
Simulation time 241559981 ps
CPU time 3.54 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 207812 kb
Host smart-bf0a415a-e62c-40ec-a82e-6667c81cd7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531661580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.531661580
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2781313914
Short name T96
Test name
Test status
Simulation time 250636698 ps
CPU time 3.24 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 210068 kb
Host smart-22cd1189-d55a-4d58-8de8-ba3f2a78fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781313914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2781313914
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2490711319
Short name T690
Test name
Test status
Simulation time 14912713 ps
CPU time 0.92 seconds
Started Apr 28 12:43:33 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 205700 kb
Host smart-63d12bb6-d44b-4202-8011-dcee12cb06de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490711319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2490711319
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2894015968
Short name T242
Test name
Test status
Simulation time 468466796 ps
CPU time 4.52 seconds
Started Apr 28 12:43:24 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 210300 kb
Host smart-d5d5f971-6bb7-4520-851c-0440abf393c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894015968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2894015968
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2695848773
Short name T61
Test name
Test status
Simulation time 230886137 ps
CPU time 4.82 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 208728 kb
Host smart-5f44156a-39f7-40b5-a7f0-5f997ca2d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695848773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2695848773
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4289590564
Short name T353
Test name
Test status
Simulation time 217825754 ps
CPU time 2.63 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 218612 kb
Host smart-150c9036-0c02-4f15-b39f-8dccb6c5f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289590564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4289590564
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.356562928
Short name T359
Test name
Test status
Simulation time 62528772 ps
CPU time 3.68 seconds
Started Apr 28 12:43:24 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 210984 kb
Host smart-3af28d71-4082-4b83-a197-3402600b8b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356562928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.356562928
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2521927573
Short name T460
Test name
Test status
Simulation time 274942331 ps
CPU time 4.22 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 219972 kb
Host smart-ff51022a-0fc7-45b4-8597-8756566d358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521927573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2521927573
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.100767235
Short name T330
Test name
Test status
Simulation time 333505462 ps
CPU time 4.37 seconds
Started Apr 28 12:43:18 PM PDT 24
Finished Apr 28 12:43:23 PM PDT 24
Peak memory 208316 kb
Host smart-a17512ee-7bc7-4494-945d-afd280adf958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100767235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.100767235
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.317699180
Short name T595
Test name
Test status
Simulation time 5057522827 ps
CPU time 23.72 seconds
Started Apr 28 12:43:10 PM PDT 24
Finished Apr 28 12:43:38 PM PDT 24
Peak memory 207748 kb
Host smart-53f5ae47-73c7-4730-a02f-87444399d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317699180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.317699180
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2351174833
Short name T261
Test name
Test status
Simulation time 869331429 ps
CPU time 6.2 seconds
Started Apr 28 12:43:11 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 208192 kb
Host smart-2f4e3900-b273-4269-93fd-fb37828e0d88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351174833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2351174833
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2361631627
Short name T583
Test name
Test status
Simulation time 68065182 ps
CPU time 3.3 seconds
Started Apr 28 12:43:09 PM PDT 24
Finished Apr 28 12:43:16 PM PDT 24
Peak memory 206520 kb
Host smart-f5d59ab4-528a-42e9-964d-b6294f8b6307
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361631627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2361631627
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2418892477
Short name T589
Test name
Test status
Simulation time 1027013879 ps
CPU time 14.53 seconds
Started Apr 28 12:43:20 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 214080 kb
Host smart-d8e30db6-9c9f-4062-8224-66070284b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418892477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2418892477
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1595334225
Short name T74
Test name
Test status
Simulation time 28526832 ps
CPU time 2.04 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 207952 kb
Host smart-c8dbc953-ea6a-49cc-ada8-257a350413dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595334225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1595334225
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3425374992
Short name T117
Test name
Test status
Simulation time 178161971 ps
CPU time 7.55 seconds
Started Apr 28 12:43:12 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 222300 kb
Host smart-5f9611de-1430-4267-89a1-942923b3ff37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425374992 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3425374992
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3700121449
Short name T677
Test name
Test status
Simulation time 682661135 ps
CPU time 7.9 seconds
Started Apr 28 12:43:38 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 207080 kb
Host smart-f0e945f4-76c8-49e9-9e0a-0c8002222647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700121449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3700121449
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3768248555
Short name T167
Test name
Test status
Simulation time 53830027 ps
CPU time 2.5 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 209632 kb
Host smart-fb764282-7a78-43ad-8609-2c2aabc404f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768248555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3768248555
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3668468457
Short name T618
Test name
Test status
Simulation time 21176494 ps
CPU time 0.75 seconds
Started Apr 28 12:43:30 PM PDT 24
Finished Apr 28 12:43:32 PM PDT 24
Peak memory 205620 kb
Host smart-504c0d35-17c6-4bf9-8615-3ca47973362a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668468457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3668468457
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2275480325
Short name T406
Test name
Test status
Simulation time 206090141 ps
CPU time 4.09 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 213968 kb
Host smart-6d95bf26-e26c-4b70-9f43-6a35b7a7940f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275480325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2275480325
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.514245929
Short name T485
Test name
Test status
Simulation time 82297867 ps
CPU time 1.55 seconds
Started Apr 28 12:43:20 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 207924 kb
Host smart-07f3a79f-131b-4f6a-aa1f-f1a5810f8d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514245929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.514245929
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2539494805
Short name T69
Test name
Test status
Simulation time 112386000 ps
CPU time 3.6 seconds
Started Apr 28 12:43:25 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 218052 kb
Host smart-f7dc4bbc-f340-4544-aa9e-e24ef07446e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539494805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2539494805
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.863428260
Short name T77
Test name
Test status
Simulation time 155382729 ps
CPU time 4.44 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 209404 kb
Host smart-e1af5b48-4d10-4756-8d0c-85307b1a4889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863428260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.863428260
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.45132317
Short name T657
Test name
Test status
Simulation time 272731939 ps
CPU time 4.49 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 210180 kb
Host smart-47416b67-b0a8-4066-970c-a7e32b5e65ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45132317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.45132317
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1957703235
Short name T212
Test name
Test status
Simulation time 785077101 ps
CPU time 9.04 seconds
Started Apr 28 12:43:19 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 214028 kb
Host smart-9be92fe7-3c76-433e-8f2e-7a2d76c0be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957703235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1957703235
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3745774592
Short name T856
Test name
Test status
Simulation time 710230847 ps
CPU time 5.43 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:35 PM PDT 24
Peak memory 207456 kb
Host smart-7c674c01-5828-4ad3-ae1a-3942bcc4dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745774592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3745774592
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2360847606
Short name T666
Test name
Test status
Simulation time 24668343 ps
CPU time 2.05 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:31 PM PDT 24
Peak memory 208280 kb
Host smart-7672e709-e8e3-4e4c-ab05-7100aa249d96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360847606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2360847606
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.987522782
Short name T222
Test name
Test status
Simulation time 122463019 ps
CPU time 3.35 seconds
Started Apr 28 12:43:17 PM PDT 24
Finished Apr 28 12:43:21 PM PDT 24
Peak memory 206508 kb
Host smart-1a86ee5f-0812-4ca8-8c6a-ff49dda335a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987522782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.987522782
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3941652883
Short name T753
Test name
Test status
Simulation time 1724848122 ps
CPU time 7.67 seconds
Started Apr 28 12:43:15 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 207724 kb
Host smart-5050dac3-6452-4be8-bda1-46d4956ad9cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941652883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3941652883
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1058736049
Short name T587
Test name
Test status
Simulation time 2086318703 ps
CPU time 19.02 seconds
Started Apr 28 12:43:31 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 209456 kb
Host smart-054f5147-81a0-481c-8800-5c84f9801cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058736049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1058736049
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3695457030
Short name T765
Test name
Test status
Simulation time 45320628 ps
CPU time 2.34 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:32 PM PDT 24
Peak memory 206552 kb
Host smart-406a9880-e01f-4b64-96a1-f2e79b5dccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695457030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3695457030
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4283724886
Short name T283
Test name
Test status
Simulation time 6385938497 ps
CPU time 34.89 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 222288 kb
Host smart-1794d891-d933-46be-b686-2188c71dfa6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283724886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4283724886
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2318231677
Short name T118
Test name
Test status
Simulation time 576295444 ps
CPU time 6.39 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 222248 kb
Host smart-802c53ba-2a43-4d55-8e91-60982a762aab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318231677 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2318231677
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.752860212
Short name T542
Test name
Test status
Simulation time 2484932986 ps
CPU time 60.5 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:44:35 PM PDT 24
Peak memory 208972 kb
Host smart-d2123c16-5387-45f2-a9a8-cd57571dee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752860212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.752860212
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.843385612
Short name T46
Test name
Test status
Simulation time 44061235 ps
CPU time 1.81 seconds
Started Apr 28 12:43:22 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 209544 kb
Host smart-ebd335c9-ffcc-4802-a264-544dcac61209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843385612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.843385612
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.900655980
Short name T774
Test name
Test status
Simulation time 11170085 ps
CPU time 0.84 seconds
Started Apr 28 12:43:24 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 205588 kb
Host smart-4a672f00-3964-4330-91b9-633cac4856ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900655980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.900655980
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1352780906
Short name T345
Test name
Test status
Simulation time 196882074 ps
CPU time 3.89 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 214820 kb
Host smart-b26419bb-a925-4cd2-8839-a2b4c3e08b47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352780906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1352780906
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2089103689
Short name T498
Test name
Test status
Simulation time 744684287 ps
CPU time 5.47 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:41 PM PDT 24
Peak memory 207236 kb
Host smart-2ebf1df1-5322-438f-be13-d43b2f2a7b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089103689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2089103689
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3141132287
Short name T25
Test name
Test status
Simulation time 175390187 ps
CPU time 4.8 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 208572 kb
Host smart-1114c6e9-9184-4149-8f29-fa4d3def3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141132287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3141132287
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3721418691
Short name T241
Test name
Test status
Simulation time 564909276 ps
CPU time 8.74 seconds
Started Apr 28 12:43:26 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 214144 kb
Host smart-ae67001d-87b3-4d9a-9013-22015c20a280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721418691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3721418691
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.108212617
Short name T655
Test name
Test status
Simulation time 142314138 ps
CPU time 2.62 seconds
Started Apr 28 12:43:24 PM PDT 24
Finished Apr 28 12:43:27 PM PDT 24
Peak memory 207100 kb
Host smart-872281dc-d534-4a4a-9fa2-af65221c82e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108212617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.108212617
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.258756848
Short name T548
Test name
Test status
Simulation time 55313366 ps
CPU time 2.96 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 207868 kb
Host smart-d9ad1ef7-ca26-47c0-87e2-fd57e824caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258756848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.258756848
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1412553373
Short name T773
Test name
Test status
Simulation time 271128685 ps
CPU time 4.09 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 206492 kb
Host smart-39861002-0118-4861-bfdc-fe2f120a760e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412553373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1412553373
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.137406090
Short name T764
Test name
Test status
Simulation time 5256910571 ps
CPU time 47.17 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 208484 kb
Host smart-78e4f1e1-1d75-4389-b189-097db88c8649
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137406090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.137406090
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.8447890
Short name T15
Test name
Test status
Simulation time 288302957 ps
CPU time 3.6 seconds
Started Apr 28 12:43:33 PM PDT 24
Finished Apr 28 12:43:37 PM PDT 24
Peak memory 208420 kb
Host smart-50714f50-ab36-4f8c-b4f9-60ecb36f55fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8447890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.8447890
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3187752649
Short name T539
Test name
Test status
Simulation time 1131568769 ps
CPU time 29.3 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 208052 kb
Host smart-2b49b555-134f-445e-9d0e-09b0724b0bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187752649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3187752649
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2210865250
Short name T530
Test name
Test status
Simulation time 80848011 ps
CPU time 1.82 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 206972 kb
Host smart-58ab730c-42b7-45cc-8fad-c01f192e858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210865250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2210865250
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.187344943
Short name T201
Test name
Test status
Simulation time 7020301574 ps
CPU time 45.07 seconds
Started Apr 28 12:43:18 PM PDT 24
Finished Apr 28 12:44:04 PM PDT 24
Peak memory 216972 kb
Host smart-57bfb42c-bbb1-4da3-8b3a-ba933e965b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187344943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.187344943
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3741952938
Short name T532
Test name
Test status
Simulation time 197498874 ps
CPU time 7.72 seconds
Started Apr 28 12:43:46 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 208892 kb
Host smart-4e84148b-e755-4bcd-982e-cf2e821774c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741952938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3741952938
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3240345996
Short name T683
Test name
Test status
Simulation time 60824806 ps
CPU time 2.68 seconds
Started Apr 28 12:43:23 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 209760 kb
Host smart-05976013-3c97-47df-ac7a-e0a9b1214fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240345996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3240345996
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1131535400
Short name T649
Test name
Test status
Simulation time 10581539 ps
CPU time 0.85 seconds
Started Apr 28 12:43:37 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 205596 kb
Host smart-e8b490c9-0d03-4490-97b9-2ae29bb94d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131535400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1131535400
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3449501905
Short name T644
Test name
Test status
Simulation time 39830043 ps
CPU time 2.62 seconds
Started Apr 28 12:43:14 PM PDT 24
Finished Apr 28 12:43:18 PM PDT 24
Peak memory 208664 kb
Host smart-cc1d4877-48eb-4d2c-a863-fcf003526447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449501905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3449501905
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1861909769
Short name T879
Test name
Test status
Simulation time 224470351 ps
CPU time 3.3 seconds
Started Apr 28 12:43:39 PM PDT 24
Finished Apr 28 12:43:43 PM PDT 24
Peak memory 207808 kb
Host smart-a428b6fc-c2f1-4858-8cc4-f215f1e80fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861909769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1861909769
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3464847280
Short name T390
Test name
Test status
Simulation time 534455368 ps
CPU time 5.24 seconds
Started Apr 28 12:43:46 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 208904 kb
Host smart-b95e0b58-0aae-489c-b1a4-18264a4233d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464847280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3464847280
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.419621742
Short name T215
Test name
Test status
Simulation time 1229947656 ps
CPU time 4.63 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 211204 kb
Host smart-c7621592-f18f-42f1-8120-6dd87f1ac6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419621742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.419621742
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3164954487
Short name T826
Test name
Test status
Simulation time 418795445 ps
CPU time 4.57 seconds
Started Apr 28 12:43:39 PM PDT 24
Finished Apr 28 12:43:44 PM PDT 24
Peak memory 220320 kb
Host smart-a76cc6a3-df3c-4415-be0f-9b2ae3da45a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164954487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3164954487
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2358346755
Short name T484
Test name
Test status
Simulation time 113914654 ps
CPU time 3.3 seconds
Started Apr 28 12:43:26 PM PDT 24
Finished Apr 28 12:43:35 PM PDT 24
Peak memory 207900 kb
Host smart-b1046294-d8b9-41aa-84e2-31c0c8babd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358346755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2358346755
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3596728996
Short name T718
Test name
Test status
Simulation time 219008308 ps
CPU time 2.39 seconds
Started Apr 28 12:43:32 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 206312 kb
Host smart-4497b1af-2179-4726-9fb2-276b295d4a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596728996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3596728996
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2304834681
Short name T190
Test name
Test status
Simulation time 622028322 ps
CPU time 12.48 seconds
Started Apr 28 12:43:33 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 208172 kb
Host smart-cf2f1708-1779-4974-b502-0368c9283f5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304834681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2304834681
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.897604752
Short name T769
Test name
Test status
Simulation time 77874439 ps
CPU time 3.02 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:43:48 PM PDT 24
Peak memory 206484 kb
Host smart-46aa7237-b206-4200-9c67-3ead96f46453
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897604752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.897604752
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.965973691
Short name T783
Test name
Test status
Simulation time 76091779 ps
CPU time 3.56 seconds
Started Apr 28 12:43:24 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 208252 kb
Host smart-35746f84-6840-4841-8cfb-ea5bfccf8c10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965973691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.965973691
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2024908180
Short name T823
Test name
Test status
Simulation time 120794944 ps
CPU time 3.48 seconds
Started Apr 28 12:43:32 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 215084 kb
Host smart-ca89adf2-36db-44c4-a6f6-65a5e127b0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024908180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2024908180
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2901198728
Short name T455
Test name
Test status
Simulation time 35966218 ps
CPU time 2.59 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 207928 kb
Host smart-db0692d6-0b9c-45da-adb0-9b274cf265df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901198728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2901198728
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1202842695
Short name T855
Test name
Test status
Simulation time 1505770116 ps
CPU time 16.23 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 209032 kb
Host smart-d7730e37-6611-4ce3-a520-2a673e230151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202842695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1202842695
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3983272682
Short name T211
Test name
Test status
Simulation time 40431369 ps
CPU time 2.98 seconds
Started Apr 28 12:43:16 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 222312 kb
Host smart-9a18b647-f256-4bb3-a85d-c002f95a544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983272682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3983272682
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.637986394
Short name T402
Test name
Test status
Simulation time 57082015 ps
CPU time 2.37 seconds
Started Apr 28 12:43:32 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 209468 kb
Host smart-192e7c4d-33de-44b2-a174-0c6078f0371b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637986394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.637986394
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.919127014
Short name T739
Test name
Test status
Simulation time 15937916 ps
CPU time 0.75 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 205680 kb
Host smart-d6372588-30b9-4363-a93d-50ce8ceb7e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919127014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.919127014
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2859320446
Short name T439
Test name
Test status
Simulation time 114449023 ps
CPU time 4.24 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:40 PM PDT 24
Peak memory 222264 kb
Host smart-cc15b495-40f6-404f-bc9c-7e6bb3617983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859320446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2859320446
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2186870302
Short name T28
Test name
Test status
Simulation time 865982953 ps
CPU time 23.53 seconds
Started Apr 28 12:43:30 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 222360 kb
Host smart-d3d0d2a8-cbf7-408e-937f-7cc4188354bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186870302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2186870302
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2204216430
Short name T686
Test name
Test status
Simulation time 151601639 ps
CPU time 3.53 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 208748 kb
Host smart-c0723044-a0f4-40fe-b780-92ccc526ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204216430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2204216430
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3615129469
Short name T252
Test name
Test status
Simulation time 731645151 ps
CPU time 6.48 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:43:55 PM PDT 24
Peak memory 222240 kb
Host smart-9e9b613d-24df-4cba-9611-b613e588e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615129469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3615129469
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.519762622
Short name T779
Test name
Test status
Simulation time 153051740 ps
CPU time 8.2 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:38 PM PDT 24
Peak memory 222136 kb
Host smart-648b2c05-274b-4d46-8c3e-167a1e2dde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519762622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.519762622
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2035498435
Short name T794
Test name
Test status
Simulation time 174836007 ps
CPU time 3.9 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 210084 kb
Host smart-5ddad687-73b9-4c56-a686-ebfe1229d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035498435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2035498435
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2857710904
Short name T899
Test name
Test status
Simulation time 126968227 ps
CPU time 2.93 seconds
Started Apr 28 12:43:22 PM PDT 24
Finished Apr 28 12:43:26 PM PDT 24
Peak memory 206480 kb
Host smart-2bcf4ca5-29d0-47ae-8ebe-9d8c30b11ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857710904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2857710904
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3671029547
Short name T603
Test name
Test status
Simulation time 739760561 ps
CPU time 4.48 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 208616 kb
Host smart-0436b513-38c3-4614-97cd-5000a5185b6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671029547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3671029547
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.625938345
Short name T204
Test name
Test status
Simulation time 187821118 ps
CPU time 2.64 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:43:53 PM PDT 24
Peak memory 206348 kb
Host smart-7c6460c4-9cfb-4de3-b73f-f05b1c8bb9ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625938345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.625938345
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1321625364
Short name T328
Test name
Test status
Simulation time 111395017 ps
CPU time 3.78 seconds
Started Apr 28 12:43:20 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 206244 kb
Host smart-d9436ab0-da90-4301-a6cb-b9475af2326b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321625364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1321625364
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.386539440
Short name T478
Test name
Test status
Simulation time 181108315 ps
CPU time 1.64 seconds
Started Apr 28 12:43:42 PM PDT 24
Finished Apr 28 12:43:44 PM PDT 24
Peak memory 207536 kb
Host smart-784677ad-96cd-4fcd-bef3-c6e9b1f2a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386539440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.386539440
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3841078284
Short name T444
Test name
Test status
Simulation time 242571297 ps
CPU time 2.91 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 208064 kb
Host smart-db86b86c-6263-405e-8259-964b10a55091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841078284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3841078284
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4022784612
Short name T99
Test name
Test status
Simulation time 1125016523 ps
CPU time 18.36 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 222328 kb
Host smart-b90c7b8d-b094-48ae-b6b4-d65a1f31c35a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022784612 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4022784612
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1075388866
Short name T680
Test name
Test status
Simulation time 500102579 ps
CPU time 14.07 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:43 PM PDT 24
Peak memory 209064 kb
Host smart-74a99da0-2619-4055-ac34-c1114715fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075388866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1075388866
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2363193351
Short name T88
Test name
Test status
Simulation time 218270377 ps
CPU time 1.97 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:43:47 PM PDT 24
Peak memory 209508 kb
Host smart-2504789d-ce2b-4040-a76e-44f28b45f85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363193351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2363193351
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4169771813
Short name T634
Test name
Test status
Simulation time 21597485 ps
CPU time 0.78 seconds
Started Apr 28 12:43:45 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 205576 kb
Host smart-965a91d1-7f21-4d11-a2d9-ee1721d2400e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169771813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4169771813
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.642023832
Short name T305
Test name
Test status
Simulation time 410863146 ps
CPU time 2.92 seconds
Started Apr 28 12:43:24 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 214132 kb
Host smart-a6013122-a7a3-4ad2-8235-809e7d8577b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642023832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.642023832
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3170348615
Short name T788
Test name
Test status
Simulation time 328397674 ps
CPU time 3.73 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:43:38 PM PDT 24
Peak memory 208772 kb
Host smart-eee4c7b4-318c-44eb-962c-1ef34bda3434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170348615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3170348615
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1098791811
Short name T302
Test name
Test status
Simulation time 169423115 ps
CPU time 5.13 seconds
Started Apr 28 12:43:38 PM PDT 24
Finished Apr 28 12:43:44 PM PDT 24
Peak memory 208632 kb
Host smart-5a8943de-c250-48bf-8e7d-38498ddc3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098791811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1098791811
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2501037816
Short name T237
Test name
Test status
Simulation time 349222443 ps
CPU time 3.84 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:31 PM PDT 24
Peak memory 209188 kb
Host smart-1e62b44a-7e71-4164-8c6d-1532427942cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501037816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2501037816
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2825643217
Short name T137
Test name
Test status
Simulation time 170494089 ps
CPU time 3.5 seconds
Started Apr 28 12:43:40 PM PDT 24
Finished Apr 28 12:43:45 PM PDT 24
Peak memory 208280 kb
Host smart-5c90f6d4-caae-499d-a33c-f44be8bbf9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825643217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2825643217
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4060869126
Short name T648
Test name
Test status
Simulation time 285713139 ps
CPU time 2.97 seconds
Started Apr 28 12:43:21 PM PDT 24
Finished Apr 28 12:43:25 PM PDT 24
Peak memory 206436 kb
Host smart-19dd4add-d538-44f8-a48b-7dea1f2562e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060869126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4060869126
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2101929312
Short name T416
Test name
Test status
Simulation time 256908332 ps
CPU time 7.73 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:35 PM PDT 24
Peak memory 207820 kb
Host smart-f0b720c8-b7db-4f4c-96f5-d1679c5c44e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101929312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2101929312
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.362466982
Short name T205
Test name
Test status
Simulation time 74853708 ps
CPU time 3.16 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 206900 kb
Host smart-e5c3bf57-db36-4de1-a3a1-1415b23be9a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362466982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.362466982
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1693683376
Short name T192
Test name
Test status
Simulation time 60402065 ps
CPU time 3.01 seconds
Started Apr 28 12:43:32 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 207496 kb
Host smart-fa54423c-c594-4d49-ac22-42c4c0aba0da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693683376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1693683376
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2075152609
Short name T829
Test name
Test status
Simulation time 150363797 ps
CPU time 2.53 seconds
Started Apr 28 12:43:30 PM PDT 24
Finished Apr 28 12:43:33 PM PDT 24
Peak memory 208776 kb
Host smart-c726b0b8-4f32-41f7-bd14-2bbcc5f186ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075152609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2075152609
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1702899542
Short name T197
Test name
Test status
Simulation time 191824173 ps
CPU time 3.33 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:43:38 PM PDT 24
Peak memory 208188 kb
Host smart-ae238ec3-0954-4be8-ba1b-4f461ac6a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702899542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1702899542
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.156729143
Short name T808
Test name
Test status
Simulation time 1882825917 ps
CPU time 19.05 seconds
Started Apr 28 12:43:41 PM PDT 24
Finished Apr 28 12:44:00 PM PDT 24
Peak memory 222264 kb
Host smart-f06fccbe-886d-4753-9c10-1d2d9e2bf79e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156729143 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.156729143
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.705914713
Short name T267
Test name
Test status
Simulation time 2566207894 ps
CPU time 9.86 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 209256 kb
Host smart-b5049ebf-c989-4f42-a146-7812a5b9e940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705914713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.705914713
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.370624177
Short name T759
Test name
Test status
Simulation time 85637344 ps
CPU time 2.08 seconds
Started Apr 28 12:43:36 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 209592 kb
Host smart-64fee5d3-e151-4a63-8f22-f189426e809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370624177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.370624177
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3406264104
Short name T777
Test name
Test status
Simulation time 9136191 ps
CPU time 0.72 seconds
Started Apr 28 12:43:40 PM PDT 24
Finished Apr 28 12:43:41 PM PDT 24
Peak memory 205604 kb
Host smart-28eda2fb-9ad9-4ef1-ad07-15b9dd06b19a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406264104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3406264104
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1813459002
Short name T731
Test name
Test status
Simulation time 3288910179 ps
CPU time 22.56 seconds
Started Apr 28 12:43:42 PM PDT 24
Finished Apr 28 12:44:06 PM PDT 24
Peak memory 208660 kb
Host smart-24c2c269-30e4-4e8b-bd36-0053e4527707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813459002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1813459002
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3197587394
Short name T299
Test name
Test status
Simulation time 688731793 ps
CPU time 9.43 seconds
Started Apr 28 12:43:41 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 222148 kb
Host smart-fa2fa5a4-e1e2-49b2-b8d3-562375da3175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197587394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3197587394
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4218720148
Short name T701
Test name
Test status
Simulation time 236382884 ps
CPU time 3.95 seconds
Started Apr 28 12:43:28 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 220092 kb
Host smart-56e8744a-b2f7-46b8-bde7-9233e36a3f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218720148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4218720148
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2243164144
Short name T531
Test name
Test status
Simulation time 1759708795 ps
CPU time 10.06 seconds
Started Apr 28 12:43:36 PM PDT 24
Finished Apr 28 12:43:47 PM PDT 24
Peak memory 208284 kb
Host smart-4dfb0c00-c786-4543-ab18-6ea3f91c66f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243164144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2243164144
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1466163455
Short name T897
Test name
Test status
Simulation time 57814554 ps
CPU time 2.23 seconds
Started Apr 28 12:43:26 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 208528 kb
Host smart-b1f0653d-a3c2-4379-b315-d1ad03121970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466163455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1466163455
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2314606005
Short name T725
Test name
Test status
Simulation time 1530069719 ps
CPU time 7.44 seconds
Started Apr 28 12:43:50 PM PDT 24
Finished Apr 28 12:43:58 PM PDT 24
Peak memory 207636 kb
Host smart-d4889e86-1990-444a-b2fc-fe41a5f27d84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314606005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2314606005
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.404984418
Short name T740
Test name
Test status
Simulation time 88459562 ps
CPU time 3.77 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:31 PM PDT 24
Peak memory 206432 kb
Host smart-311cc681-375b-41d6-8ef3-2202d0f2bc9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404984418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.404984418
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3069995590
Short name T828
Test name
Test status
Simulation time 176527662 ps
CPU time 3.41 seconds
Started Apr 28 12:43:33 PM PDT 24
Finished Apr 28 12:43:37 PM PDT 24
Peak memory 208252 kb
Host smart-af23a364-4e8e-4fd0-83a6-b2cd50461345
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069995590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3069995590
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.618540682
Short name T658
Test name
Test status
Simulation time 365683028 ps
CPU time 3.61 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 215100 kb
Host smart-3a7dc5de-9120-46d3-9871-92cb77273858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618540682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.618540682
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3268971804
Short name T488
Test name
Test status
Simulation time 1784114300 ps
CPU time 15.89 seconds
Started Apr 28 12:43:30 PM PDT 24
Finished Apr 28 12:43:47 PM PDT 24
Peak memory 207684 kb
Host smart-2e4e968d-2b8f-416f-8672-460d8699a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268971804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3268971804
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1155917542
Short name T57
Test name
Test status
Simulation time 621221132 ps
CPU time 9.01 seconds
Started Apr 28 12:43:26 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 216276 kb
Host smart-ba11a77b-e8f3-4b6c-8b66-b2fc9f8a3ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155917542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1155917542
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3484521401
Short name T849
Test name
Test status
Simulation time 138332442 ps
CPU time 8.85 seconds
Started Apr 28 12:43:36 PM PDT 24
Finished Apr 28 12:43:45 PM PDT 24
Peak memory 222324 kb
Host smart-f05dd4ba-681c-45b4-b995-e940e08f0a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484521401 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3484521401
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1281841013
Short name T887
Test name
Test status
Simulation time 254876263 ps
CPU time 6.06 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 209440 kb
Host smart-aacdae44-08a5-474b-82e7-a89366b98ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281841013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1281841013
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2763954707
Short name T694
Test name
Test status
Simulation time 215547716 ps
CPU time 1.6 seconds
Started Apr 28 12:43:47 PM PDT 24
Finished Apr 28 12:43:49 PM PDT 24
Peak memory 209848 kb
Host smart-96f390de-f054-4a97-a3e1-e31692cb2b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763954707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2763954707
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3828384142
Short name T453
Test name
Test status
Simulation time 28699105 ps
CPU time 0.76 seconds
Started Apr 28 12:43:27 PM PDT 24
Finished Apr 28 12:43:29 PM PDT 24
Peak memory 205612 kb
Host smart-b343332c-a5d4-4d11-8f51-065e97d6929e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828384142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3828384142
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.791458465
Short name T232
Test name
Test status
Simulation time 143639619 ps
CPU time 3.66 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:43:52 PM PDT 24
Peak memory 216620 kb
Host smart-dcb058a8-7f95-4ca8-8cbc-418bb5a9357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791458465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.791458465
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1342835173
Short name T656
Test name
Test status
Simulation time 243271435 ps
CPU time 3.47 seconds
Started Apr 28 12:43:51 PM PDT 24
Finished Apr 28 12:43:55 PM PDT 24
Peak memory 209632 kb
Host smart-f9772812-d8ff-46fe-83a5-f324c9df1924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342835173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1342835173
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.454188671
Short name T850
Test name
Test status
Simulation time 936905780 ps
CPU time 6.09 seconds
Started Apr 28 12:43:30 PM PDT 24
Finished Apr 28 12:43:37 PM PDT 24
Peak memory 213972 kb
Host smart-c399eee1-f94b-43bb-9548-d35be2c59a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454188671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.454188671
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.593058273
Short name T277
Test name
Test status
Simulation time 89617850 ps
CPU time 5.16 seconds
Started Apr 28 12:43:32 PM PDT 24
Finished Apr 28 12:43:38 PM PDT 24
Peak memory 210240 kb
Host smart-a07cf25b-128e-4dfa-931b-74a5ae4dc975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593058273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.593058273
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.526141400
Short name T496
Test name
Test status
Simulation time 1110676829 ps
CPU time 3.67 seconds
Started Apr 28 12:43:34 PM PDT 24
Finished Apr 28 12:43:38 PM PDT 24
Peak memory 206476 kb
Host smart-412da393-16b5-4180-be10-d26017a3becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526141400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.526141400
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3253870064
Short name T400
Test name
Test status
Simulation time 645790612 ps
CPU time 7.39 seconds
Started Apr 28 12:43:43 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 206848 kb
Host smart-20c3768d-270d-444b-ba2b-2a61db9927f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253870064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3253870064
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3632610574
Short name T638
Test name
Test status
Simulation time 107969240 ps
CPU time 2.92 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:44:07 PM PDT 24
Peak memory 206960 kb
Host smart-99506ee5-be16-4886-bcb6-1547984ec566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632610574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3632610574
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.592195165
Short name T792
Test name
Test status
Simulation time 157462410 ps
CPU time 2.46 seconds
Started Apr 28 12:43:33 PM PDT 24
Finished Apr 28 12:43:36 PM PDT 24
Peak memory 206608 kb
Host smart-b523bda2-675b-4f59-be7f-0dba8e154ae2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592195165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.592195165
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3559937944
Short name T832
Test name
Test status
Simulation time 3251623508 ps
CPU time 23.43 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:53 PM PDT 24
Peak memory 208100 kb
Host smart-83cfdeb9-995d-4a1e-81c2-0bfedec4dcb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559937944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3559937944
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.637252933
Short name T650
Test name
Test status
Simulation time 259683052 ps
CPU time 2.62 seconds
Started Apr 28 12:43:58 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 207040 kb
Host smart-bcc302a7-bcea-49ff-9750-eabd73da035e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637252933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.637252933
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3275822221
Short name T279
Test name
Test status
Simulation time 166493470 ps
CPU time 3.97 seconds
Started Apr 28 12:43:36 PM PDT 24
Finished Apr 28 12:43:41 PM PDT 24
Peak memory 218044 kb
Host smart-cc379046-d412-445c-a560-97473727730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275822221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3275822221
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.244250861
Short name T217
Test name
Test status
Simulation time 283773659 ps
CPU time 3.83 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 206236 kb
Host smart-f8c4f166-d6ad-4486-95cd-62095422c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244250861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.244250861
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.953198771
Short name T198
Test name
Test status
Simulation time 2416754026 ps
CPU time 24.73 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 215444 kb
Host smart-5b5272f2-4fb6-4b47-9227-6122e8b38677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953198771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.953198771
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.362446291
Short name T289
Test name
Test status
Simulation time 257305647 ps
CPU time 4.04 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:43:49 PM PDT 24
Peak memory 209800 kb
Host smart-a7b55eda-7cef-4f01-a396-79db5167bfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362446291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.362446291
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2906150074
Short name T159
Test name
Test status
Simulation time 69714077 ps
CPU time 2.11 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 208856 kb
Host smart-644c1f1d-14a4-4951-9a8a-021f229ec45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906150074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2906150074
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3702487486
Short name T560
Test name
Test status
Simulation time 18190086 ps
CPU time 0.97 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 205764 kb
Host smart-299deaf9-72c8-4d41-9c69-72f6eaad4781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702487486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3702487486
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.791627633
Short name T438
Test name
Test status
Simulation time 248842010 ps
CPU time 4.2 seconds
Started Apr 28 12:43:29 PM PDT 24
Finished Apr 28 12:43:34 PM PDT 24
Peak memory 213944 kb
Host smart-599287c3-37d1-4572-97d2-df99869c4eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791627633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.791627633
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3458446055
Short name T27
Test name
Test status
Simulation time 164051944 ps
CPU time 4.47 seconds
Started Apr 28 12:43:47 PM PDT 24
Finished Apr 28 12:43:52 PM PDT 24
Peak memory 208676 kb
Host smart-faa8d998-200c-4e66-aeff-6c08f22c4d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458446055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3458446055
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3857451778
Short name T534
Test name
Test status
Simulation time 36975310 ps
CPU time 1.96 seconds
Started Apr 28 12:43:51 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 208704 kb
Host smart-72b2a619-943a-4d87-82eb-1db7c19684dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857451778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3857451778
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2506011961
Short name T79
Test name
Test status
Simulation time 660306509 ps
CPU time 5.53 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 214136 kb
Host smart-5d8bf41b-74d9-49d9-9854-913633401d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506011961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2506011961
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2017271469
Short name T396
Test name
Test status
Simulation time 1030729528 ps
CPU time 4.08 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:41 PM PDT 24
Peak memory 222172 kb
Host smart-6dfac5a6-9dd9-465f-a62e-b62a274e1e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017271469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2017271469
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3999391122
Short name T226
Test name
Test status
Simulation time 254353598 ps
CPU time 6.77 seconds
Started Apr 28 12:43:43 PM PDT 24
Finished Apr 28 12:43:50 PM PDT 24
Peak memory 222096 kb
Host smart-cd048e96-1684-4416-9188-f00e1593357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999391122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3999391122
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.548430889
Short name T679
Test name
Test status
Simulation time 41490362 ps
CPU time 2.86 seconds
Started Apr 28 12:43:39 PM PDT 24
Finished Apr 28 12:43:43 PM PDT 24
Peak memory 207104 kb
Host smart-e6a8bce0-fda1-488a-99f2-7517de916467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548430889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.548430889
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1353582770
Short name T761
Test name
Test status
Simulation time 119941677 ps
CPU time 3.16 seconds
Started Apr 28 12:43:42 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 206344 kb
Host smart-983e63f3-2863-4bec-80e9-9fbc529d0255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353582770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1353582770
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4016510800
Short name T738
Test name
Test status
Simulation time 148717219 ps
CPU time 2.33 seconds
Started Apr 28 12:43:43 PM PDT 24
Finished Apr 28 12:43:46 PM PDT 24
Peak memory 206560 kb
Host smart-63315ea4-999a-482a-acd9-e36edd6a471e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016510800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4016510800
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1397473396
Short name T878
Test name
Test status
Simulation time 164448555 ps
CPU time 3.25 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 208396 kb
Host smart-98f1cb98-000f-4c5e-8048-2b49c9d059bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397473396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1397473396
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.848992427
Short name T691
Test name
Test status
Simulation time 1013528722 ps
CPU time 4.52 seconds
Started Apr 28 12:43:35 PM PDT 24
Finished Apr 28 12:43:40 PM PDT 24
Peak memory 207468 kb
Host smart-0e41f125-a342-444e-9c8d-9b9c14b88e7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848992427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.848992427
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.421691488
Short name T39
Test name
Test status
Simulation time 303420189 ps
CPU time 9.07 seconds
Started Apr 28 12:43:40 PM PDT 24
Finished Apr 28 12:43:50 PM PDT 24
Peak memory 208364 kb
Host smart-fb139b10-13f5-4120-ad38-8482dda234fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421691488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.421691488
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2990160503
Short name T863
Test name
Test status
Simulation time 141292495 ps
CPU time 4.04 seconds
Started Apr 28 12:43:37 PM PDT 24
Finished Apr 28 12:43:42 PM PDT 24
Peak memory 206164 kb
Host smart-70b76ee7-fa1a-4b85-a1b5-4a6819cf414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990160503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2990160503
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.95143957
Short name T329
Test name
Test status
Simulation time 761853502 ps
CPU time 4.67 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:11 PM PDT 24
Peak memory 207116 kb
Host smart-16dfef91-d1ad-4168-b2a6-51dfa0498406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95143957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.95143957
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1572446524
Short name T107
Test name
Test status
Simulation time 33316544 ps
CPU time 2.18 seconds
Started Apr 28 12:43:50 PM PDT 24
Finished Apr 28 12:43:53 PM PDT 24
Peak memory 209240 kb
Host smart-194fff55-d9c7-41e2-8847-7b847d30d237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572446524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1572446524
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.206975055
Short name T502
Test name
Test status
Simulation time 156016366 ps
CPU time 0.94 seconds
Started Apr 28 12:43:50 PM PDT 24
Finished Apr 28 12:43:52 PM PDT 24
Peak memory 205452 kb
Host smart-1199a049-37a8-4110-9c5f-cdd02e369dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206975055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.206975055
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4198430222
Short name T228
Test name
Test status
Simulation time 1396518366 ps
CPU time 8.4 seconds
Started Apr 28 12:43:51 PM PDT 24
Finished Apr 28 12:44:00 PM PDT 24
Peak memory 215628 kb
Host smart-6310fdb0-ae04-4fee-a4c3-cce6ffe94366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198430222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4198430222
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1754496775
Short name T591
Test name
Test status
Simulation time 216678897 ps
CPU time 3.2 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:44:00 PM PDT 24
Peak memory 214028 kb
Host smart-8fdc0fd9-ff04-4b13-9746-1087531ded5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754496775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1754496775
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3998629291
Short name T318
Test name
Test status
Simulation time 509893207 ps
CPU time 5.44 seconds
Started Apr 28 12:43:45 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 218968 kb
Host smart-5af0d152-5eda-4989-9dc0-49c639263409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998629291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3998629291
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.952116089
Short name T322
Test name
Test status
Simulation time 792478875 ps
CPU time 8.25 seconds
Started Apr 28 12:43:45 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 222164 kb
Host smart-538a12c0-dd53-4348-84de-97a17ecaa2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952116089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.952116089
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2618698502
Short name T234
Test name
Test status
Simulation time 76793639 ps
CPU time 2.4 seconds
Started Apr 28 12:43:40 PM PDT 24
Finished Apr 28 12:43:43 PM PDT 24
Peak memory 214028 kb
Host smart-6b91aaa3-3700-4470-aa1f-7ac7f806d56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618698502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2618698502
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3432696683
Short name T374
Test name
Test status
Simulation time 171218536 ps
CPU time 4.28 seconds
Started Apr 28 12:43:55 PM PDT 24
Finished Apr 28 12:44:00 PM PDT 24
Peak memory 206920 kb
Host smart-90da7c82-5cf9-46c9-a6c6-f7f44cc6231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432696683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3432696683
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3782053009
Short name T661
Test name
Test status
Simulation time 4405100950 ps
CPU time 40.71 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:40 PM PDT 24
Peak memory 207472 kb
Host smart-7007edd5-1de4-4961-9da9-216a2d52cd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782053009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3782053009
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.106471769
Short name T822
Test name
Test status
Simulation time 101396812 ps
CPU time 2.34 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 208400 kb
Host smart-d0567f10-8f76-49e9-8e85-fac41147efd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106471769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.106471769
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2381648086
Short name T876
Test name
Test status
Simulation time 310833638 ps
CPU time 4.81 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 207776 kb
Host smart-bfdf5c9a-c81e-4bc8-b796-1ecb2f21df7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381648086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2381648086
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1320207112
Short name T755
Test name
Test status
Simulation time 251413508 ps
CPU time 8.68 seconds
Started Apr 28 12:43:54 PM PDT 24
Finished Apr 28 12:44:03 PM PDT 24
Peak memory 208288 kb
Host smart-05cda079-c364-4833-8b69-7ee40d15bc3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320207112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1320207112
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3012425646
Short name T700
Test name
Test status
Simulation time 357063415 ps
CPU time 2.66 seconds
Started Apr 28 12:43:42 PM PDT 24
Finished Apr 28 12:43:45 PM PDT 24
Peak memory 207536 kb
Host smart-111129a1-a181-41c3-aea4-10ed86a31fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012425646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3012425646
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.601961038
Short name T284
Test name
Test status
Simulation time 593676207 ps
CPU time 5.56 seconds
Started Apr 28 12:43:55 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 208344 kb
Host smart-de833d33-31a7-4d11-b6c2-42bf587c76c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601961038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.601961038
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3993296581
Short name T757
Test name
Test status
Simulation time 140705239 ps
CPU time 4.59 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:43:49 PM PDT 24
Peak memory 214088 kb
Host smart-623ffb27-3c1c-4bc1-b194-d2210be3281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993296581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3993296581
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2717919840
Short name T749
Test name
Test status
Simulation time 65376107 ps
CPU time 0.77 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 205444 kb
Host smart-a812b17b-d722-4412-8d61-e26ad0392c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717919840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2717919840
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2857478628
Short name T437
Test name
Test status
Simulation time 118345661 ps
CPU time 2.59 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 214012 kb
Host smart-72a3d025-bb19-4154-9545-930317d141a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857478628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2857478628
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1006216960
Short name T32
Test name
Test status
Simulation time 49405052 ps
CPU time 3.51 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 222432 kb
Host smart-e74897f3-13f9-4ece-a036-b5625bf12c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006216960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1006216960
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.637526571
Short name T629
Test name
Test status
Simulation time 133109619 ps
CPU time 2.58 seconds
Started Apr 28 12:41:39 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 207500 kb
Host smart-69584b44-82b6-40d2-9424-30a168e50921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637526571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.637526571
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3854596577
Short name T414
Test name
Test status
Simulation time 2055261544 ps
CPU time 8.87 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:41:58 PM PDT 24
Peak memory 209432 kb
Host smart-33df382c-800d-4dcb-b6af-0e6371a8d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854596577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3854596577
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2067591139
Short name T337
Test name
Test status
Simulation time 217733652 ps
CPU time 8.21 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 213984 kb
Host smart-e7e41c08-7678-4d4d-acd1-46ced3d0de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067591139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2067591139
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2789241544
Short name T672
Test name
Test status
Simulation time 509316916 ps
CPU time 3.74 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 214012 kb
Host smart-7d29e923-2f76-4fce-85f7-f5bf92802016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789241544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2789241544
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3382192944
Short name T772
Test name
Test status
Simulation time 50453484 ps
CPU time 3.31 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 213972 kb
Host smart-5a099ca4-e660-40cd-b98a-6ba472d3c318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382192944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3382192944
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3692484297
Short name T295
Test name
Test status
Simulation time 158431352 ps
CPU time 5.13 seconds
Started Apr 28 12:41:39 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 206248 kb
Host smart-c2f000af-1a2f-4129-83eb-8828e5cf185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692484297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3692484297
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3883262236
Short name T771
Test name
Test status
Simulation time 193311624 ps
CPU time 2.91 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 206404 kb
Host smart-01f03f9c-c07f-40c7-a25e-721253a9920d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883262236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3883262236
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.519997574
Short name T249
Test name
Test status
Simulation time 201187314 ps
CPU time 2.59 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 208212 kb
Host smart-afe30f24-909f-4204-a1f9-de66ac570f12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519997574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.519997574
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2266309101
Short name T767
Test name
Test status
Simulation time 75991266 ps
CPU time 1.76 seconds
Started Apr 28 12:41:45 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 206484 kb
Host smart-5e59050f-80b3-4ad7-a981-7e6c6d0395a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266309101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2266309101
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3956549755
Short name T688
Test name
Test status
Simulation time 162758916 ps
CPU time 4.06 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 210092 kb
Host smart-d2728fb8-1d3f-4dc0-bfb5-981e044e837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956549755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3956549755
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3578021238
Short name T458
Test name
Test status
Simulation time 128392167 ps
CPU time 2.03 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 208204 kb
Host smart-eedbd9c7-49d2-4400-8905-6833a0ec857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578021238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3578021238
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1529419431
Short name T415
Test name
Test status
Simulation time 1072096939 ps
CPU time 8.64 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 213984 kb
Host smart-788ce402-4703-471a-915c-f3f1ca8cb229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529419431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1529419431
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3460770072
Short name T733
Test name
Test status
Simulation time 288289531 ps
CPU time 4.65 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 207756 kb
Host smart-d0eaad64-48e2-4694-9bb9-9889097d86cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460770072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3460770072
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3582157500
Short name T830
Test name
Test status
Simulation time 60676684 ps
CPU time 2.47 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:41:58 PM PDT 24
Peak memory 210096 kb
Host smart-9b68c9c1-524d-4e8f-9707-68dbb64c61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582157500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3582157500
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2198761059
Short name T481
Test name
Test status
Simulation time 46272569 ps
CPU time 0.72 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 205520 kb
Host smart-d07699ab-94ce-4bbb-a6b3-f84b7e557b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198761059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2198761059
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2509684438
Short name T408
Test name
Test status
Simulation time 128797156 ps
CPU time 3.36 seconds
Started Apr 28 12:41:45 PM PDT 24
Finished Apr 28 12:41:50 PM PDT 24
Peak memory 215292 kb
Host smart-2a694ffc-6480-46a0-ac74-6bd17103e212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509684438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2509684438
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1562896764
Short name T35
Test name
Test status
Simulation time 255595200 ps
CPU time 3.09 seconds
Started Apr 28 12:41:51 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 214100 kb
Host smart-a264f8a9-66f8-41da-9853-0e84ebf32ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562896764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1562896764
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2172722375
Short name T868
Test name
Test status
Simulation time 5119172603 ps
CPU time 16.26 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:15 PM PDT 24
Peak memory 218104 kb
Host smart-88c87446-e7cc-4198-a203-900e4ca6dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172722375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2172722375
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1026258194
Short name T340
Test name
Test status
Simulation time 210731957 ps
CPU time 3.6 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 214180 kb
Host smart-3d736b1e-66f0-4ee7-8ad1-f0378ecee63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026258194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1026258194
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2162182197
Short name T312
Test name
Test status
Simulation time 738069847 ps
CPU time 6.2 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 213920 kb
Host smart-91ec2f42-acab-43f0-8e0f-2452554a846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162182197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2162182197
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2182086944
Short name T870
Test name
Test status
Simulation time 2274811831 ps
CPU time 61.38 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:42:53 PM PDT 24
Peak memory 209904 kb
Host smart-0a11426d-5644-443d-990a-c0a504d355ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182086944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2182086944
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1711655036
Short name T506
Test name
Test status
Simulation time 33619847 ps
CPU time 2.43 seconds
Started Apr 28 12:41:51 PM PDT 24
Finished Apr 28 12:41:55 PM PDT 24
Peak memory 207012 kb
Host smart-7c7d6039-0fb7-4336-8006-86ad3a1b9dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711655036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1711655036
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2647829139
Short name T325
Test name
Test status
Simulation time 884954914 ps
CPU time 23.47 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:42:14 PM PDT 24
Peak memory 208088 kb
Host smart-e6428834-06bb-45fe-8d5b-57f9b7b96a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647829139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2647829139
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.999239409
Short name T553
Test name
Test status
Simulation time 557536420 ps
CPU time 4.32 seconds
Started Apr 28 12:41:47 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 207308 kb
Host smart-5d2276fb-e275-4eee-8779-8c76d9baa979
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999239409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.999239409
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3033596764
Short name T203
Test name
Test status
Simulation time 180155290 ps
CPU time 2.49 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 207680 kb
Host smart-8ed29cf0-321b-4c49-9e0f-93fd97a9a50f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033596764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3033596764
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3987902992
Short name T552
Test name
Test status
Simulation time 65159175 ps
CPU time 3.16 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 206704 kb
Host smart-2f9c9866-ee86-425d-9d57-022ca408fd17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987902992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3987902992
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4176551922
Short name T473
Test name
Test status
Simulation time 533173128 ps
CPU time 3.39 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 214012 kb
Host smart-a9a76129-f128-4682-a2b0-c8f033274e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176551922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4176551922
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2275798447
Short name T73
Test name
Test status
Simulation time 129443907 ps
CPU time 2.79 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 208064 kb
Host smart-4d11d250-9e17-4897-9b4c-a6b3505c7d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275798447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2275798447
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3068851039
Short name T799
Test name
Test status
Simulation time 39062337333 ps
CPU time 230.35 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 219548 kb
Host smart-8cf15f3b-9b9f-48f3-80e7-0da1196ec6ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068851039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3068851039
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1539407661
Short name T303
Test name
Test status
Simulation time 690920714 ps
CPU time 5.63 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 214124 kb
Host smart-8a7b5316-632c-431f-ab7e-3a74885731d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539407661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1539407661
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.415862336
Short name T173
Test name
Test status
Simulation time 127841470 ps
CPU time 1.9 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 209884 kb
Host smart-df3cba20-b65c-4b25-966b-79dcf5bfbcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415862336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.415862336
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2475850746
Short name T639
Test name
Test status
Simulation time 49768239 ps
CPU time 1.11 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 205748 kb
Host smart-e0e8ccae-51b8-4763-96b0-8b515d873836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475850746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2475850746
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1527862994
Short name T662
Test name
Test status
Simulation time 407956592 ps
CPU time 3.05 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 219560 kb
Host smart-adca52cf-d32e-4638-a4fe-a1deaf73d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527862994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1527862994
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1388507901
Short name T395
Test name
Test status
Simulation time 602876510 ps
CPU time 2.39 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 213952 kb
Host smart-43a5972f-1b5f-4a9c-82e9-dc9a99a143a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388507901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1388507901
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2807245736
Short name T804
Test name
Test status
Simulation time 395323656 ps
CPU time 5.75 seconds
Started Apr 28 12:42:00 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 213852 kb
Host smart-71364c2a-8f41-4445-bb90-9f1a77a374cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807245736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2807245736
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3773605381
Short name T646
Test name
Test status
Simulation time 761439811 ps
CPU time 4.98 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 218472 kb
Host smart-120183dd-9321-4f25-8f78-3d1be869ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773605381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3773605381
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1357790662
Short name T320
Test name
Test status
Simulation time 815434330 ps
CPU time 5.67 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 208804 kb
Host smart-dc5314f1-4ea2-4a9c-b1cc-1d4107a3813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357790662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1357790662
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2420780679
Short name T421
Test name
Test status
Simulation time 266473687 ps
CPU time 4.62 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 206244 kb
Host smart-b7aa5e4e-17ce-476d-bc07-01d4560c8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420780679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2420780679
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2188979734
Short name T641
Test name
Test status
Simulation time 248086315 ps
CPU time 2.92 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 206360 kb
Host smart-ac650cb5-f1c4-4051-a7e8-6109019dc3ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188979734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2188979734
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2111791570
Short name T543
Test name
Test status
Simulation time 50662607 ps
CPU time 2.23 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 208404 kb
Host smart-6f835128-e57a-40db-90ac-562b8b44a50e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111791570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2111791570
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3492123528
Short name T521
Test name
Test status
Simulation time 33141509 ps
CPU time 2.46 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 206932 kb
Host smart-5254b1b7-69ed-4a81-bf9f-442005183df0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492123528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3492123528
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.492421958
Short name T123
Test name
Test status
Simulation time 166918687 ps
CPU time 2.83 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 209300 kb
Host smart-2d2528e1-ad91-4f7e-ba0f-fbbd7ef942a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492421958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.492421958
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1358265373
Short name T206
Test name
Test status
Simulation time 100467536 ps
CPU time 2.96 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 207392 kb
Host smart-f4778f78-b7ef-4261-978c-af7f67310f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358265373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1358265373
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2876956403
Short name T344
Test name
Test status
Simulation time 2141789236 ps
CPU time 61.22 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:42:57 PM PDT 24
Peak memory 222108 kb
Host smart-3e8904b3-39dd-40a9-ad0d-a4edcc051dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876956403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2876956403
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.951124389
Short name T131
Test name
Test status
Simulation time 280781179 ps
CPU time 19.15 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:42:15 PM PDT 24
Peak memory 222252 kb
Host smart-3ffb40cf-2aeb-4389-9a67-460b12d6d641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951124389 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.951124389
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.399887320
Short name T392
Test name
Test status
Simulation time 793007275 ps
CPU time 6.47 seconds
Started Apr 28 12:41:49 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 207740 kb
Host smart-a38bc90c-38dc-420c-ad19-61dc0dba89ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399887320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.399887320
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1399868537
Short name T631
Test name
Test status
Simulation time 12672804 ps
CPU time 0.88 seconds
Started Apr 28 12:42:00 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 205608 kb
Host smart-c46a673d-fdd8-4bea-be69-32da20b00eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399868537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1399868537
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.19591463
Short name T384
Test name
Test status
Simulation time 199635205 ps
CPU time 6.21 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 214048 kb
Host smart-9c8eefb6-8062-4c22-8151-ad71cc708ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19591463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.19591463
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2546310682
Short name T840
Test name
Test status
Simulation time 483364146 ps
CPU time 4.32 seconds
Started Apr 28 12:42:00 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 209412 kb
Host smart-fdc0c0e3-872a-44df-b688-1d6cb15c7eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546310682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2546310682
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.273908480
Short name T554
Test name
Test status
Simulation time 480952848 ps
CPU time 3 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 214012 kb
Host smart-e828df7f-2844-4399-8445-49e1813845f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273908480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.273908480
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1040622781
Short name T85
Test name
Test status
Simulation time 298261705 ps
CPU time 4.12 seconds
Started Apr 28 12:42:03 PM PDT 24
Finished Apr 28 12:42:09 PM PDT 24
Peak memory 208448 kb
Host smart-fecd65ca-3454-4b30-aa08-64e3133f55d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040622781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1040622781
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1017163013
Short name T874
Test name
Test status
Simulation time 89922748 ps
CPU time 3.88 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 219564 kb
Host smart-362cd63b-7e2e-41b0-823b-e2f058a2be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017163013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1017163013
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3578744114
Short name T351
Test name
Test status
Simulation time 52331537 ps
CPU time 2.55 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 207644 kb
Host smart-f3edc035-aa94-449f-89de-486b7272251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578744114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3578744114
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1380196886
Short name T676
Test name
Test status
Simulation time 321404682 ps
CPU time 3.24 seconds
Started Apr 28 12:41:50 PM PDT 24
Finished Apr 28 12:41:55 PM PDT 24
Peak memory 206404 kb
Host smart-93d68ed0-5997-4afc-bc5d-f6490fa687c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380196886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1380196886
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3393996768
Short name T825
Test name
Test status
Simulation time 239804714 ps
CPU time 4.16 seconds
Started Apr 28 12:41:51 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 208080 kb
Host smart-d88aa2cd-2f8d-4f90-878c-5fba27d805b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393996768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3393996768
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1340924595
Short name T741
Test name
Test status
Simulation time 568778583 ps
CPU time 5.52 seconds
Started Apr 28 12:41:53 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 208496 kb
Host smart-07ba532d-ed4a-4a94-9e97-a438c509ef6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340924595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1340924595
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.759074200
Short name T640
Test name
Test status
Simulation time 607476147 ps
CPU time 7.77 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 207468 kb
Host smart-3aa57194-8a38-4fab-960a-e50f58da45d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759074200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.759074200
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1460065831
Short name T324
Test name
Test status
Simulation time 201415283 ps
CPU time 2.27 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 221928 kb
Host smart-8dd8c16f-5971-492f-bce7-b9fc5b8b6b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460065831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1460065831
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2379136233
Short name T608
Test name
Test status
Simulation time 33524774 ps
CPU time 2.16 seconds
Started Apr 28 12:41:47 PM PDT 24
Finished Apr 28 12:41:50 PM PDT 24
Peak memory 206384 kb
Host smart-4dd90aa0-44b9-405a-8750-f209bfa78dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379136233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2379136233
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2463645791
Short name T296
Test name
Test status
Simulation time 1132793383 ps
CPU time 37.43 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:42:33 PM PDT 24
Peak memory 209220 kb
Host smart-7b0cf64e-a994-4e0b-acd5-a7dcf39ed138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463645791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2463645791
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.40760948
Short name T182
Test name
Test status
Simulation time 116155698 ps
CPU time 1.9 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 209588 kb
Host smart-dc4fb087-c492-4c54-9f2a-46ce2ec4418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40760948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.40760948
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.300531530
Short name T495
Test name
Test status
Simulation time 24080971 ps
CPU time 0.87 seconds
Started Apr 28 12:42:19 PM PDT 24
Finished Apr 28 12:42:21 PM PDT 24
Peak memory 205568 kb
Host smart-f69d73d9-7fa2-4be9-b9a0-92e42dfafa19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300531530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.300531530
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1484605233
Short name T22
Test name
Test status
Simulation time 65744385 ps
CPU time 2.8 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 220432 kb
Host smart-2efc7d64-b58c-4d3b-8fc1-630cc22c8fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484605233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1484605233
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.257792632
Short name T602
Test name
Test status
Simulation time 36609247 ps
CPU time 2.1 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 208780 kb
Host smart-870fcd84-d745-45a2-99ef-dbdab8b708b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257792632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.257792632
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.970588476
Short name T784
Test name
Test status
Simulation time 362878007 ps
CPU time 3.58 seconds
Started Apr 28 12:41:57 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 213688 kb
Host smart-5e35e52e-2882-4ea3-bd30-6441c1a8dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970588476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.970588476
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2737488934
Short name T699
Test name
Test status
Simulation time 597115814 ps
CPU time 4.87 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 209276 kb
Host smart-e0498bfe-fa36-472d-a483-401cbbbfaea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737488934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2737488934
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3169411142
Short name T750
Test name
Test status
Simulation time 131211769 ps
CPU time 5.68 seconds
Started Apr 28 12:41:52 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 206908 kb
Host smart-b8b545be-6f5b-424c-8fd6-f1170949e7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169411142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3169411142
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1664078438
Short name T308
Test name
Test status
Simulation time 318216730 ps
CPU time 4.82 seconds
Started Apr 28 12:42:01 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 206312 kb
Host smart-744d7294-f8c2-4034-88cc-6dfdda7e4cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664078438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1664078438
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.592254977
Short name T571
Test name
Test status
Simulation time 102873451 ps
CPU time 4.73 seconds
Started Apr 28 12:42:01 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 208344 kb
Host smart-12bd3cd6-d2c4-4c4a-af4e-9576b02424c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592254977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.592254977
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.687984161
Short name T528
Test name
Test status
Simulation time 93693202 ps
CPU time 3.55 seconds
Started Apr 28 12:41:56 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 206352 kb
Host smart-2ea35150-b006-46ee-bee5-f877e1920da2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687984161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.687984161
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.99924853
Short name T781
Test name
Test status
Simulation time 42273318 ps
CPU time 1.85 seconds
Started Apr 28 12:41:58 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 206896 kb
Host smart-66258f17-1e63-4561-b87e-7c332c181b9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99924853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.99924853
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.802588901
Short name T541
Test name
Test status
Simulation time 123534196 ps
CPU time 2.61 seconds
Started Apr 28 12:42:16 PM PDT 24
Finished Apr 28 12:42:19 PM PDT 24
Peak memory 214084 kb
Host smart-a9fd5c54-afbf-4ebd-8432-1325f8ab864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802588901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.802588901
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.920032507
Short name T491
Test name
Test status
Simulation time 683867149 ps
CPU time 3.1 seconds
Started Apr 28 12:41:59 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 208000 kb
Host smart-9c90e037-5422-47e0-954c-514523d9fdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920032507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.920032507
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3475770909
Short name T763
Test name
Test status
Simulation time 264124405 ps
CPU time 5.19 seconds
Started Apr 28 12:42:13 PM PDT 24
Finished Apr 28 12:42:20 PM PDT 24
Peak memory 219884 kb
Host smart-29cad4cf-8fd2-422c-aed6-9abe60964b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475770909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3475770909
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1111493579
Short name T619
Test name
Test status
Simulation time 202434021 ps
CPU time 5.71 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:09 PM PDT 24
Peak memory 207188 kb
Host smart-74dab71b-fada-418c-985c-9148513d7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111493579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1111493579
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1359985012
Short name T47
Test name
Test status
Simulation time 77417454 ps
CPU time 2.53 seconds
Started Apr 28 12:42:02 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 209624 kb
Host smart-fbd83bfa-7bf2-4a57-8f32-6153b1df5db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359985012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1359985012
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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