Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3611622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

572542

1

T1

200

T2

667

T3

509

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3795359	1			T1	410		T2	1684		T3	692
values[0x0]	192618	1			T1	63		T2	232		T3	205
values[0x1]	196187	1			T1	66		T2	243		T3	175

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2462119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1722045

1

T1

279

T2

1103

T3

671

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14221	1			T1	1		T2	12		T13	16
valid_sources[0x01]	25829	1			T1	12		T2	10		T13	120
valid_sources[0x02]	15393	1			T1	8		T2	9		T13	44
valid_sources[0x03]	14774	1			T1	4		T2	6		T13	46
valid_sources[0x04]	13233	1			T2	15		T13	24		T18	482
valid_sources[0x05]	14472	1			T2	12		T13	7		T16	9
valid_sources[0x06]	15100	1			T1	6		T2	11		T3	1072
valid_sources[0x07]	14745	1			T1	4		T2	10		T13	23
valid_sources[0x08]	15567	1			T1	2		T2	18		T13	27
valid_sources[0x09]	18388	1			T2	8		T13	64		T18	410
valid_sources[0x0a]	13442	1			T1	2		T2	5		T13	45
valid_sources[0x0b]	13099	1			T1	1		T2	5		T13	66
valid_sources[0x0c]	12963	1			T1	6		T2	5		T13	21
valid_sources[0x0d]	14607	1			T1	5		T2	4		T13	166
valid_sources[0x0e]	13218	1			T1	2		T2	2		T13	16
valid_sources[0x0f]	15738	1			T2	4		T13	31		T18	367
valid_sources[0x10]	13675	1			T2	12		T13	148		T16	22
valid_sources[0x11]	12946	1			T1	3		T2	23		T13	38
valid_sources[0x12]	20709	1			T1	1		T2	12		T13	29
valid_sources[0x13]	14428	1			T2	8		T13	56		T16	8
valid_sources[0x14]	13730	1			T1	1		T2	4		T13	52
valid_sources[0x15]	14429	1			T1	2		T2	7		T13	98
valid_sources[0x16]	16257	1			T1	3		T2	6		T13	76
valid_sources[0x17]	13910	1			T1	1		T2	2		T13	54
valid_sources[0x18]	14458	1			T1	3		T2	4		T13	65
valid_sources[0x19]	14449	1			T1	1		T2	6		T13	69
valid_sources[0x1a]	13446	1			T1	1		T2	5		T13	13
valid_sources[0x1b]	14102	1			T1	1		T2	1		T13	9
valid_sources[0x1c]	12818	1			T1	1		T2	14		T13	14
valid_sources[0x1d]	13899	1			T1	1		T2	3		T13	96
valid_sources[0x1e]	14869	1			T1	1		T2	2		T13	31
valid_sources[0x1f]	13263	1			T2	9		T13	26		T16	14
valid_sources[0x20]	12798	1			T1	5		T2	3		T13	23
valid_sources[0x21]	13075	1			T2	9		T13	37		T17	2
valid_sources[0x22]	13062	1			T2	7		T13	75		T16	1
valid_sources[0x23]	12897	1			T1	4		T2	4		T13	16
valid_sources[0x24]	15231	1			T1	3		T2	26		T13	55
valid_sources[0x25]	14146	1			T1	1		T2	10		T13	102
valid_sources[0x26]	13989	1			T2	15		T13	43		T16	14
valid_sources[0x27]	15332	1			T1	1		T2	10		T13	63
valid_sources[0x28]	12967	1			T1	5		T2	13		T13	44
valid_sources[0x29]	13078	1			T1	6		T2	8		T13	57
valid_sources[0x2a]	14181	1			T2	3		T13	41		T18	461
valid_sources[0x2b]	15872	1			T1	2		T2	1		T13	39
valid_sources[0x2c]	13545	1			T2	7		T13	44		T17	5
valid_sources[0x2d]	14114	1			T1	1		T2	9		T13	50
valid_sources[0x2e]	14877	1			T2	9		T13	37		T16	8
valid_sources[0x2f]	13752	1			T1	2		T2	14		T13	47
valid_sources[0x30]	14503	1			T1	4		T2	4		T13	52
valid_sources[0x31]	17390	1			T1	6		T2	14		T13	133
valid_sources[0x32]	13405	1			T1	2		T2	7		T13	30
valid_sources[0x33]	14062	1			T2	8		T13	70		T16	15
valid_sources[0x34]	14272	1			T1	3		T2	15		T13	31
valid_sources[0x35]	13438	1			T1	2		T2	5		T13	29
valid_sources[0x36]	14288	1			T1	7		T2	2		T13	30
valid_sources[0x37]	13956	1			T1	1		T2	6		T13	29
valid_sources[0x38]	13351	1			T1	1		T2	7		T13	38
valid_sources[0x39]	13753	1			T1	3		T2	8		T13	55
valid_sources[0x3a]	23025	1			T1	1		T2	11		T13	57
valid_sources[0x3b]	14582	1			T2	2		T13	39		T16	15
valid_sources[0x3c]	13367	1			T2	30		T13	40		T18	522
valid_sources[0x3d]	13468	1			T1	1		T2	5		T13	72
valid_sources[0x3e]	13331	1			T1	2		T2	2		T13	89
valid_sources[0x3f]	12963	1			T1	2		T2	14		T13	9
valid_sources[0x40]	14324	1			T1	1		T2	7		T13	87
valid_sources[0x41]	13393	1			T1	4		T2	1		T13	88
valid_sources[0x42]	14328	1			T2	8		T13	61		T16	4
valid_sources[0x43]	15427	1			T1	2		T2	4		T13	62
valid_sources[0x44]	13261	1			T1	1		T2	6		T13	34
valid_sources[0x45]	13357	1			T1	1		T2	17		T13	39
valid_sources[0x46]	15655	1			T1	2		T2	21		T13	30
valid_sources[0x47]	13067	1			T2	9		T13	53		T18	469
valid_sources[0x48]	13331	1			T1	2		T2	6		T13	15
valid_sources[0x49]	15469	1			T2	14		T13	35		T16	3
valid_sources[0x4a]	13734	1			T1	3		T2	7		T13	43
valid_sources[0x4b]	14089	1			T1	2		T2	17		T13	36
valid_sources[0x4c]	14633	1			T2	2		T13	37		T16	4
valid_sources[0x4d]	13959	1			T2	12		T13	105		T16	1
valid_sources[0x4e]	13876	1			T2	6		T13	19		T17	8
valid_sources[0x4f]	14807	1			T1	1		T2	5		T13	59
valid_sources[0x50]	13334	1			T1	2		T2	9		T13	56
valid_sources[0x51]	14013	1			T1	5		T2	9		T13	34
valid_sources[0x52]	15011	1			T1	4		T2	14		T13	79
valid_sources[0x53]	13158	1			T1	5		T2	13		T13	28
valid_sources[0x54]	14042	1			T1	2		T2	18		T13	50
valid_sources[0x55]	13099	1			T1	3		T2	13		T13	91
valid_sources[0x56]	15477	1			T1	6		T2	2		T13	74
valid_sources[0x57]	13938	1			T1	2		T2	6		T13	59
valid_sources[0x58]	18776	1			T2	17		T13	84		T17	4
valid_sources[0x59]	15203	1			T1	5		T2	18		T13	1
valid_sources[0x5a]	13416	1			T1	2		T2	3		T13	6
valid_sources[0x5b]	13225	1			T1	2		T2	5		T13	30
valid_sources[0x5c]	13270	1			T2	10		T13	55		T18	475
valid_sources[0x5d]	16154	1			T1	2		T2	8		T13	3
valid_sources[0x5e]	20816	1			T1	7		T2	5		T13	95
valid_sources[0x5f]	12895	1			T1	2		T2	4		T13	40
valid_sources[0x60]	14430	1			T1	2		T2	8		T13	28
valid_sources[0x61]	14323	1			T1	2		T2	8		T13	67
valid_sources[0x62]	16340	1			T2	9		T13	37		T18	472
valid_sources[0x63]	23768	1			T1	1		T2	18		T13	29
valid_sources[0x64]	14312	1			T1	1		T2	8		T13	43
valid_sources[0x65]	13444	1			T1	5		T2	7		T13	27
valid_sources[0x66]	17015	1			T2	9		T13	16		T18	507
valid_sources[0x67]	14046	1			T2	6		T13	33		T18	543
valid_sources[0x68]	14257	1			T1	3		T2	11		T13	30
valid_sources[0x69]	20595	1			T1	6		T2	9		T13	28
valid_sources[0x6a]	23538	1			T2	9		T13	69		T16	21
valid_sources[0x6b]	13781	1			T1	1		T2	1		T13	47
valid_sources[0x6c]	14180	1			T1	2		T2	1		T13	52
valid_sources[0x6d]	44893	1			T2	14		T13	40		T16	22
valid_sources[0x6e]	13415	1			T1	1		T2	3		T13	29
valid_sources[0x6f]	13896	1			T1	2		T2	6		T13	96
valid_sources[0x70]	15709	1			T2	9		T13	18		T18	526
valid_sources[0x71]	15094	1			T1	2		T2	3		T13	51
valid_sources[0x72]	32968	1			T2	15		T13	134		T18	512
valid_sources[0x73]	13796	1			T1	2		T2	17		T13	59
valid_sources[0x74]	15726	1			T1	4		T2	15		T13	71
valid_sources[0x75]	15423	1			T2	1		T13	42		T17	4
valid_sources[0x76]	14821	1			T2	11		T13	104		T18	404
valid_sources[0x77]	14628	1			T1	3		T13	24		T16	20
valid_sources[0x78]	13765	1			T1	6		T2	8		T13	124
valid_sources[0x79]	13801	1			T1	3		T2	4		T13	92
valid_sources[0x7a]	13512	1			T1	4		T2	17		T13	45
valid_sources[0x7b]	25331	1			T1	4		T2	11		T13	122
valid_sources[0x7c]	12975	1			T1	1		T2	7		T13	32
valid_sources[0x7d]	118653	1			T1	3		T2	12		T13	81
valid_sources[0x7e]	15341	1			T1	1		T2	4		T13	40
valid_sources[0x7f]	13522	1			T1	2		T2	13		T13	32
valid_sources[0x80]	14596	1			T1	7		T2	19		T13	97

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

309176

1

T1

163

T2

325

T3

237

values[0x0]

all_enables

biggest_size

138160

1

T1

21

T2

182

T3

155

values[0x1]

all_enables

biggest_size

125206

1

T1

16

T2

160

T3

117