SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 4218752 | 0 | T1 | 539 | T2 | 2159 | T3 | 1072 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4218520 | 1 | T1 | 539 | T2 | 2159 | T3 | 1072 | ||||
values[1] | 34 | 1 | T377 | 1 | T135 | 1 | T136 | 1 | ||||
values[2] | 1 | 1 | T167 | 1 | - | - | - | - | ||||
values[3] | 118 | 1 | T54 | 1 | T112 | 1 | T158 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4218527 | 1 | T1 | 538 | T2 | 2159 | T3 | 1072 | ||||
values[1] | 24 | 1 | T45 | 1 | T378 | 1 | T177 | 1 | ||||
values[2] | 6 | 1 | T162 | 1 | T166 | 1 | T165 | 1 | ||||
values[3] | 108 | 1 | T1 | 1 | T46 | 1 | T185 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4218403 | 1 | T1 | 538 | T2 | 2159 | T3 | 1072 | ||||
auto[TlIntgErrCmd] | 124 | 1 | T54 | 1 | T112 | 1 | T158 | 1 | ||||
auto[TlIntgErrData] | 117 | 1 | T1 | 1 | T45 | 1 | T185 | 1 | ||||
auto[TlIntgErrBoth] | 108 | 1 | T46 | 1 | T379 | 1 | T153 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |