SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_sideload_ctrl.u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[0].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[1].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[2].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[3].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[4].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[5].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[6].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[7].u_mubi_buf | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_sideload_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 7785 | 7785 | 0 | 0 |
OutputsKnown_A | 239005998 | 237589776 | 0 | 0 |
gen_no_flops.OutputDelay_A | 239005998 | 237589776 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7785 | 7785 | 0 | 0 |
T1 | 9 | 9 | 0 | 0 |
T2 | 9 | 9 | 0 | 0 |
T3 | 9 | 9 | 0 | 0 |
T13 | 9 | 9 | 0 | 0 |
T14 | 9 | 9 | 0 | 0 |
T15 | 9 | 9 | 0 | 0 |
T16 | 9 | 9 | 0 | 0 |
T17 | 9 | 9 | 0 | 0 |
T18 | 9 | 9 | 0 | 0 |
T19 | 9 | 9 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 239005998 | 237589776 | 0 | 0 |
T1 | 17451 | 15714 | 0 | 0 |
T2 | 202950 | 201573 | 0 | 0 |
T3 | 92448 | 91944 | 0 | 0 |
T13 | 1305756 | 1304964 | 0 | 0 |
T14 | 53118 | 52236 | 0 | 0 |
T15 | 31365 | 30645 | 0 | 0 |
T16 | 79749 | 78633 | 0 | 0 |
T17 | 32436 | 31644 | 0 | 0 |
T18 | 1391805 | 1390878 | 0 | 0 |
T19 | 29349 | 28800 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 239005998 | 237589776 | 0 | 0 |
T1 | 17451 | 15714 | 0 | 0 |
T2 | 202950 | 201573 | 0 | 0 |
T3 | 92448 | 91944 | 0 | 0 |
T13 | 1305756 | 1304964 | 0 | 0 |
T14 | 53118 | 52236 | 0 | 0 |
T15 | 31365 | 30645 | 0 | 0 |
T16 | 79749 | 78633 | 0 | 0 |
T17 | 32436 | 31644 | 0 | 0 |
T18 | 1391805 | 1390878 | 0 | 0 |
T19 | 29349 | 28800 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 865 | 865 | 0 | 0 |
OutputsKnown_A | 26556222 | 26398864 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26556222 | 26398864 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 865 | 865 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26556222 | 26398864 | 0 | 0 |
T1 | 1939 | 1746 | 0 | 0 |
T2 | 22550 | 22397 | 0 | 0 |
T3 | 10272 | 10216 | 0 | 0 |
T13 | 145084 | 144996 | 0 | 0 |
T14 | 5902 | 5804 | 0 | 0 |
T15 | 3485 | 3405 | 0 | 0 |
T16 | 8861 | 8737 | 0 | 0 |
T17 | 3604 | 3516 | 0 | 0 |
T18 | 154645 | 154542 | 0 | 0 |
T19 | 3261 | 3200 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |