Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3336867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

605864

1

T1

519

T2

295

T3

245

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3531330	1			T1	1258		T2	32082		T3	502
values[0x0]	203978	1			T1	174		T2	110		T3	64
values[0x1]	207423	1			T1	171		T2	121		T3	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2282333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1660398

1

T1

831

T2

10923

T3

337

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12750	1			T2	157		T4	9		T14	4
valid_sources[0x01]	13884	1			T2	133		T4	8		T14	3
valid_sources[0x02]	12160	1			T2	148		T4	18		T14	1
valid_sources[0x03]	20427	1			T2	127		T4	7		T14	2
valid_sources[0x04]	12767	1			T2	150		T16	3		T18	34
valid_sources[0x05]	29395	1			T2	141		T4	1		T14	2
valid_sources[0x06]	12681	1			T2	127		T14	4		T16	6
valid_sources[0x07]	19260	1			T2	96		T4	3		T14	3
valid_sources[0x08]	12655	1			T2	140		T4	11		T14	2
valid_sources[0x09]	13239	1			T2	104		T4	35		T14	1
valid_sources[0x0a]	13954	1			T2	141		T4	16		T16	4
valid_sources[0x0b]	12977	1			T2	134		T4	37		T14	2
valid_sources[0x0c]	13029	1			T2	110		T4	20		T16	4
valid_sources[0x0d]	11895	1			T2	142		T4	3		T14	4
valid_sources[0x0e]	11380	1			T2	143		T4	3		T14	2
valid_sources[0x0f]	12367	1			T2	96		T4	4		T14	1
valid_sources[0x10]	13755	1			T2	104		T4	17		T16	1
valid_sources[0x11]	13791	1			T2	135		T4	19		T14	1
valid_sources[0x12]	12409	1			T2	109		T14	2		T16	16
valid_sources[0x13]	12766	1			T2	128		T14	3		T16	1
valid_sources[0x14]	16929	1			T2	102		T14	6		T16	5
valid_sources[0x15]	11987	1			T2	106		T14	4		T19	8
valid_sources[0x16]	14188	1			T1	1603		T2	143		T4	2
valid_sources[0x17]	12962	1			T2	105		T14	2		T16	1
valid_sources[0x18]	13552	1			T2	126		T4	6		T16	3
valid_sources[0x19]	12090	1			T2	193		T4	19		T14	4
valid_sources[0x1a]	14837	1			T2	163		T16	8		T19	19
valid_sources[0x1b]	20943	1			T2	120		T4	13		T14	3
valid_sources[0x1c]	13133	1			T2	112		T14	1		T16	6
valid_sources[0x1d]	14199	1			T2	116		T4	5		T14	1
valid_sources[0x1e]	35649	1			T2	139		T4	16		T14	2
valid_sources[0x1f]	12330	1			T2	109		T4	4		T14	1
valid_sources[0x20]	13869	1			T2	84		T16	2		T19	13
valid_sources[0x21]	13188	1			T2	106		T4	5		T14	2
valid_sources[0x22]	12077	1			T2	102		T4	3		T14	2
valid_sources[0x23]	15279	1			T2	144		T4	10		T14	3
valid_sources[0x24]	12705	1			T2	98		T16	3		T19	11
valid_sources[0x25]	13794	1			T2	130		T14	4		T16	4
valid_sources[0x26]	12968	1			T2	150		T4	7		T16	3
valid_sources[0x27]	20184	1			T2	144		T4	68		T14	1
valid_sources[0x28]	19280	1			T2	135		T4	7		T16	7
valid_sources[0x29]	13286	1			T2	135		T14	1		T16	6
valid_sources[0x2a]	13134	1			T2	165		T4	1		T14	5
valid_sources[0x2b]	39230	1			T2	101		T4	9		T14	1
valid_sources[0x2c]	14100	1			T2	123		T4	37		T16	6
valid_sources[0x2d]	12639	1			T2	124		T3	636		T14	1
valid_sources[0x2e]	12696	1			T2	114		T4	6		T16	2
valid_sources[0x2f]	12722	1			T2	101		T14	1		T19	17
valid_sources[0x30]	20368	1			T2	117		T4	2		T14	2
valid_sources[0x31]	12317	1			T2	130		T4	16		T16	2
valid_sources[0x32]	11920	1			T2	163		T4	10		T16	6
valid_sources[0x33]	14670	1			T2	138		T4	2		T14	3
valid_sources[0x34]	14136	1			T2	90		T4	7		T14	3
valid_sources[0x35]	12554	1			T2	118		T4	4		T16	3
valid_sources[0x36]	13715	1			T2	111		T4	3		T16	8
valid_sources[0x37]	12748	1			T2	98		T14	1		T19	13
valid_sources[0x38]	13812	1			T2	124		T4	8		T14	1
valid_sources[0x39]	15816	1			T2	114		T4	4		T14	5
valid_sources[0x3a]	12608	1			T2	169		T4	6		T14	1
valid_sources[0x3b]	16621	1			T2	160		T14	1		T16	3
valid_sources[0x3c]	12099	1			T2	83		T14	1		T16	12
valid_sources[0x3d]	14553	1			T2	131		T4	4		T14	4
valid_sources[0x3e]	12612	1			T2	129		T14	9		T16	7
valid_sources[0x3f]	22469	1			T2	143		T14	1		T16	19
valid_sources[0x40]	12906	1			T2	141		T4	21		T14	2
valid_sources[0x41]	12982	1			T2	122		T4	3		T16	3
valid_sources[0x42]	14537	1			T2	126		T4	3		T16	3
valid_sources[0x43]	13477	1			T2	114		T4	5		T14	2
valid_sources[0x44]	17247	1			T2	111		T4	1		T14	2
valid_sources[0x45]	12939	1			T2	181		T14	1		T16	10
valid_sources[0x46]	16284	1			T2	131		T4	47		T14	2
valid_sources[0x47]	12287	1			T2	131		T4	6		T14	2
valid_sources[0x48]	12579	1			T2	141		T14	4		T18	17
valid_sources[0x49]	12082	1			T2	91		T4	14		T16	3
valid_sources[0x4a]	18282	1			T2	109		T4	4		T14	1
valid_sources[0x4b]	12529	1			T2	109		T4	2		T14	1
valid_sources[0x4c]	17499	1			T2	111		T4	13		T14	4
valid_sources[0x4d]	22523	1			T2	109		T4	2		T14	4
valid_sources[0x4e]	13219	1			T2	151		T4	4		T14	4
valid_sources[0x4f]	12949	1			T2	108		T4	19		T14	3
valid_sources[0x50]	72234	1			T2	114		T4	3		T14	3
valid_sources[0x51]	21191	1			T2	130		T4	17		T16	9
valid_sources[0x52]	16744	1			T2	152		T4	43		T14	1
valid_sources[0x53]	12043	1			T2	82		T14	1		T16	3
valid_sources[0x54]	13118	1			T2	125		T4	3		T14	1
valid_sources[0x55]	12650	1			T2	125		T4	18		T14	8
valid_sources[0x56]	13553	1			T2	148		T4	12		T14	1
valid_sources[0x57]	13256	1			T2	133		T4	4		T14	2
valid_sources[0x58]	14208	1			T2	126		T4	25		T14	2
valid_sources[0x59]	12728	1			T2	114		T4	16		T14	2
valid_sources[0x5a]	13214	1			T2	109		T14	2		T16	15
valid_sources[0x5b]	13225	1			T2	103		T4	12		T16	12
valid_sources[0x5c]	17829	1			T2	152		T4	1		T14	5
valid_sources[0x5d]	13468	1			T2	141		T4	18		T14	1
valid_sources[0x5e]	11865	1			T2	127		T4	40		T14	2
valid_sources[0x5f]	13309	1			T2	167		T4	9		T14	3
valid_sources[0x60]	12269	1			T2	121		T4	4		T14	3
valid_sources[0x61]	16046	1			T2	132		T4	4		T14	3
valid_sources[0x62]	12744	1			T2	159		T4	29		T14	3
valid_sources[0x63]	12052	1			T2	124		T4	1		T14	2
valid_sources[0x64]	12405	1			T2	138		T16	4		T19	22
valid_sources[0x65]	18638	1			T2	122		T4	7		T14	5
valid_sources[0x66]	12734	1			T2	121		T4	33		T16	7
valid_sources[0x67]	18516	1			T2	113		T4	6		T14	3
valid_sources[0x68]	18144	1			T2	127		T14	1		T16	3
valid_sources[0x69]	21293	1			T2	137		T4	3		T14	1
valid_sources[0x6a]	51403	1			T2	117		T14	4		T16	12
valid_sources[0x6b]	12716	1			T2	106		T4	11		T14	4
valid_sources[0x6c]	12929	1			T2	150		T14	3		T16	4
valid_sources[0x6d]	12428	1			T2	144		T4	17		T16	11
valid_sources[0x6e]	12791	1			T2	107		T4	2		T18	9
valid_sources[0x6f]	17735	1			T2	176		T4	11		T14	2
valid_sources[0x70]	11519	1			T2	126		T4	23		T16	7
valid_sources[0x71]	13532	1			T2	173		T4	32		T14	2
valid_sources[0x72]	13130	1			T2	123		T14	1		T16	4
valid_sources[0x73]	12867	1			T2	120		T4	3		T14	4
valid_sources[0x74]	15362	1			T2	106		T4	6		T14	1
valid_sources[0x75]	13135	1			T2	143		T4	1		T14	2
valid_sources[0x76]	14006	1			T2	143		T4	9		T14	1
valid_sources[0x77]	14795	1			T2	118		T4	3		T14	2
valid_sources[0x78]	12647	1			T2	99		T4	14		T14	2
valid_sources[0x79]	13365	1			T2	106		T4	19		T14	7
valid_sources[0x7a]	13066	1			T2	149		T4	17		T14	1
valid_sources[0x7b]	11865	1			T2	108		T4	47		T14	3
valid_sources[0x7c]	14132	1			T2	174		T4	7		T16	9
valid_sources[0x7d]	11912	1			T2	102		T4	2		T16	4
valid_sources[0x7e]	32005	1			T2	118		T16	7		T18	30
valid_sources[0x7f]	12771	1			T2	128		T4	5		T14	3
valid_sources[0x80]	12709	1			T2	115		T4	8		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325982

1

T1

272

T2

178

T3

200

values[0x0]

all_enables

biggest_size

147481

1

T1

130

T2

60

T3

28

values[0x1]

all_enables

biggest_size

132401

1

T1

117

T2

57

T3

17