Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
25196235 |
25037167 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25196235 |
25037167 |
0 |
0 |
T1 |
5387 |
5256 |
0 |
0 |
T2 |
161942 |
161881 |
0 |
0 |
T3 |
2389 |
2327 |
0 |
0 |
T4 |
5338 |
5259 |
0 |
0 |
T14 |
1963 |
1881 |
0 |
0 |
T15 |
7520 |
7470 |
0 |
0 |
T16 |
17018 |
16924 |
0 |
0 |
T17 |
9954 |
9901 |
0 |
0 |
T18 |
12911 |
12824 |
0 |
0 |
T19 |
35567 |
35077 |
0 |
0 |