Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27613446	19636	0	0
attest_sw_binding_0_rd_A	27613446	2986	0	0
attest_sw_binding_1_rd_A	27613446	2990	0	0
attest_sw_binding_2_rd_A	27613446	3089	0	0
attest_sw_binding_3_rd_A	27613446	3045	0	0
attest_sw_binding_4_rd_A	27613446	3090	0	0
attest_sw_binding_5_rd_A	27613446	3179	0	0
attest_sw_binding_6_rd_A	27613446	3125	0	0
attest_sw_binding_7_rd_A	27613446	3002	0	0
intr_enable_rd_A	27613446	3513	0	0
key_version_rd_A	27613446	2920	0	0
max_creator_key_ver_regwen_rd_A	27613446	3077	0	0
max_owner_int_key_ver_regwen_rd_A	27613446	3101	0	0
max_owner_key_ver_regwen_rd_A	27613446	3037	0	0
reseed_interval_regwen_rd_A	27613446	3050	0	0
salt_0_rd_A	27613446	3041	0	0
salt_1_rd_A	27613446	2988	0	0
salt_2_rd_A	27613446	3030	0	0
salt_3_rd_A	27613446	3051	0	0
salt_4_rd_A	27613446	3009	0	0
salt_5_rd_A	27613446	2955	0	0
salt_6_rd_A	27613446	3011	0	0
salt_7_rd_A	27613446	2875	0	0
sealing_sw_binding_0_rd_A	27613446	2987	0	0
sealing_sw_binding_1_rd_A	27613446	2910	0	0
sealing_sw_binding_2_rd_A	27613446	2958	0	0
sealing_sw_binding_3_rd_A	27613446	3092	0	0
sealing_sw_binding_4_rd_A	27613446	2874	0	0
sealing_sw_binding_5_rd_A	27613446	3002	0	0
sealing_sw_binding_6_rd_A	27613446	2917	0	0
sealing_sw_binding_7_rd_A	27613446	3004	0	0
sideload_clear_rd_A	27613446	2947	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	19636	0	0
T19	35567	93	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T60	0	31	0	0
T63	0	920	0	0
T64	0	189	0	0
T71	0	183	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T114	0	226	0	0
T120	0	91	0	0
T121	0	421	0	0
T122	0	492	0	0
T123	0	887	0	0
T124	9121	0	0	0
T125	19269	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2986	0	0
T19	35567	27	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	220	0	0
T120	0	38	0	0
T121	0	37	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	28	0	0
T175	0	17	0	0
T176	0	22	0	0
T177	0	42	0	0
T178	0	11	0	0
T179	0	22	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2990	0	0
T19	35567	17	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	192	0	0
T120	0	37	0	0
T121	0	53	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	28	0	0
T175	0	33	0	0
T176	0	59	0	0
T177	0	47	0	0
T178	0	29	0	0
T179	0	28	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3089	0	0
T19	35567	31	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T120	0	28	0	0
T121	0	43	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	22	0	0
T175	0	51	0	0
T176	0	46	0	0
T177	0	36	0	0
T178	0	20	0	0
T179	0	25	0	0
T180	0	7	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3045	0	0
T19	35567	17	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	197	0	0
T120	0	30	0	0
T121	0	62	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	20	0	0
T175	0	26	0	0
T176	0	46	0	0
T177	0	43	0	0
T178	0	15	0	0
T179	0	19	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3090	0	0
T19	35567	28	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	216	0	0
T120	0	29	0	0
T121	0	52	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	33	0	0
T175	0	24	0	0
T176	0	17	0	0
T177	0	39	0	0
T178	0	13	0	0
T179	0	21	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3179	0	0
T19	35567	20	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	211	0	0
T120	0	25	0	0
T121	0	37	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	28	0	0
T175	0	48	0	0
T176	0	32	0	0
T177	0	65	0	0
T178	0	2	0	0
T179	0	30	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3125	0	0
T19	35567	16	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	239	0	0
T120	0	41	0	0
T121	0	60	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	19	0	0
T175	0	25	0	0
T176	0	24	0	0
T177	0	51	0	0
T178	0	3	0	0
T179	0	45	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3002	0	0
T19	35567	15	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	204	0	0
T120	0	26	0	0
T121	0	49	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	30	0	0
T175	0	41	0	0
T176	0	50	0	0
T177	0	66	0	0
T178	0	11	0	0
T179	0	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3513	0	0
T19	35567	84	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T51	0	58	0	0
T74	0	26	0	0
T85	3676	0	0	0
T99	843	0	0	0
T105	0	9	0	0
T110	11549	0	0	0
T120	0	39	0	0
T121	0	32	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T175	0	62	0	0
T176	0	22	0	0
T181	0	6	0	0
T182	0	16	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2920	0	0
T19	35567	17	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	197	0	0
T120	0	32	0	0
T121	0	46	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	17	0	0
T175	0	25	0	0
T176	0	29	0	0
T177	0	29	0	0
T178	0	2	0	0
T179	0	6	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3077	0	0
T19	35567	24	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	249	0	0
T120	0	47	0	0
T121	0	36	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	28	0	0
T175	0	28	0	0
T176	0	30	0	0
T177	0	70	0	0
T178	0	5	0	0
T179	0	30	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3101	0	0
T19	35567	13	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	1	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T120	0	38	0	0
T121	0	46	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	42	0	0
T175	0	18	0	0
T176	0	45	0	0
T177	0	48	0	0
T178	0	8	0	0
T179	0	24	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3037	0	0
T19	35567	23	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T120	0	31	0	0
T121	0	56	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	7	0	0
T175	0	33	0	0
T176	0	38	0	0
T177	0	40	0	0
T178	0	8	0	0
T179	0	15	0	0
T183	0	5	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3050	0	0
T19	35567	30	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	191	0	0
T120	0	28	0	0
T121	0	58	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	35	0	0
T175	0	52	0	0
T176	0	23	0	0
T177	0	52	0	0
T178	0	12	0	0
T179	0	31	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3041	0	0
T19	35567	26	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	205	0	0
T120	0	28	0	0
T121	0	47	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	25	0	0
T175	0	36	0	0
T176	0	37	0	0
T177	0	46	0	0
T178	0	34	0	0
T179	0	16	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2988	0	0
T19	35567	25	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	218	0	0
T120	0	34	0	0
T121	0	54	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	33	0	0
T175	0	14	0	0
T176	0	45	0	0
T177	0	71	0	0
T178	0	19	0	0
T179	0	29	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3030	0	0
T19	35567	28	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T62	0	1	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T120	0	39	0	0
T121	0	42	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	19	0	0
T175	0	26	0	0
T176	0	25	0	0
T177	0	82	0	0
T178	0	26	0	0
T179	0	17	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3051	0	0
T19	35567	45	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	234	0	0
T120	0	39	0	0
T121	0	48	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	33	0	0
T175	0	56	0	0
T176	0	38	0	0
T177	0	51	0	0
T178	0	12	0	0
T179	0	39	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3009	0	0
T19	35567	20	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	199	0	0
T120	0	41	0	0
T121	0	52	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	12	0	0
T175	0	47	0	0
T176	0	34	0	0
T177	0	50	0	0
T178	0	23	0	0
T179	0	15	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2955	0	0
T19	35567	36	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	207	0	0
T120	0	24	0	0
T121	0	47	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	8	0	0
T175	0	32	0	0
T176	0	22	0	0
T177	0	34	0	0
T178	0	36	0	0
T179	0	38	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3011	0	0
T19	35567	23	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	241	0	0
T120	0	16	0	0
T121	0	41	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	7	0	0
T175	0	62	0	0
T176	0	27	0	0
T177	0	35	0	0
T178	0	39	0	0
T179	0	24	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2875	0	0
T19	35567	21	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	225	0	0
T120	0	33	0	0
T121	0	40	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	12	0	0
T175	0	54	0	0
T176	0	15	0	0
T177	0	36	0	0
T178	0	36	0	0
T179	0	22	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2987	0	0
T19	35567	14	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	226	0	0
T120	0	34	0	0
T121	0	49	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	12	0	0
T175	0	36	0	0
T176	0	23	0	0
T177	0	52	0	0
T178	0	29	0	0
T179	0	30	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2910	0	0
T19	35567	27	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T120	0	25	0	0
T121	0	55	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	6	0	0
T175	0	34	0	0
T176	0	24	0	0
T177	0	41	0	0
T178	0	8	0	0
T179	0	36	0	0
T184	0	10	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2958	0	0
T19	35567	11	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	224	0	0
T120	0	28	0	0
T121	0	67	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	33	0	0
T175	0	23	0	0
T176	0	24	0	0
T177	0	42	0	0
T178	0	7	0	0
T179	0	21	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3092	0	0
T19	35567	17	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	227	0	0
T120	0	35	0	0
T121	0	65	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	12	0	0
T175	0	33	0	0
T176	0	26	0	0
T177	0	44	0	0
T178	0	22	0	0
T179	0	48	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2874	0	0
T19	35567	29	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	241	0	0
T120	0	15	0	0
T121	0	46	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	17	0	0
T175	0	17	0	0
T176	0	43	0	0
T177	0	46	0	0
T178	0	3	0	0
T179	0	19	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3002	0	0
T19	35567	42	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	189	0	0
T120	0	47	0	0
T121	0	63	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	27	0	0
T175	0	35	0	0
T176	0	44	0	0
T177	0	61	0	0
T178	0	4	0	0
T179	0	22	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2917	0	0
T19	35567	24	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T108	0	1	0	0
T110	11549	0	0	0
T120	0	24	0	0
T121	0	73	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	3	0	0
T175	0	25	0	0
T176	0	26	0	0
T177	0	42	0	0
T178	0	18	0	0
T179	0	29	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	3004	0	0
T19	35567	31	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	220	0	0
T120	0	25	0	0
T121	0	66	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	18	0	0
T175	0	40	0	0
T176	0	22	0	0
T177	0	57	0	0
T178	0	12	0	0
T179	0	37	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27613446	2947	0	0
T19	35567	9	0	0
T20	10369	0	0	0
T37	3366	0	0	0
T38	14691	0	0	0
T39	9792	0	0	0
T85	3676	0	0	0
T99	843	0	0	0
T110	11549	0	0	0
T112	0	188	0	0
T120	0	20	0	0
T121	0	52	0	0
T124	9121	0	0	0
T125	19269	0	0	0
T149	0	8	0	0
T175	0	17	0	0
T176	0	16	0	0
T177	0	59	0	0
T178	0	21	0	0
T179	0	41	0	0