Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3692378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

637911

1

T1

151

T2

8

T3

2949

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3902947	1			T1	3159		T2	1		T3	3385
values[0x0]	212513	1			T1	46		T2	24		T3	1061
values[0x1]	214829	1			T1	44		T2	21		T3	1026

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2521291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1808998

1

T1

1186

T2

15

T3

3598

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15734	1			T3	20		T4	53		T16	3
valid_sources[0x01]	13090	1			T3	19		T4	41		T16	21
valid_sources[0x02]	13992	1			T3	30		T4	50		T16	16
valid_sources[0x03]	12635	1			T3	16		T4	46		T16	20
valid_sources[0x04]	12590	1			T3	28		T4	45		T16	3
valid_sources[0x05]	17373	1			T2	3		T3	27		T4	47
valid_sources[0x06]	14845	1			T3	14		T4	46		T16	11
valid_sources[0x07]	12571	1			T3	17		T4	50		T16	5
valid_sources[0x08]	16311	1			T3	30		T4	50		T16	28
valid_sources[0x09]	12746	1			T3	17		T4	47		T78	2
valid_sources[0x0a]	13181	1			T3	17		T4	53		T16	5
valid_sources[0x0b]	20146	1			T3	16		T4	38		T16	7
valid_sources[0x0c]	28711	1			T3	7		T4	54		T16	12
valid_sources[0x0d]	13053	1			T3	18		T4	47		T16	33
valid_sources[0x0e]	12654	1			T3	20		T4	49		T16	3
valid_sources[0x0f]	14647	1			T3	12		T4	42		T16	2
valid_sources[0x10]	12766	1			T3	6		T4	42		T40	4
valid_sources[0x11]	15694	1			T3	31		T4	49		T16	23
valid_sources[0x12]	12176	1			T3	23		T4	51		T16	15
valid_sources[0x13]	15467	1			T3	31		T4	61		T16	13
valid_sources[0x14]	13168	1			T3	30		T4	51		T16	12
valid_sources[0x15]	12766	1			T3	14		T4	38		T18	7
valid_sources[0x16]	12523	1			T3	15		T4	50		T16	33
valid_sources[0x17]	13974	1			T3	23		T4	41		T16	3
valid_sources[0x18]	13827	1			T3	41		T4	50		T16	2
valid_sources[0x19]	12563	1			T3	41		T4	40		T16	6
valid_sources[0x1a]	14688	1			T3	8		T4	38		T16	2
valid_sources[0x1b]	13217	1			T3	19		T4	48		T16	2
valid_sources[0x1c]	22622	1			T3	23		T4	49		T16	20
valid_sources[0x1d]	12986	1			T2	6		T3	22		T4	34
valid_sources[0x1e]	12461	1			T3	30		T4	38		T16	41
valid_sources[0x1f]	13293	1			T3	21		T4	48		T18	5
valid_sources[0x20]	12487	1			T3	15		T4	54		T16	13
valid_sources[0x21]	12056	1			T3	25		T4	54		T16	19
valid_sources[0x22]	14772	1			T3	15		T4	54		T16	9
valid_sources[0x23]	13580	1			T3	16		T4	51		T16	30
valid_sources[0x24]	13095	1			T3	43		T4	54		T16	2
valid_sources[0x25]	14011	1			T3	13		T4	44		T16	16
valid_sources[0x26]	13748	1			T3	16		T4	33		T16	5
valid_sources[0x27]	12595	1			T3	15		T4	53		T16	5
valid_sources[0x28]	17907	1			T3	13		T4	55		T16	10
valid_sources[0x29]	16630	1			T3	25		T4	47		T16	33
valid_sources[0x2a]	47485	1			T3	31		T4	49		T17	2
valid_sources[0x2b]	12653	1			T3	17		T4	55		T16	24
valid_sources[0x2c]	12655	1			T3	11		T4	46		T18	6
valid_sources[0x2d]	16302	1			T3	18		T4	55		T16	10
valid_sources[0x2e]	13104	1			T3	31		T4	55		T16	20
valid_sources[0x2f]	13177	1			T3	27		T4	48		T16	1
valid_sources[0x30]	17351	1			T3	18		T4	43		T17	5
valid_sources[0x31]	12570	1			T3	10		T4	45		T16	1
valid_sources[0x32]	14228	1			T2	6		T3	22		T4	51
valid_sources[0x33]	14460	1			T3	26		T4	60		T16	6
valid_sources[0x34]	16637	1			T3	28		T4	42		T16	22
valid_sources[0x35]	13007	1			T3	6		T4	57		T16	20
valid_sources[0x36]	16377	1			T3	24		T4	51		T16	30
valid_sources[0x37]	12406	1			T3	19		T4	46		T16	3
valid_sources[0x38]	19956	1			T3	30		T4	45		T16	9
valid_sources[0x39]	14554	1			T3	16		T4	36		T16	8
valid_sources[0x3a]	14060	1			T3	28		T4	53		T16	3
valid_sources[0x3b]	13034	1			T3	39		T4	52		T16	19
valid_sources[0x3c]	14722	1			T3	21		T4	45		T16	7
valid_sources[0x3d]	12463	1			T3	17		T4	48		T16	9
valid_sources[0x3e]	13344	1			T3	12		T4	45		T16	93
valid_sources[0x3f]	16000	1			T3	17		T4	55		T16	5
valid_sources[0x40]	14683	1			T3	18		T4	52		T16	39
valid_sources[0x41]	21932	1			T3	23		T4	38		T16	25
valid_sources[0x42]	12128	1			T3	22		T4	47		T16	3
valid_sources[0x43]	13700	1			T3	25		T4	51		T16	10
valid_sources[0x44]	14546	1			T3	23		T4	52		T16	10
valid_sources[0x45]	12950	1			T3	18		T4	68		T16	25
valid_sources[0x46]	11741	1			T3	15		T4	51		T16	12
valid_sources[0x47]	13088	1			T3	24		T4	44		T16	8
valid_sources[0x48]	14675	1			T3	10		T4	56		T40	6
valid_sources[0x49]	12892	1			T3	36		T4	49		T18	1
valid_sources[0x4a]	12639	1			T3	24		T4	50		T16	14
valid_sources[0x4b]	15062	1			T3	13		T4	50		T16	13
valid_sources[0x4c]	40077	1			T3	21		T4	56		T16	7
valid_sources[0x4d]	12203	1			T3	14		T4	62		T16	21
valid_sources[0x4e]	15325	1			T3	20		T4	38		T16	6
valid_sources[0x4f]	12225	1			T3	23		T4	52		T16	7
valid_sources[0x50]	53203	1			T3	28		T4	40		T16	3
valid_sources[0x51]	12470	1			T3	14		T4	39		T16	8
valid_sources[0x52]	13883	1			T3	9		T4	35		T16	7
valid_sources[0x53]	17251	1			T3	22		T4	38		T16	7
valid_sources[0x54]	13684	1			T3	36		T4	38		T16	14
valid_sources[0x55]	22720	1			T3	14		T4	50		T18	2
valid_sources[0x56]	13425	1			T3	7		T4	48		T16	15
valid_sources[0x57]	13330	1			T3	20		T4	57		T16	12
valid_sources[0x58]	14818	1			T3	29		T4	39		T16	7
valid_sources[0x59]	13688	1			T3	16		T4	52		T16	12
valid_sources[0x5a]	12753	1			T3	28		T4	62		T16	2
valid_sources[0x5b]	12552	1			T3	26		T4	43		T16	2
valid_sources[0x5c]	13757	1			T3	17		T4	42		T16	10
valid_sources[0x5d]	13035	1			T3	23		T4	50		T16	1
valid_sources[0x5e]	12630	1			T3	32		T4	50		T16	7
valid_sources[0x5f]	13020	1			T3	20		T4	48		T16	14
valid_sources[0x60]	12034	1			T3	17		T4	53		T18	14
valid_sources[0x61]	33687	1			T3	18		T4	50		T18	9
valid_sources[0x62]	15701	1			T3	22		T4	43		T40	3
valid_sources[0x63]	24271	1			T3	16		T4	60		T16	11
valid_sources[0x64]	12341	1			T3	3		T4	49		T16	4
valid_sources[0x65]	14611	1			T3	17		T4	59		T16	6
valid_sources[0x66]	14116	1			T3	28		T4	63		T16	4
valid_sources[0x67]	12585	1			T3	13		T4	53		T16	16
valid_sources[0x68]	13382	1			T3	38		T4	45		T16	11
valid_sources[0x69]	12794	1			T3	30		T4	48		T16	2
valid_sources[0x6a]	14138	1			T3	26		T4	52		T16	37
valid_sources[0x6b]	16925	1			T3	30		T4	53		T17	174
valid_sources[0x6c]	12709	1			T3	28		T4	61		T16	1
valid_sources[0x6d]	16455	1			T3	21		T4	52		T16	1
valid_sources[0x6e]	18998	1			T3	11		T4	46		T16	7
valid_sources[0x6f]	13474	1			T3	12		T4	46		T16	3
valid_sources[0x70]	14233	1			T3	28		T4	46		T16	14
valid_sources[0x71]	60316	1			T3	20		T4	37		T16	5
valid_sources[0x72]	13535	1			T3	18		T4	58		T16	13
valid_sources[0x73]	15756	1			T3	11		T4	41		T40	3
valid_sources[0x74]	13042	1			T3	22		T4	57		T16	16
valid_sources[0x75]	13811	1			T3	21		T4	44		T16	15
valid_sources[0x76]	15899	1			T3	22		T4	44		T16	18
valid_sources[0x77]	15019	1			T3	23		T4	56		T16	16
valid_sources[0x78]	14018	1			T3	18		T4	50		T17	77
valid_sources[0x79]	14576	1			T2	1		T3	22		T4	50
valid_sources[0x7a]	17871	1			T3	20		T4	53		T6	4495
valid_sources[0x7b]	13129	1			T2	5		T3	25		T4	59
valid_sources[0x7c]	13603	1			T3	11		T4	60		T16	24
valid_sources[0x7d]	27257	1			T3	29		T4	47		T16	1
valid_sources[0x7e]	99873	1			T3	18		T4	49		T16	38
valid_sources[0x7f]	35001	1			T3	17		T4	50		T16	12
valid_sources[0x80]	12882	1			T3	19		T4	59		T16	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

345133

1

T1

124

T3

1229

T4

129

values[0x0]

all_enables

biggest_size

154203

1

T1

16

T2

6

T3

874

values[0x1]

all_enables

biggest_size

138575

1

T1

11

T2

2

T3

846