Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
178326 |
0 |
0 |
T1 |
10441 |
2 |
0 |
0 |
T2 |
1465 |
0 |
0 |
0 |
T3 |
43645 |
174 |
0 |
0 |
T4 |
168386 |
14 |
0 |
0 |
T5 |
2095 |
2 |
0 |
0 |
T6 |
42998 |
91 |
0 |
0 |
T15 |
9512 |
175 |
0 |
0 |
T16 |
33731 |
2 |
0 |
0 |
T17 |
21736 |
82 |
0 |
0 |
T18 |
7196 |
2 |
0 |
0 |
T37 |
0 |
160 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
178317 |
0 |
0 |
T1 |
10441 |
2 |
0 |
0 |
T2 |
1465 |
0 |
0 |
0 |
T3 |
43645 |
174 |
0 |
0 |
T4 |
168386 |
14 |
0 |
0 |
T5 |
2095 |
2 |
0 |
0 |
T6 |
42998 |
91 |
0 |
0 |
T15 |
9512 |
175 |
0 |
0 |
T16 |
33731 |
2 |
0 |
0 |
T17 |
21736 |
82 |
0 |
0 |
T18 |
7196 |
2 |
0 |
0 |
T37 |
0 |
160 |
0 |
0 |