Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3092409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

620964

1

T1

302

T2

304

T3

135

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3290657	1			T1	2854		T2	583		T3	372
values[0x0]	209699	1			T1	74		T2	55		T3	33
values[0x1]	213017	1			T1	80		T2	67		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2120722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1592651

1

T1

1146

T2

404

T3

227

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11271	1			T1	8		T2	1		T3	1
valid_sources[0x01]	11156	1			T1	14		T2	11		T3	3
valid_sources[0x02]	33290	1			T1	9		T3	3		T14	1
valid_sources[0x03]	13864	1			T1	8		T2	7		T3	2
valid_sources[0x04]	13295	1			T1	15		T2	4		T3	1
valid_sources[0x05]	13359	1			T1	9		T2	2		T3	1
valid_sources[0x06]	14435	1			T1	14		T2	3		T3	2
valid_sources[0x07]	11569	1			T1	10		T2	1		T3	2
valid_sources[0x08]	13219	1			T1	10		T2	4		T3	2
valid_sources[0x09]	12334	1			T1	7		T2	3		T3	2
valid_sources[0x0a]	11295	1			T1	8		T2	6		T3	4
valid_sources[0x0b]	11664	1			T1	18		T2	5		T14	1
valid_sources[0x0c]	11291	1			T1	8		T3	2		T13	4
valid_sources[0x0d]	11671	1			T1	13		T3	2		T13	5
valid_sources[0x0e]	12519	1			T1	8		T3	3		T13	1
valid_sources[0x0f]	12808	1			T1	15		T2	9		T3	2
valid_sources[0x10]	12326	1			T1	11		T2	3		T3	2
valid_sources[0x11]	11351	1			T1	8		T2	10		T13	1
valid_sources[0x12]	12804	1			T1	17		T2	4		T3	3
valid_sources[0x13]	11515	1			T1	16		T2	4		T3	3
valid_sources[0x14]	11536	1			T1	10		T2	6		T3	6
valid_sources[0x15]	11744	1			T1	21		T3	1		T13	3
valid_sources[0x16]	11456	1			T1	18		T3	3		T15	4
valid_sources[0x17]	13797	1			T1	7		T2	14		T3	2
valid_sources[0x18]	16340	1			T1	12		T2	4		T13	1
valid_sources[0x19]	11596	1			T1	16		T13	8		T15	2
valid_sources[0x1a]	11712	1			T1	11		T3	2		T13	7
valid_sources[0x1b]	11388	1			T1	5		T2	3		T3	4
valid_sources[0x1c]	12663	1			T1	11		T3	3		T13	4
valid_sources[0x1d]	13189	1			T1	13		T3	3		T13	7
valid_sources[0x1e]	12920	1			T1	10		T2	2		T3	3
valid_sources[0x1f]	11307	1			T1	12		T2	4		T3	1
valid_sources[0x20]	11906	1			T1	8		T3	1		T10	1
valid_sources[0x21]	11388	1			T1	15		T3	2		T13	2
valid_sources[0x22]	12665	1			T1	7		T2	6		T3	1
valid_sources[0x23]	15717	1			T1	17		T2	3		T13	3
valid_sources[0x24]	15038	1			T1	15		T2	4		T3	3
valid_sources[0x25]	12120	1			T1	9		T2	1		T3	2
valid_sources[0x26]	11822	1			T1	6		T2	10		T3	3
valid_sources[0x27]	11797	1			T1	22		T2	3		T3	2
valid_sources[0x28]	12210	1			T1	11		T2	4		T3	1
valid_sources[0x29]	11363	1			T1	21		T2	4		T13	2
valid_sources[0x2a]	11652	1			T1	15		T13	4		T15	3
valid_sources[0x2b]	11261	1			T1	16		T2	4		T3	3
valid_sources[0x2c]	17491	1			T1	9		T2	1		T13	3
valid_sources[0x2d]	24072	1			T1	15		T2	2		T3	1
valid_sources[0x2e]	11561	1			T1	13		T2	1		T3	4
valid_sources[0x2f]	12411	1			T1	7		T2	10		T3	3
valid_sources[0x30]	11296	1			T1	7		T3	4		T13	2
valid_sources[0x31]	11118	1			T1	11		T3	1		T13	4
valid_sources[0x32]	10916	1			T1	11		T2	4		T13	4
valid_sources[0x33]	11340	1			T1	15		T13	4		T15	5
valid_sources[0x34]	12630	1			T1	14		T2	6		T3	1
valid_sources[0x35]	12005	1			T1	6		T2	1		T3	1
valid_sources[0x36]	13374	1			T1	5		T3	2		T13	2
valid_sources[0x37]	11932	1			T1	13		T2	10		T3	3
valid_sources[0x38]	29054	1			T1	13		T2	4		T3	2
valid_sources[0x39]	11693	1			T1	14		T2	3		T13	2
valid_sources[0x3a]	11715	1			T1	18		T2	2		T3	1
valid_sources[0x3b]	11841	1			T1	8		T13	5		T15	4
valid_sources[0x3c]	11308	1			T1	14		T3	1		T13	2
valid_sources[0x3d]	11440	1			T1	10		T13	5		T15	11
valid_sources[0x3e]	11369	1			T1	10		T2	4		T3	1
valid_sources[0x3f]	11151	1			T1	14		T2	3		T3	3
valid_sources[0x40]	30918	1			T1	16		T2	9		T3	3
valid_sources[0x41]	11634	1			T1	16		T2	2		T13	1
valid_sources[0x42]	14074	1			T1	19		T2	4		T3	1
valid_sources[0x43]	11437	1			T1	9		T3	1		T15	7
valid_sources[0x44]	11963	1			T1	11		T3	1		T13	1
valid_sources[0x45]	12873	1			T1	13		T2	4		T3	2
valid_sources[0x46]	11194	1			T1	11		T3	3		T13	2
valid_sources[0x47]	13322	1			T1	14		T2	4		T3	2
valid_sources[0x48]	12025	1			T1	11		T13	8		T15	2
valid_sources[0x49]	12112	1			T1	9		T2	1		T3	2
valid_sources[0x4a]	12555	1			T1	9		T2	4		T13	1
valid_sources[0x4b]	11797	1			T1	9		T2	1		T3	2
valid_sources[0x4c]	11778	1			T1	11		T2	1		T3	2
valid_sources[0x4d]	13211	1			T1	8		T3	2		T13	3
valid_sources[0x4e]	11395	1			T1	15		T2	1		T3	2
valid_sources[0x4f]	10962	1			T1	11		T2	5		T3	5
valid_sources[0x50]	11523	1			T1	14		T2	1		T3	3
valid_sources[0x51]	12135	1			T1	13		T2	10		T13	9
valid_sources[0x52]	35463	1			T1	7		T3	1		T13	3
valid_sources[0x53]	17320	1			T1	12		T3	2		T13	2
valid_sources[0x54]	11689	1			T1	7		T3	2		T13	3
valid_sources[0x55]	12787	1			T1	12		T2	3		T13	6
valid_sources[0x56]	11543	1			T1	18		T2	6		T3	3
valid_sources[0x57]	11235	1			T1	22		T2	5		T3	1
valid_sources[0x58]	21081	1			T1	10		T2	2		T3	3
valid_sources[0x59]	12449	1			T1	12		T2	13		T13	1
valid_sources[0x5a]	13381	1			T1	7		T2	1		T13	3
valid_sources[0x5b]	12041	1			T1	19		T2	3		T3	2
valid_sources[0x5c]	236920	1			T1	22		T13	4		T10	4
valid_sources[0x5d]	21992	1			T1	5		T2	1		T3	2
valid_sources[0x5e]	12366	1			T1	11		T13	2		T15	4
valid_sources[0x5f]	11880	1			T1	10		T3	5		T13	11
valid_sources[0x60]	11541	1			T1	7		T2	8		T3	2
valid_sources[0x61]	18017	1			T1	9		T2	10		T3	1
valid_sources[0x62]	12865	1			T1	6		T3	2		T13	2
valid_sources[0x63]	11400	1			T1	14		T13	2		T15	6
valid_sources[0x64]	14406	1			T1	8		T3	1		T13	6
valid_sources[0x65]	16267	1			T1	18		T2	6		T3	3
valid_sources[0x66]	15901	1			T1	7		T2	6		T13	5
valid_sources[0x67]	12422	1			T1	21		T2	2		T3	7
valid_sources[0x68]	22208	1			T1	3		T3	1		T13	3
valid_sources[0x69]	14377	1			T1	11		T2	2		T3	5
valid_sources[0x6a]	11327	1			T1	16		T2	1		T13	2
valid_sources[0x6b]	11029	1			T1	13		T13	4		T15	11
valid_sources[0x6c]	13944	1			T1	9		T13	1		T15	2
valid_sources[0x6d]	14252	1			T1	12		T2	9		T3	3
valid_sources[0x6e]	14115	1			T1	9		T2	1		T3	5
valid_sources[0x6f]	17669	1			T1	11		T2	2		T3	2
valid_sources[0x70]	13830	1			T1	8		T2	3		T3	3
valid_sources[0x71]	11670	1			T1	11		T2	1		T3	1
valid_sources[0x72]	11200	1			T1	21		T3	6		T13	6
valid_sources[0x73]	11520	1			T1	16		T2	2		T13	4
valid_sources[0x74]	11834	1			T1	10		T2	2		T3	3
valid_sources[0x75]	12740	1			T1	5		T2	5		T13	3
valid_sources[0x76]	13251	1			T1	11		T2	8		T3	2
valid_sources[0x77]	11304	1			T1	10		T3	1		T13	9
valid_sources[0x78]	11483	1			T1	11		T2	1		T3	3
valid_sources[0x79]	11127	1			T1	13		T3	1		T15	1
valid_sources[0x7a]	12456	1			T1	10		T2	3		T3	4
valid_sources[0x7b]	11613	1			T1	22		T15	3		T10	1
valid_sources[0x7c]	25442	1			T1	11		T2	8		T3	2
valid_sources[0x7d]	14349	1			T1	9		T3	3		T13	1
valid_sources[0x7e]	11317	1			T1	12		T3	1		T13	1
valid_sources[0x7f]	14481	1			T1	10		T3	3		T13	4
valid_sources[0x80]	11410	1			T1	10		T2	1		T13	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333241

1

T1

260

T2

261

T3

112

values[0x0]

all_enables

biggest_size

150942

1

T1

23

T2

23

T3

12

values[0x1]

all_enables

biggest_size

136781

1

T1

19

T2

20

T3

11