Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
21480283 |
21311729 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21480283 |
21311729 |
0 |
0 |
T1 |
12382 |
12293 |
0 |
0 |
T2 |
4087 |
3919 |
0 |
0 |
T3 |
1877 |
1811 |
0 |
0 |
T10 |
49974 |
42917 |
0 |
0 |
T13 |
3905 |
3826 |
0 |
0 |
T14 |
829 |
752 |
0 |
0 |
T15 |
7077 |
6918 |
0 |
0 |
T16 |
5815 |
5732 |
0 |
0 |
T17 |
4927 |
4859 |
0 |
0 |
T18 |
18982 |
18899 |
0 |
0 |