Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23291839	15317	0	0
attest_sw_binding_0_rd_A	23291839	2992	0	0
attest_sw_binding_1_rd_A	23291839	2961	0	0
attest_sw_binding_2_rd_A	23291839	2944	0	0
attest_sw_binding_3_rd_A	23291839	2850	0	0
attest_sw_binding_4_rd_A	23291839	3025	0	0
attest_sw_binding_5_rd_A	23291839	2975	0	0
attest_sw_binding_6_rd_A	23291839	3213	0	0
attest_sw_binding_7_rd_A	23291839	3168	0	0
intr_enable_rd_A	23291839	3604	0	0
key_version_rd_A	23291839	3180	0	0
max_creator_key_ver_regwen_rd_A	23291839	2951	0	0
max_owner_int_key_ver_regwen_rd_A	23291839	3147	0	0
max_owner_key_ver_regwen_rd_A	23291839	3060	0	0
reseed_interval_regwen_rd_A	23291839	2977	0	0
salt_0_rd_A	23291839	2977	0	0
salt_1_rd_A	23291839	3099	0	0
salt_2_rd_A	23291839	3149	0	0
salt_3_rd_A	23291839	3000	0	0
salt_4_rd_A	23291839	3167	0	0
salt_5_rd_A	23291839	3069	0	0
salt_6_rd_A	23291839	2984	0	0
salt_7_rd_A	23291839	3078	0	0
sealing_sw_binding_0_rd_A	23291839	3084	0	0
sealing_sw_binding_1_rd_A	23291839	2971	0	0
sealing_sw_binding_2_rd_A	23291839	3052	0	0
sealing_sw_binding_3_rd_A	23291839	3067	0	0
sealing_sw_binding_4_rd_A	23291839	3091	0	0
sealing_sw_binding_5_rd_A	23291839	3140	0	0
sealing_sw_binding_6_rd_A	23291839	3096	0	0
sealing_sw_binding_7_rd_A	23291839	3199	0	0
sideload_clear_rd_A	23291839	3054	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	15317	0	0
T18	18982	739	0	0
T22	22238	0	0	0
T25	4502	0	0	0
T26	8993	0	0	0
T27	6883	0	0	0
T35	6166	0	0	0
T48	18638	0	0	0
T52	0	193	0	0
T54	0	60	0	0
T68	0	213	0	0
T80	140738	0	0	0
T81	3284	0	0	0
T82	6881	0	0	0
T98	0	80	0	0
T111	0	62	0	0
T112	0	967	0	0
T113	0	244	0	0
T114	0	124	0	0
T115	0	650	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2992	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	68	0	0
T114	6035	0	0	0
T159	0	14	0	0
T160	0	57	0	0
T161	0	28	0	0
T162	0	19	0	0
T163	0	16	0	0
T164	0	30	0	0
T165	0	32	0	0
T166	0	28	0	0
T167	0	23	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2961	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	57	0	0
T114	6035	0	0	0
T159	0	24	0	0
T160	0	31	0	0
T161	0	16	0	0
T162	0	25	0	0
T163	0	41	0	0
T164	0	42	0	0
T165	0	26	0	0
T166	0	21	0	0
T167	0	15	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2944	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	27	0	0
T114	6035	0	0	0
T159	0	24	0	0
T160	0	54	0	0
T161	0	23	0	0
T162	0	27	0	0
T163	0	23	0	0
T164	0	33	0	0
T165	0	48	0	0
T166	0	31	0	0
T167	0	16	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2850	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	57	0	0
T114	6035	0	0	0
T159	0	12	0	0
T160	0	30	0	0
T161	0	47	0	0
T162	0	23	0	0
T163	0	21	0	0
T164	0	38	0	0
T165	0	15	0	0
T166	0	40	0	0
T167	0	30	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3025	0	0
T19	7542	0	0	0
T24	8597	0	0	0
T38	3946	1	0	0
T53	5089	0	0	0
T105	2682	0	0	0
T113	0	84	0	0
T159	0	21	0	0
T160	0	62	0	0
T161	0	37	0	0
T162	0	18	0	0
T163	0	44	0	0
T164	0	30	0	0
T165	0	30	0	0
T174	0	1	0	0
T175	2971	0	0	0
T176	22888	0	0	0
T177	25371	0	0	0
T178	3638	0	0	0
T179	5103	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2975	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	43	0	0
T114	6035	0	0	0
T159	0	20	0	0
T160	0	51	0	0
T161	0	33	0	0
T162	0	16	0	0
T163	0	32	0	0
T164	0	28	0	0
T165	0	20	0	0
T166	0	27	0	0
T167	0	45	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3213	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	49	0	0
T114	6035	0	0	0
T159	0	14	0	0
T160	0	73	0	0
T161	0	44	0	0
T162	0	19	0	0
T163	0	25	0	0
T164	0	22	0	0
T165	0	23	0	0
T166	0	21	0	0
T167	0	32	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3168	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	59	0	0
T114	6035	0	0	0
T159	0	10	0	0
T160	0	86	0	0
T161	0	20	0	0
T162	0	35	0	0
T163	0	26	0	0
T164	0	27	0	0
T165	0	26	0	0
T166	0	20	0	0
T167	0	35	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3604	0	0
T36	6705	0	0	0
T46	9416	0	0	0
T49	347113	21	0	0
T52	46142	0	0	0
T63	25304	12	0	0
T76	0	27	0	0
T83	13071	0	0	0
T86	22728	0	0	0
T98	50469	0	0	0
T113	0	99	0	0
T116	2744	0	0	0
T117	6026	0	0	0
T159	0	14	0	0
T160	0	25	0	0
T161	0	43	0	0
T162	0	47	0	0
T180	0	37	0	0
T181	0	70	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3180	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	56	0	0
T114	6035	0	0	0
T159	0	32	0	0
T160	0	77	0	0
T161	0	27	0	0
T162	0	26	0	0
T163	0	16	0	0
T164	0	26	0	0
T165	0	34	0	0
T166	0	31	0	0
T167	0	45	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2951	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	56	0	0
T114	6035	0	0	0
T159	0	19	0	0
T160	0	52	0	0
T161	0	20	0	0
T162	0	12	0	0
T163	0	32	0	0
T164	0	19	0	0
T165	0	54	0	0
T166	0	31	0	0
T167	0	27	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3147	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	37	0	0
T114	6035	0	0	0
T159	0	16	0	0
T160	0	49	0	0
T161	0	53	0	0
T162	0	22	0	0
T163	0	38	0	0
T164	0	29	0	0
T165	0	64	0	0
T166	0	37	0	0
T167	0	20	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3060	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	36	0	0
T114	6035	0	0	0
T159	0	15	0	0
T160	0	55	0	0
T161	0	37	0	0
T162	0	25	0	0
T163	0	37	0	0
T164	0	12	0	0
T165	0	31	0	0
T166	0	25	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0
T182	0	8	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2977	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	57	0	0
T114	6035	0	0	0
T159	0	6	0	0
T160	0	77	0	0
T161	0	21	0	0
T162	0	29	0	0
T163	0	11	0	0
T164	0	15	0	0
T165	0	24	0	0
T166	0	35	0	0
T167	0	26	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2977	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	43	0	0
T114	6035	0	0	0
T159	0	4	0	0
T160	0	42	0	0
T161	0	15	0	0
T162	0	26	0	0
T163	0	23	0	0
T164	0	24	0	0
T165	0	31	0	0
T166	0	18	0	0
T167	0	30	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3099	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	62	0	0
T114	6035	0	0	0
T159	0	13	0	0
T160	0	62	0	0
T161	0	36	0	0
T162	0	28	0	0
T163	0	48	0	0
T164	0	29	0	0
T165	0	33	0	0
T166	0	23	0	0
T167	0	25	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3149	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	81	0	0
T114	6035	0	0	0
T159	0	36	0	0
T160	0	37	0	0
T161	0	30	0	0
T162	0	21	0	0
T163	0	28	0	0
T164	0	11	0	0
T165	0	47	0	0
T166	0	25	0	0
T167	0	27	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3000	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	52	0	0
T114	6035	0	0	0
T159	0	11	0	0
T160	0	79	0	0
T161	0	43	0	0
T162	0	17	0	0
T163	0	33	0	0
T164	0	20	0	0
T165	0	22	0	0
T166	0	24	0	0
T167	0	6	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3167	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	79	0	0
T114	6035	0	0	0
T159	0	18	0	0
T160	0	44	0	0
T161	0	46	0	0
T162	0	39	0	0
T163	0	21	0	0
T164	0	29	0	0
T165	0	48	0	0
T166	0	36	0	0
T167	0	17	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3069	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	38	0	0
T114	6035	0	0	0
T159	0	5	0	0
T160	0	45	0	0
T161	0	45	0	0
T162	0	44	0	0
T163	0	15	0	0
T164	0	20	0	0
T165	0	34	0	0
T166	0	9	0	0
T167	0	18	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2984	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	72	0	0
T114	6035	0	0	0
T159	0	13	0	0
T160	0	59	0	0
T161	0	36	0	0
T162	0	29	0	0
T163	0	31	0	0
T164	0	18	0	0
T165	0	15	0	0
T166	0	30	0	0
T167	0	45	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3078	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	47	0	0
T114	6035	0	0	0
T159	0	1	0	0
T160	0	74	0	0
T161	0	21	0	0
T162	0	21	0	0
T163	0	47	0	0
T164	0	20	0	0
T165	0	43	0	0
T166	0	24	0	0
T167	0	7	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3084	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	60	0	0
T114	6035	0	0	0
T159	0	21	0	0
T160	0	37	0	0
T161	0	39	0	0
T162	0	45	0	0
T163	0	11	0	0
T164	0	26	0	0
T165	0	28	0	0
T166	0	21	0	0
T167	0	27	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	2971	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	66	0	0
T114	6035	0	0	0
T159	0	16	0	0
T160	0	46	0	0
T161	0	28	0	0
T162	0	19	0	0
T163	0	32	0	0
T164	0	12	0	0
T165	0	33	0	0
T166	0	30	0	0
T167	0	36	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3052	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	56	0	0
T114	6035	0	0	0
T159	0	10	0	0
T160	0	64	0	0
T161	0	25	0	0
T162	0	21	0	0
T163	0	8	0	0
T164	0	35	0	0
T165	0	24	0	0
T166	0	10	0	0
T167	0	18	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3067	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	52	0	0
T114	6035	0	0	0
T159	0	18	0	0
T160	0	36	0	0
T161	0	39	0	0
T162	0	34	0	0
T163	0	53	0	0
T164	0	20	0	0
T165	0	44	0	0
T166	0	28	0	0
T167	0	28	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3091	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	48	0	0
T114	6035	0	0	0
T159	0	15	0	0
T160	0	35	0	0
T161	0	31	0	0
T162	0	20	0	0
T163	0	13	0	0
T164	0	23	0	0
T165	0	42	0	0
T166	0	13	0	0
T167	0	37	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3140	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	56	0	0
T114	6035	0	0	0
T159	0	24	0	0
T160	0	51	0	0
T161	0	43	0	0
T162	0	26	0	0
T163	0	22	0	0
T164	0	32	0	0
T165	0	29	0	0
T166	0	31	0	0
T167	0	33	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3096	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	72	0	0
T114	6035	0	0	0
T159	0	14	0	0
T160	0	103	0	0
T161	0	24	0	0
T162	0	38	0	0
T163	0	34	0	0
T164	0	29	0	0
T165	0	50	0	0
T166	0	33	0	0
T167	0	34	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3199	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	90	0	0
T114	6035	0	0	0
T159	0	18	0	0
T160	0	86	0	0
T161	0	28	0	0
T162	0	17	0	0
T163	0	38	0	0
T164	0	26	0	0
T165	0	21	0	0
T166	0	26	0	0
T167	0	29	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23291839	3054	0	0
T7	8769	0	0	0
T30	5957	0	0	0
T113	59483	56	0	0
T114	6035	0	0	0
T159	0	11	0	0
T160	0	66	0	0
T161	0	12	0	0
T162	0	13	0	0
T163	0	32	0	0
T164	0	27	0	0
T165	0	54	0	0
T166	0	19	0	0
T167	0	38	0	0
T168	17794	0	0	0
T169	916	0	0	0
T170	7454	0	0	0
T171	4441	0	0	0
T172	4353	0	0	0
T173	9033	0	0	0