Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3698691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

612269

1

T1

650

T2

343

T3

201

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3889966	1			T1	1041		T2	523		T3	3732
values[0x0]	209088	1			T1	120		T2	180		T3	63
values[0x1]	211906	1			T1	111		T2	158		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2524938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1786022

1

T1

789

T2

499

T3

1458

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15694	1			T1	3		T2	2		T3	11
valid_sources[0x01]	13996	1			T1	5		T2	6		T3	5
valid_sources[0x02]	13462	1			T1	4		T2	3		T3	17
valid_sources[0x03]	14080	1			T1	7		T2	1		T3	12
valid_sources[0x04]	14332	1			T1	3		T2	3		T3	9
valid_sources[0x05]	16921	1			T1	7		T2	3		T3	17
valid_sources[0x06]	16217	1			T1	5		T2	1		T3	16
valid_sources[0x07]	63857	1			T1	5		T2	2		T3	17
valid_sources[0x08]	23511	1			T1	1		T2	5		T3	21
valid_sources[0x09]	39610	1			T2	1		T3	13		T14	91
valid_sources[0x0a]	13505	1			T1	6		T3	12		T14	67
valid_sources[0x0b]	15215	1			T1	4		T2	4		T3	27
valid_sources[0x0c]	13528	1			T1	5		T2	5		T3	16
valid_sources[0x0d]	13750	1			T1	9		T2	2		T3	20
valid_sources[0x0e]	14619	1			T1	2		T3	11		T14	53
valid_sources[0x0f]	13624	1			T1	12		T2	5		T3	22
valid_sources[0x10]	13554	1			T1	2		T2	6		T3	21
valid_sources[0x11]	15229	1			T2	4		T3	13		T14	82
valid_sources[0x12]	14301	1			T1	3		T2	4		T3	16
valid_sources[0x13]	13213	1			T1	4		T3	20		T14	215
valid_sources[0x14]	15636	1			T1	2		T2	1		T3	17
valid_sources[0x15]	14323	1			T1	10		T2	6		T3	18
valid_sources[0x16]	14271	1			T1	6		T2	3		T3	16
valid_sources[0x17]	58261	1			T1	4		T2	3		T3	22
valid_sources[0x18]	13501	1			T1	2		T2	6		T3	11
valid_sources[0x19]	17362	1			T1	8		T2	3		T3	14
valid_sources[0x1a]	14945	1			T1	3		T2	1		T3	10
valid_sources[0x1b]	14429	1			T1	3		T2	4		T3	15
valid_sources[0x1c]	14240	1			T1	1		T2	2		T3	21
valid_sources[0x1d]	38932	1			T1	6		T2	1		T3	16
valid_sources[0x1e]	15427	1			T1	18		T2	2		T3	14
valid_sources[0x1f]	14006	1			T1	4		T2	3		T3	12
valid_sources[0x20]	13712	1			T1	4		T2	2		T3	16
valid_sources[0x21]	13938	1			T1	1		T2	2		T3	18
valid_sources[0x22]	14298	1			T1	5		T2	6		T3	18
valid_sources[0x23]	14588	1			T1	4		T2	3		T3	12
valid_sources[0x24]	14590	1			T1	5		T2	2		T3	13
valid_sources[0x25]	14470	1			T1	4		T2	5		T3	6
valid_sources[0x26]	15235	1			T2	2		T3	8		T14	118
valid_sources[0x27]	14018	1			T1	7		T2	3		T3	10
valid_sources[0x28]	13667	1			T1	5		T2	1		T3	12
valid_sources[0x29]	14631	1			T1	3		T2	3		T3	5
valid_sources[0x2a]	16728	1			T1	2		T3	14		T14	44
valid_sources[0x2b]	35946	1			T1	3		T2	6		T3	6
valid_sources[0x2c]	13535	1			T1	3		T2	5		T3	5
valid_sources[0x2d]	14448	1			T1	2		T2	7		T3	16
valid_sources[0x2e]	15725	1			T1	4		T2	1		T3	6
valid_sources[0x2f]	13520	1			T1	2		T2	4		T3	14
valid_sources[0x30]	15142	1			T1	7		T2	8		T3	13
valid_sources[0x31]	13827	1			T1	4		T2	4		T3	20
valid_sources[0x32]	14406	1			T1	9		T2	5		T3	15
valid_sources[0x33]	14448	1			T1	4		T2	3		T3	12
valid_sources[0x34]	16025	1			T1	6		T2	3		T3	16
valid_sources[0x35]	15118	1			T1	2		T2	2		T3	13
valid_sources[0x36]	13841	1			T1	5		T2	5		T3	10
valid_sources[0x37]	13863	1			T1	3		T2	6		T3	23
valid_sources[0x38]	14491	1			T1	5		T2	2		T3	12
valid_sources[0x39]	14996	1			T1	6		T2	9		T3	12
valid_sources[0x3a]	15875	1			T1	8		T2	3		T3	16
valid_sources[0x3b]	14393	1			T1	1		T2	6		T3	16
valid_sources[0x3c]	13674	1			T1	4		T3	20		T14	71
valid_sources[0x3d]	14497	1			T1	3		T2	4		T3	14
valid_sources[0x3e]	13929	1			T1	2		T2	2		T3	13
valid_sources[0x3f]	37090	1			T1	12		T2	3		T3	11
valid_sources[0x40]	17765	1			T1	4		T2	3		T3	13
valid_sources[0x41]	13701	1			T1	7		T2	2		T3	10
valid_sources[0x42]	13642	1			T1	1		T2	4		T3	18
valid_sources[0x43]	18217	1			T1	5		T2	5		T3	16
valid_sources[0x44]	15269	1			T1	3		T2	2		T3	13
valid_sources[0x45]	14390	1			T2	1		T3	14		T14	114
valid_sources[0x46]	16135	1			T2	6		T3	10		T14	124
valid_sources[0x47]	14799	1			T1	11		T2	2		T3	18
valid_sources[0x48]	14467	1			T1	6		T2	4		T3	10
valid_sources[0x49]	13840	1			T1	1		T2	3		T3	12
valid_sources[0x4a]	20676	1			T1	1		T2	1		T3	15
valid_sources[0x4b]	20322	1			T1	11		T2	2		T3	11
valid_sources[0x4c]	14720	1			T1	5		T3	27		T14	165
valid_sources[0x4d]	13795	1			T1	4		T2	5		T3	10
valid_sources[0x4e]	13851	1			T1	1		T2	5		T3	8
valid_sources[0x4f]	14777	1			T1	10		T2	6		T3	14
valid_sources[0x50]	15401	1			T1	6		T2	3		T3	16
valid_sources[0x51]	14601	1			T1	1		T2	2		T3	21
valid_sources[0x52]	13948	1			T1	5		T2	3		T3	22
valid_sources[0x53]	13864	1			T2	1		T3	10		T14	121
valid_sources[0x54]	16204	1			T1	7		T2	4		T3	20
valid_sources[0x55]	31624	1			T1	3		T2	6		T3	19
valid_sources[0x56]	14390	1			T1	6		T2	4		T3	12
valid_sources[0x57]	44099	1			T1	10		T2	3		T3	20
valid_sources[0x58]	13618	1			T1	1		T2	1		T3	20
valid_sources[0x59]	13915	1			T1	10		T2	2		T3	15
valid_sources[0x5a]	13164	1			T1	6		T2	3		T3	16
valid_sources[0x5b]	16154	1			T1	1		T2	4		T3	14
valid_sources[0x5c]	13492	1			T1	4		T2	2		T3	13
valid_sources[0x5d]	15361	1			T1	14		T2	2		T3	20
valid_sources[0x5e]	15387	1			T1	10		T2	4		T3	16
valid_sources[0x5f]	14058	1			T1	4		T2	8		T3	19
valid_sources[0x60]	13605	1			T1	11		T2	3		T3	13
valid_sources[0x61]	29724	1			T2	5		T3	15		T14	75
valid_sources[0x62]	12997	1			T1	11		T2	4		T3	17
valid_sources[0x63]	14163	1			T1	5		T2	2		T3	19
valid_sources[0x64]	13155	1			T1	9		T3	16		T14	15
valid_sources[0x65]	14118	1			T1	6		T2	6		T3	14
valid_sources[0x66]	18611	1			T1	13		T2	2		T3	23
valid_sources[0x67]	14117	1			T2	4		T3	11		T14	10
valid_sources[0x68]	14672	1			T1	6		T2	4		T3	27
valid_sources[0x69]	14550	1			T1	1		T2	6		T3	17
valid_sources[0x6a]	13824	1			T1	1		T2	2		T3	20
valid_sources[0x6b]	13737	1			T1	10		T2	3		T3	14
valid_sources[0x6c]	15522	1			T1	5		T2	5		T3	11
valid_sources[0x6d]	15623	1			T1	2		T2	1		T3	23
valid_sources[0x6e]	14734	1			T1	3		T2	2		T3	14
valid_sources[0x6f]	14067	1			T1	11		T2	3		T3	10
valid_sources[0x70]	14593	1			T1	8		T2	3		T3	10
valid_sources[0x71]	13753	1			T1	16		T2	3		T3	12
valid_sources[0x72]	14192	1			T3	12		T14	143		T15	4
valid_sources[0x73]	15159	1			T1	2		T2	1		T3	19
valid_sources[0x74]	16964	1			T3	10		T14	76		T15	3
valid_sources[0x75]	14437	1			T1	8		T2	3		T3	15
valid_sources[0x76]	59644	1			T1	13		T2	1		T3	13
valid_sources[0x77]	17059	1			T1	2		T2	3		T3	19
valid_sources[0x78]	14850	1			T1	3		T2	5		T3	8
valid_sources[0x79]	14009	1			T1	3		T2	4		T3	15
valid_sources[0x7a]	16258	1			T3	24		T14	127		T15	3
valid_sources[0x7b]	20525	1			T1	10		T2	4		T3	15
valid_sources[0x7c]	14863	1			T1	6		T2	1		T3	14
valid_sources[0x7d]	14329	1			T2	1		T3	12		T14	85
valid_sources[0x7e]	15720	1			T1	4		T2	6		T3	20
valid_sources[0x7f]	18612	1			T1	3		T2	4		T3	13
valid_sources[0x80]	17681	1			T1	8		T2	6		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326805

1

T1

483

T2

115

T3

165

values[0x0]

all_enables

biggest_size

150427

1

T1

94

T2

128

T3

26

values[0x1]

all_enables

biggest_size

135037

1

T1

73

T2

100

T3

10