Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
23284960 |
23107987 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23284960 |
23107987 |
0 |
0 |
T1 |
4305 |
4122 |
0 |
0 |
T2 |
10159 |
10097 |
0 |
0 |
T3 |
44501 |
44446 |
0 |
0 |
T13 |
5398 |
5239 |
0 |
0 |
T14 |
356709 |
355627 |
0 |
0 |
T15 |
4546 |
4466 |
0 |
0 |
T16 |
6340 |
6247 |
0 |
0 |
T17 |
154323 |
154233 |
0 |
0 |
T18 |
1291 |
1196 |
0 |
0 |
T19 |
3816 |
3650 |
0 |
0 |