Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25013031	17244	0	0
attest_sw_binding_0_rd_A	25013031	2980	0	0
attest_sw_binding_1_rd_A	25013031	2930	0	0
attest_sw_binding_2_rd_A	25013031	2862	0	0
attest_sw_binding_3_rd_A	25013031	2944	0	0
attest_sw_binding_4_rd_A	25013031	3055	0	0
attest_sw_binding_5_rd_A	25013031	3064	0	0
attest_sw_binding_6_rd_A	25013031	2938	0	0
attest_sw_binding_7_rd_A	25013031	3026	0	0
intr_enable_rd_A	25013031	3467	0	0
key_version_rd_A	25013031	2925	0	0
max_creator_key_ver_regwen_rd_A	25013031	2839	0	0
max_owner_int_key_ver_regwen_rd_A	25013031	2973	0	0
max_owner_key_ver_regwen_rd_A	25013031	2893	0	0
reseed_interval_regwen_rd_A	25013031	2952	0	0
salt_0_rd_A	25013031	2945	0	0
salt_1_rd_A	25013031	2916	0	0
salt_2_rd_A	25013031	2807	0	0
salt_3_rd_A	25013031	2954	0	0
salt_4_rd_A	25013031	3011	0	0
salt_5_rd_A	25013031	2857	0	0
salt_6_rd_A	25013031	3018	0	0
salt_7_rd_A	25013031	2950	0	0
sealing_sw_binding_0_rd_A	25013031	2758	0	0
sealing_sw_binding_1_rd_A	25013031	2802	0	0
sealing_sw_binding_2_rd_A	25013031	2933	0	0
sealing_sw_binding_3_rd_A	25013031	2898	0	0
sealing_sw_binding_4_rd_A	25013031	2928	0	0
sealing_sw_binding_5_rd_A	25013031	2900	0	0
sealing_sw_binding_6_rd_A	25013031	2906	0	0
sealing_sw_binding_7_rd_A	25013031	2854	0	0
sideload_clear_rd_A	25013031	3023	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	17244	0	0
T32	5408	0	0	0
T44	0	46	0	0
T51	0	700	0	0
T71	0	197	0	0
T100	25645	903	0	0
T101	0	953	0	0
T117	0	129	0	0
T118	0	257	0	0
T119	0	339	0	0
T123	0	728	0	0
T124	0	512	0	0
T125	3159	0	0	0
T126	2045	0	0	0
T127	67409	0	0	0
T128	1220	0	0	0
T129	859	0	0	0
T130	31569	0	0	0
T131	5836	0	0	0
T132	7747	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2980	0	0
T44	0	52	0	0
T69	2534	0	0	0
T117	58008	39	0	0
T118	0	25	0	0
T139	0	51	0	0
T173	0	9	0	0
T174	0	20	0	0
T175	0	5	0	0
T176	0	14	0	0
T177	0	48	0	0
T178	0	22	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2930	0	0
T44	0	28	0	0
T69	2534	0	0	0
T117	58008	35	0	0
T118	0	25	0	0
T139	0	19	0	0
T173	0	18	0	0
T174	0	20	0	0
T175	0	16	0	0
T176	0	38	0	0
T177	0	32	0	0
T178	0	17	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2862	0	0
T44	0	51	0	0
T69	2534	0	0	0
T117	58008	31	0	0
T118	0	36	0	0
T139	0	18	0	0
T173	0	13	0	0
T174	0	33	0	0
T175	0	28	0	0
T176	0	31	0	0
T177	0	74	0	0
T178	0	34	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2944	0	0
T44	0	45	0	0
T69	2534	0	0	0
T117	58008	42	0	0
T118	0	18	0	0
T139	0	49	0	0
T173	0	7	0	0
T174	0	30	0	0
T175	0	18	0	0
T176	0	20	0	0
T177	0	45	0	0
T178	0	34	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3055	0	0
T44	0	59	0	0
T69	2534	0	0	0
T117	58008	46	0	0
T118	0	24	0	0
T139	0	30	0	0
T173	0	12	0	0
T174	0	34	0	0
T175	0	14	0	0
T176	0	24	0	0
T177	0	62	0	0
T178	0	21	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3064	0	0
T44	0	41	0	0
T69	2534	0	0	0
T117	58008	32	0	0
T118	0	44	0	0
T139	0	79	0	0
T173	0	26	0	0
T174	0	21	0	0
T175	0	5	0	0
T176	0	16	0	0
T177	0	56	0	0
T178	0	14	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2938	0	0
T44	0	53	0	0
T69	2534	0	0	0
T117	58008	23	0	0
T118	0	31	0	0
T139	0	58	0	0
T173	0	10	0	0
T174	0	29	0	0
T175	0	15	0	0
T176	0	21	0	0
T177	0	65	0	0
T178	0	22	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3026	0	0
T44	0	82	0	0
T69	2534	0	0	0
T117	58008	15	0	0
T118	0	22	0	0
T139	0	23	0	0
T173	0	29	0	0
T174	0	37	0	0
T175	0	13	0	0
T176	0	32	0	0
T177	0	39	0	0
T178	0	29	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3467	0	0
T6	7894	0	0	0
T25	21199	0	0	0
T44	0	95	0	0
T84	10904	0	0	0
T117	0	28	0	0
T118	0	35	0	0
T136	4903	0	0	0
T173	0	32	0	0
T174	0	38	0	0
T175	0	18	0	0
T187	37956	8	0	0
T188	0	20	0	0
T189	0	30	0	0
T190	0	14	0	0
T191	110138	0	0	0
T192	4929	0	0	0
T193	4794	0	0	0
T194	4265	0	0	0
T195	2604	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2925	0	0
T44	0	48	0	0
T69	2534	0	0	0
T117	58008	35	0	0
T118	0	21	0	0
T139	0	19	0	0
T173	0	13	0	0
T174	0	28	0	0
T175	0	3	0	0
T176	0	18	0	0
T177	0	70	0	0
T178	0	16	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2839	0	0
T44	0	71	0	0
T69	2534	0	0	0
T117	58008	32	0	0
T118	0	19	0	0
T139	0	26	0	0
T173	0	29	0	0
T174	0	18	0	0
T175	0	8	0	0
T176	0	20	0	0
T177	0	42	0	0
T178	0	9	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2973	0	0
T44	0	57	0	0
T69	2534	0	0	0
T117	58008	39	0	0
T118	0	18	0	0
T139	0	29	0	0
T173	0	26	0	0
T174	0	46	0	0
T175	0	14	0	0
T176	0	27	0	0
T177	0	46	0	0
T178	0	32	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2893	0	0
T44	0	34	0	0
T69	2534	0	0	0
T117	58008	33	0	0
T118	0	33	0	0
T139	0	32	0	0
T173	0	16	0	0
T174	0	38	0	0
T175	0	12	0	0
T176	0	30	0	0
T177	0	43	0	0
T178	0	27	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2952	0	0
T44	0	44	0	0
T69	2534	0	0	0
T117	58008	6	0	0
T118	0	23	0	0
T139	0	13	0	0
T173	0	30	0	0
T174	0	20	0	0
T175	0	23	0	0
T176	0	22	0	0
T177	0	51	0	0
T178	0	26	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2945	0	0
T44	0	43	0	0
T69	2534	0	0	0
T117	58008	20	0	0
T118	0	27	0	0
T139	0	55	0	0
T173	0	17	0	0
T174	0	19	0	0
T175	0	16	0	0
T176	0	32	0	0
T177	0	41	0	0
T178	0	20	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2916	0	0
T44	0	53	0	0
T69	2534	0	0	0
T117	58008	7	0	0
T118	0	47	0	0
T139	0	41	0	0
T173	0	23	0	0
T174	0	26	0	0
T175	0	13	0	0
T176	0	42	0	0
T177	0	28	0	0
T178	0	23	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2807	0	0
T44	0	44	0	0
T69	2534	0	0	0
T117	58008	30	0	0
T118	0	21	0	0
T139	0	10	0	0
T173	0	15	0	0
T174	0	40	0	0
T175	0	11	0	0
T176	0	21	0	0
T177	0	39	0	0
T178	0	23	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2954	0	0
T44	0	62	0	0
T69	2534	0	0	0
T117	58008	12	0	0
T118	0	34	0	0
T139	0	24	0	0
T173	0	13	0	0
T174	0	21	0	0
T175	0	19	0	0
T176	0	17	0	0
T177	0	59	0	0
T178	0	29	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3011	0	0
T44	0	75	0	0
T69	2534	0	0	0
T117	58008	35	0	0
T118	0	15	0	0
T139	0	48	0	0
T173	0	18	0	0
T174	0	23	0	0
T175	0	26	0	0
T176	0	31	0	0
T177	0	83	0	0
T178	0	19	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2857	0	0
T44	0	51	0	0
T69	2534	0	0	0
T117	58008	33	0	0
T118	0	14	0	0
T139	0	34	0	0
T173	0	12	0	0
T174	0	25	0	0
T175	0	4	0	0
T176	0	20	0	0
T177	0	64	0	0
T178	0	10	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3018	0	0
T44	0	32	0	0
T69	2534	0	0	0
T117	58008	32	0	0
T118	0	31	0	0
T139	0	56	0	0
T173	0	16	0	0
T174	0	8	0	0
T175	0	11	0	0
T176	0	19	0	0
T177	0	71	0	0
T178	0	36	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2950	0	0
T44	0	39	0	0
T69	2534	0	0	0
T117	58008	40	0	0
T118	0	38	0	0
T139	0	40	0	0
T173	0	6	0	0
T174	0	10	0	0
T175	0	22	0	0
T176	0	29	0	0
T177	0	53	0	0
T178	0	25	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2758	0	0
T44	0	36	0	0
T69	2534	0	0	0
T117	58008	31	0	0
T118	0	22	0	0
T139	0	49	0	0
T173	0	7	0	0
T174	0	27	0	0
T175	0	10	0	0
T176	0	27	0	0
T177	0	72	0	0
T178	0	19	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2802	0	0
T44	0	60	0	0
T69	2534	0	0	0
T117	58008	42	0	0
T118	0	23	0	0
T139	0	24	0	0
T173	0	24	0	0
T174	0	28	0	0
T175	0	16	0	0
T176	0	18	0	0
T177	0	57	0	0
T178	0	23	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2933	0	0
T44	0	61	0	0
T69	2534	0	0	0
T117	58008	41	0	0
T118	0	21	0	0
T139	0	29	0	0
T173	0	8	0	0
T174	0	43	0	0
T175	0	17	0	0
T176	0	16	0	0
T177	0	57	0	0
T178	0	18	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2898	0	0
T44	0	54	0	0
T69	2534	0	0	0
T117	58008	10	0	0
T118	0	25	0	0
T139	0	55	0	0
T173	0	19	0	0
T174	0	13	0	0
T175	0	22	0	0
T176	0	30	0	0
T177	0	53	0	0
T178	0	18	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2928	0	0
T44	0	54	0	0
T69	2534	0	0	0
T117	58008	11	0	0
T118	0	36	0	0
T139	0	41	0	0
T173	0	7	0	0
T174	0	17	0	0
T175	0	17	0	0
T176	0	31	0	0
T177	0	60	0	0
T178	0	12	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2900	0	0
T44	0	48	0	0
T69	2534	0	0	0
T117	58008	22	0	0
T118	0	20	0	0
T139	0	66	0	0
T173	0	28	0	0
T174	0	24	0	0
T175	0	11	0	0
T176	0	32	0	0
T177	0	61	0	0
T178	0	20	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2906	0	0
T44	0	44	0	0
T69	2534	0	0	0
T117	58008	18	0	0
T118	0	18	0	0
T139	0	54	0	0
T173	0	18	0	0
T174	0	35	0	0
T175	0	22	0	0
T176	0	27	0	0
T177	0	52	0	0
T178	0	20	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	2854	0	0
T44	0	42	0	0
T69	2534	0	0	0
T117	58008	28	0	0
T118	0	38	0	0
T139	0	56	0	0
T173	0	16	0	0
T174	0	34	0	0
T175	0	13	0	0
T176	0	24	0	0
T177	0	48	0	0
T178	0	11	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25013031	3023	0	0
T44	0	51	0	0
T69	2534	0	0	0
T117	58008	25	0	0
T118	0	45	0	0
T139	0	37	0	0
T173	0	34	0	0
T174	0	21	0	0
T175	0	12	0	0
T176	0	23	0	0
T177	0	58	0	0
T178	0	25	0	0
T179	12366	0	0	0
T180	3303	0	0	0
T181	4198	0	0	0
T182	225783	0	0	0
T183	3988	0	0	0
T184	5408	0	0	0
T185	6128	0	0	0
T186	3656	0	0	0