Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4109763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

596464

1

T1

199

T2

241

T3

196

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4298820	1			T1	444		T2	512		T3	480
values[0x0]	201608	1			T1	68		T2	83		T3	59
values[0x1]	205799	1			T1	85		T2	84		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2797486	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1908741

1

T1

305

T2

370

T3

299

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14478	1			T1	4		T12	6		T13	2
valid_sources[0x01]	15791	1			T3	4		T12	5		T13	5
valid_sources[0x02]	15645	1			T1	4		T3	1		T13	6
valid_sources[0x03]	13520	1			T1	4		T3	2		T12	2
valid_sources[0x04]	14633	1			T1	4		T3	2		T12	5
valid_sources[0x05]	24415	1			T1	2		T3	6		T13	1
valid_sources[0x06]	13535	1			T1	1		T3	6		T12	1
valid_sources[0x07]	18387	1			T1	4		T3	4		T12	3
valid_sources[0x08]	13249	1			T1	4		T3	3		T12	1
valid_sources[0x09]	17762	1			T3	2		T12	8		T13	3
valid_sources[0x0a]	16568	1			T1	2		T3	3		T12	3
valid_sources[0x0b]	14535	1			T1	1		T3	4		T12	6
valid_sources[0x0c]	15718	1			T1	2		T3	2		T13	12
valid_sources[0x0d]	19142	1			T3	2		T12	3		T13	4
valid_sources[0x0e]	14456	1			T1	1		T3	5		T12	11
valid_sources[0x0f]	13131	1			T1	3		T3	3		T12	7
valid_sources[0x10]	13933	1			T3	1		T12	5		T13	5
valid_sources[0x11]	13462	1			T1	11		T12	4		T13	5
valid_sources[0x12]	15162	1			T1	7		T3	4		T12	3
valid_sources[0x13]	19423	1			T1	3		T15	19		T16	2
valid_sources[0x14]	15833	1			T1	5		T3	2		T12	8
valid_sources[0x15]	13918	1			T1	3		T3	6		T12	8
valid_sources[0x16]	15089	1			T1	1		T3	3		T12	2
valid_sources[0x17]	13808	1			T3	2		T12	4		T13	4
valid_sources[0x18]	13843	1			T1	2		T3	2		T12	3
valid_sources[0x19]	21247	1			T1	5		T12	3		T13	5
valid_sources[0x1a]	13920	1			T1	5		T3	4		T13	3
valid_sources[0x1b]	14317	1			T1	2		T3	1		T12	5
valid_sources[0x1c]	14546	1			T1	8		T3	5		T12	1
valid_sources[0x1d]	13138	1			T1	5		T3	2		T12	7
valid_sources[0x1e]	18438	1			T1	2		T3	2		T12	10
valid_sources[0x1f]	17195	1			T1	2		T3	3		T15	6
valid_sources[0x20]	14018	1			T1	1		T3	2		T12	1
valid_sources[0x21]	13866	1			T1	1		T3	3		T12	6
valid_sources[0x22]	13652	1			T1	3		T12	6		T13	6
valid_sources[0x23]	15854	1			T1	3		T3	2		T13	8
valid_sources[0x24]	23000	1			T3	3		T12	1		T13	1
valid_sources[0x25]	14258	1			T1	1		T3	2		T12	5
valid_sources[0x26]	19696	1			T1	5		T3	1		T12	2
valid_sources[0x27]	17499	1			T1	3		T3	2		T12	6
valid_sources[0x28]	14083	1			T1	2		T3	1		T12	1
valid_sources[0x29]	13569	1			T3	3		T12	1		T13	3
valid_sources[0x2a]	45123	1			T1	2		T3	5		T12	2
valid_sources[0x2b]	14810	1			T3	1		T12	1		T13	4
valid_sources[0x2c]	15636	1			T1	3		T3	2		T12	6
valid_sources[0x2d]	13780	1			T3	3		T12	10		T13	3
valid_sources[0x2e]	16410	1			T1	2		T3	2		T12	2
valid_sources[0x2f]	17149	1			T1	2		T3	3		T12	7
valid_sources[0x30]	13820	1			T1	3		T3	1		T12	2
valid_sources[0x31]	13207	1			T1	2		T3	5		T13	5
valid_sources[0x32]	19343	1			T1	8		T3	2		T12	3
valid_sources[0x33]	16060	1			T3	1		T12	5		T13	3
valid_sources[0x34]	16336	1			T1	4		T3	1		T12	3
valid_sources[0x35]	14995	1			T1	6		T3	1		T12	2
valid_sources[0x36]	16517	1			T1	1		T3	4		T12	1
valid_sources[0x37]	14294	1			T1	1		T3	3		T13	4
valid_sources[0x38]	13442	1			T3	1		T13	8		T15	9
valid_sources[0x39]	13275	1			T1	2		T3	2		T12	1
valid_sources[0x3a]	16286	1			T3	2		T13	2		T15	14
valid_sources[0x3b]	13682	1			T3	2		T12	3		T13	2
valid_sources[0x3c]	13413	1			T1	1		T3	1		T12	1
valid_sources[0x3d]	14471	1			T3	2		T12	1		T13	7
valid_sources[0x3e]	27087	1			T3	3		T13	2		T15	13
valid_sources[0x3f]	13913	1			T1	5		T3	2		T12	2
valid_sources[0x40]	14154	1			T3	3		T12	2		T15	7
valid_sources[0x41]	135549	1			T1	2		T3	2		T12	3
valid_sources[0x42]	15178	1			T1	1		T3	1		T12	1
valid_sources[0x43]	14167	1			T1	2		T3	3		T13	3
valid_sources[0x44]	15168	1			T3	3		T12	3		T13	1
valid_sources[0x45]	14876	1			T1	1		T3	2		T12	7
valid_sources[0x46]	25215	1			T1	1		T3	1		T12	3
valid_sources[0x47]	13782	1			T1	4		T3	2		T13	4
valid_sources[0x48]	66379	1			T1	7		T3	1		T13	1
valid_sources[0x49]	13395	1			T1	5		T12	3		T13	6
valid_sources[0x4a]	15168	1			T1	1		T13	2		T15	20
valid_sources[0x4b]	13499	1			T1	3		T3	2		T12	1
valid_sources[0x4c]	14686	1			T1	1		T3	3		T12	2
valid_sources[0x4d]	19130	1			T1	1		T12	5		T13	1
valid_sources[0x4e]	21892	1			T1	1		T3	1		T12	6
valid_sources[0x4f]	13785	1			T1	5		T3	2		T13	6
valid_sources[0x50]	19128	1			T1	6		T3	6		T12	5
valid_sources[0x51]	15055	1			T1	1		T3	1		T12	2
valid_sources[0x52]	15812	1			T3	5		T12	6		T13	10
valid_sources[0x53]	16196	1			T1	7		T12	2		T13	10
valid_sources[0x54]	17506	1			T3	4		T13	2		T15	16
valid_sources[0x55]	15089	1			T1	8		T3	1		T12	5
valid_sources[0x56]	41841	1			T1	1		T13	1		T15	12
valid_sources[0x57]	14330	1			T1	1		T3	4		T13	3
valid_sources[0x58]	13500	1			T1	3		T3	1		T13	3
valid_sources[0x59]	13641	1			T1	1		T3	1		T12	9
valid_sources[0x5a]	17806	1			T1	5		T3	3		T12	1
valid_sources[0x5b]	20666	1			T1	5		T3	1		T12	7
valid_sources[0x5c]	17103	1			T3	3		T12	4		T15	13
valid_sources[0x5d]	14138	1			T1	3		T3	3		T13	4
valid_sources[0x5e]	60176	1			T1	1		T12	1		T13	6
valid_sources[0x5f]	22857	1			T1	6		T3	4		T12	3
valid_sources[0x60]	15121	1			T1	4		T12	2		T13	4
valid_sources[0x61]	13433	1			T1	7		T3	3		T13	3
valid_sources[0x62]	14907	1			T1	2		T3	1		T13	4
valid_sources[0x63]	25649	1			T1	1		T3	3		T12	3
valid_sources[0x64]	14866	1			T1	5		T3	2		T12	4
valid_sources[0x65]	12998	1			T1	9		T3	2		T12	3
valid_sources[0x66]	12981	1			T1	2		T3	3		T12	6
valid_sources[0x67]	13234	1			T1	2		T3	4		T12	2
valid_sources[0x68]	13217	1			T3	4		T12	5		T13	4
valid_sources[0x69]	14262	1			T1	2		T3	7		T13	8
valid_sources[0x6a]	13995	1			T1	1		T3	4		T12	3
valid_sources[0x6b]	23884	1			T1	2		T3	4		T12	5
valid_sources[0x6c]	13813	1			T3	1		T12	1		T13	5
valid_sources[0x6d]	16024	1			T3	4		T12	1		T13	10
valid_sources[0x6e]	15797	1			T1	3		T3	4		T12	9
valid_sources[0x6f]	18237	1			T1	3		T3	1		T13	7
valid_sources[0x70]	22903	1			T3	3		T12	3		T13	2
valid_sources[0x71]	13761	1			T1	2		T3	3		T12	1
valid_sources[0x72]	14867	1			T3	2		T12	4		T13	9
valid_sources[0x73]	13073	1			T3	2		T13	1		T15	7
valid_sources[0x74]	14650	1			T3	3		T12	11		T13	4
valid_sources[0x75]	13028	1			T3	1		T12	1		T13	7
valid_sources[0x76]	15215	1			T1	1		T3	6		T12	4
valid_sources[0x77]	14363	1			T1	2		T13	3		T15	14
valid_sources[0x78]	13930	1			T3	3		T12	1		T13	4
valid_sources[0x79]	21423	1			T3	1		T12	2		T13	5
valid_sources[0x7a]	15367	1			T1	4		T3	2		T12	1
valid_sources[0x7b]	16857	1			T13	1		T15	20		T16	9
valid_sources[0x7c]	28948	1			T13	3		T15	11		T16	5
valid_sources[0x7d]	26647	1			T1	5		T3	2		T13	2
valid_sources[0x7e]	14181	1			T1	1		T3	2		T12	6
valid_sources[0x7f]	20320	1			T1	2		T3	2		T12	2
valid_sources[0x80]	16339	1			T1	12		T3	1		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

321146

1

T1

87

T2

120

T3

161

values[0x0]

all_enables

biggest_size

144671

1

T1

51

T2

68

T3

30

values[0x1]

all_enables

biggest_size

130647

1

T1

61

T2

53

T3

5