SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[keymgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 4751308 | 0 | T1 | 597 | T2 | 679 | T3 | 579 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4751090 | 1 | T1 | 597 | T2 | 679 | T3 | 579 | ||||
values[1] | 24 | 1 | T12 | 1 | T37 | 1 | T369 | 1 | ||||
values[2] | 7 | 1 | T370 | 1 | T130 | 1 | T140 | 1 | ||||
values[3] | 112 | 1 | T114 | 1 | T371 | 1 | T372 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4751094 | 1 | T1 | 597 | T2 | 679 | T3 | 579 | ||||
values[1] | 20 | 1 | T42 | 1 | T373 | 1 | T131 | 1 | ||||
values[2] | 6 | 1 | T141 | 1 | T374 | 1 | T144 | 2 | ||||
values[3] | 111 | 1 | T375 | 1 | T183 | 1 | T376 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4750988 | 1 | T1 | 597 | T2 | 679 | T3 | 579 | ||||
auto[TlIntgErrCmd] | 106 | 1 | T37 | 1 | T51 | 1 | T191 | 1 | ||||
auto[TlIntgErrData] | 102 | 1 | T375 | 1 | T57 | 1 | T183 | 1 | ||||
auto[TlIntgErrBoth] | 112 | 1 | T12 | 1 | T42 | 1 | T52 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |