Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 7929 7929 0 0
OutputsKnown_A 238606740 237022290 0 0
gen_no_flops.OutputDelay_A 238606740 237022290 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7929 7929 0 0
T1 9 9 0 0
T2 9 9 0 0
T3 9 9 0 0
T12 9 9 0 0
T13 9 9 0 0
T14 9 9 0 0
T15 9 9 0 0
T16 9 9 0 0
T17 9 9 0 0
T18 9 9 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238606740 237022290 0 0
T1 19368 18711 0 0
T2 76734 76185 0 0
T3 65142 64242 0 0
T12 104544 103050 0 0
T13 32895 31689 0 0
T14 7722 7020 0 0
T15 342927 342423 0 0
T16 70587 70128 0 0
T17 26883 25857 0 0
T18 169110 168426 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238606740 237022290 0 0
T1 19368 18711 0 0
T2 76734 76185 0 0
T3 65142 64242 0 0
T12 104544 103050 0 0
T13 32895 31689 0 0
T14 7722 7020 0 0
T15 342927 342423 0 0
T16 70587 70128 0 0
T17 26883 25857 0 0
T18 169110 168426 0 0

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 881 881 0 0
OutputsKnown_A 26511860 26335810 0 0
gen_no_flops.OutputDelay_A 26511860 26335810 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 881 881 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26511860 26335810 0 0
T1 2152 2079 0 0
T2 8526 8465 0 0
T3 7238 7138 0 0
T12 11616 11450 0 0
T13 3655 3521 0 0
T14 858 780 0 0
T15 38103 38047 0 0
T16 7843 7792 0 0
T17 2987 2873 0 0
T18 18790 18714 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%