Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
26511860 |
26335810 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26511860 |
26335810 |
0 |
0 |
T1 |
2152 |
2079 |
0 |
0 |
T2 |
8526 |
8465 |
0 |
0 |
T3 |
7238 |
7138 |
0 |
0 |
T12 |
11616 |
11450 |
0 |
0 |
T13 |
3655 |
3521 |
0 |
0 |
T14 |
858 |
780 |
0 |
0 |
T15 |
38103 |
38047 |
0 |
0 |
T16 |
7843 |
7792 |
0 |
0 |
T17 |
2987 |
2873 |
0 |
0 |
T18 |
18790 |
18714 |
0 |
0 |